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From: Michael Rolnik <mrolnik@gmail.com>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, peter.maydell@linaro.org,
	Michael Rolnik <mrolnik@gmail.com>
Subject: [Qemu-devel] [PATCH v5 05/10] target-avr: adding AVR interrupt handling
Date: Thu,  9 Jun 2016 00:11:17 +0300	[thread overview]
Message-ID: <1465420282-68685-6-git-send-email-rolnik@amazon.com> (raw)
In-Reply-To: <1465420282-68685-1-git-send-email-rolnik@amazon.com>

From: Michael Rolnik <mrolnik@gmail.com>

From: Michael Rolnik <rolnik@amazon.com>

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target-avr/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/target-avr/helper.c b/target-avr/helper.c
index ad8f83e..f96fa27 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper.c
@@ -31,11 +31,68 @@
 
 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
-    return  false;
+    CPUClass *cc = CPU_GET_CLASS(cs);
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    bool ret = false;
+
+    if (interrupt_request & CPU_INTERRUPT_RESET) {
+        if (cpu_interrupts_enabled(env)) {
+            cs->exception_index = EXCP_RESET;
+            cc->do_interrupt(cs);
+
+            cs->interrupt_request   &= ~CPU_INTERRUPT_RESET;
+
+            ret = true;
+        }
+    }
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
+            int     index = ctz32(env->intsrc);
+            cs->exception_index = EXCP_INT(index);
+            cc->do_interrupt(cs);
+
+            env->intsrc &= env->intsrc - 1; /* clear the interrupt */
+            cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+
+            ret = true;
+        }
+    }
+    return ret;
 }
 
 void avr_cpu_do_interrupt(CPUState *cs)
 {
+    AVRCPU         *cpu = AVR_CPU(cs);
+    CPUAVRState    *env = &cpu->env;
+
+    uint32_t ret = env->pc_w;
+    int vector = 0;
+    int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
+    int base = 0;    /* TODO: where to get it */
+
+    if (cs->exception_index == EXCP_RESET) {
+        vector = 0;
+    } else if (env->intsrc != 0) {
+        vector = ctz32(env->intsrc) + 1;
+    }
+
+    if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
+        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
+        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
+        stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16);
+    } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
+        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
+        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
+    } else {
+        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
+    }
+
+    env->pc_w = base + vector * size;
+    env->sregI = 0;    /*  clear Global Interrupt Flag */
+
+    cs->exception_index = -1;
 }
 
 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
-- 
2.4.9 (Apple Git-60)

  parent reply	other threads:[~2016-06-08 21:12 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-08 21:11 [Qemu-devel] [PATCH v5 00/10] 8bit AVR cores Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 02/10] target-avr: adding AVR CPU features/flavors Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 03/10] target-avr: adding a sample AVR board Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 04/10] target-avr: adding instructions encodings Michael Rolnik
2016-06-08 21:11 ` Michael Rolnik [this message]
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 07/10] target-avr: adding instruction decoder Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 08/10] target-avr: adding instruction translation Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 09/10] target-avr: updating translate.c to use instructions translation Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 10/10] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features Michael Rolnik

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