All of lore.kernel.org
 help / color / mirror / Atom feed
From: Michael Rolnik <mrolnik@gmail.com>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, peter.maydell@linaro.org,
	Michael Rolnik <mrolnik@gmail.com>
Subject: [Qemu-devel] [PATCH v5 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions
Date: Thu,  9 Jun 2016 00:11:18 +0300	[thread overview]
Message-ID: <1465420282-68685-7-git-send-email-rolnik@amazon.com> (raw)
In-Reply-To: <1465420282-68685-1-git-send-email-rolnik@amazon.com>

From: Michael Rolnik <mrolnik@gmail.com>

From: Michael Rolnik <rolnik@amazon.com>

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target-avr/helper.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++++----
 target-avr/helper.h |   5 ++
 2 files changed, 140 insertions(+), 10 deletions(-)

diff --git a/target-avr/helper.c b/target-avr/helper.c
index f96fa27..9e2b52a 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper.c
@@ -42,14 +42,14 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
             cs->exception_index = EXCP_RESET;
             cc->do_interrupt(cs);
 
-            cs->interrupt_request   &= ~CPU_INTERRUPT_RESET;
+            cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
 
             ret = true;
         }
     }
     if (interrupt_request & CPU_INTERRUPT_HARD) {
         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
-            int     index = ctz32(env->intsrc);
+            int index = ctz32(env->intsrc);
             cs->exception_index = EXCP_INT(index);
             cc->do_interrupt(cs);
 
@@ -64,8 +64,8 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 
 void avr_cpu_do_interrupt(CPUState *cs)
 {
-    AVRCPU         *cpu = AVR_CPU(cs);
-    CPUAVRState    *env = &cpu->env;
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
 
     uint32_t ret = env->pc_w;
     int vector = 0;
@@ -79,14 +79,14 @@ void avr_cpu_do_interrupt(CPUState *cs)
     }
 
     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
-        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
-        stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16);
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >>  8);
+        cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
-        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >>  8);
     } else {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
     }
 
     env->pc_w = base + vector * size;
@@ -133,6 +133,28 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int is_write,
 
     tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, page_size);
 }
+void helper_sleep(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    cs->exception_index = EXCP_HLT;
+    cpu_loop_exit(cs);
+}
+void helper_unsupported(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    /*
+        I count not find what happens on the real platform, so
+        it's EXCP_DEBUG for meanwhile
+    */
+    cs->exception_index = EXCP_DEBUG;
+    if (qemu_loglevel_mask(LOG_UNIMP)) {
+        qemu_log("UNSUPPORTED\n");
+        cpu_dump_state(cs, qemu_logfile, fprintf, 0);
+    }
+    cpu_loop_exit(cs);
+}
 
 void helper_debug(CPUAVRState *env)
 {
@@ -142,3 +164,106 @@ void helper_debug(CPUAVRState *env)
     cpu_loop_exit(cs);
 }
 
+void helper_wdr(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    /*
+        WD is not implemented yet, placeholder
+    */
+    cs->exception_index = EXCP_DEBUG;
+    cpu_loop_exit(cs);
+}
+
+target_ulong helper_inb(CPUAVRState *env, uint32_t port)
+{
+    qemu_log("in: io[%02x]\n", port);
+
+    switch (port) {
+        case    0x38: {
+            return  0xff & (env->rampD >> 16);  /*  RAMPD   */
+        }
+        case    0x39: {
+            return  0xff & (env->rampX >> 16);  /*  RAMPX   */
+        }
+        case    0x3a: {
+            return  0xff & (env->rampY >> 16);  /*  RAMPY   */
+        }
+        case    0x3b: {
+            return  0xff & (env->rampZ >> 16);  /*  RAMPZ   */
+        }
+        case    0x3c: {
+            return  0xff & (env->eind  >> 16);  /*  EIND    */
+        }
+        case    0x3d: {                         /*  SPL     */
+            return  env->sp & 0x00ff;
+        }
+        case    0x3e: {                         /*  SPH     */
+            return  env->sp >> 8;
+        }
+        case    0x3f: {                         /*  SREG    */
+            return cpu_get_sreg(env);
+        }
+    }
+    return  0;
+}
+
+void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
+{
+    qemu_log("out:%02x -> io[%02x]\n", data, port);
+
+    data    &= 0x000000ff;
+
+    switch (port) {
+        case    0x04: {
+            qemu_irq    irq;
+            CPUState   *cpu = CPU(avr_env_get_cpu(env));
+            irq = qdev_get_gpio_in(DEVICE(cpu), 3);
+            qemu_set_irq(irq, 1);
+            break;
+        }
+        case    0x38: {
+            if (avr_feature(env, AVR_FEATURE_RAMPD)) {
+                env->rampD = (data & 0xff) << 16;   /*  RAMPD   */
+            }
+            break;
+        }
+        case    0x39: {
+            if (avr_feature(env, AVR_FEATURE_RAMPX)) {
+                env->rampX = (data & 0xff) << 16;   /*  RAMPX   */
+            }
+            break;
+        }
+        case    0x3a: {
+            if (avr_feature(env, AVR_FEATURE_RAMPY)) {
+                env->rampY = (data & 0xff) << 16;   /*  RAMPY   */
+            }
+            break;
+        }
+        case    0x3b: {
+            if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
+                env->rampZ = (data & 0xff) << 16;   /*  RAMPZ   */
+            }
+            break;
+        }
+        case    0x3c: {
+            env->eind = (data & 0xff) << 16;        /*  EIDN    */
+            break;
+        }
+        case    0x3d: {                             /*  SPL */
+            env->sp = (env->sp & 0xff00) | (data);
+            break;
+        }
+        case    0x3e: {                             /*  SPH */
+            if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
+                env->sp = (env->sp & 0x00ff) | (data << 8);
+            }
+            break;
+        }
+        case    0x3f: {                             /*  SREG */
+            cpu_set_sreg(env, data);
+            break;
+        }
+    }
+}
+
diff --git a/target-avr/helper.h b/target-avr/helper.h
index b5ef3bf..82f440a 100644
--- a/target-avr/helper.h
+++ b/target-avr/helper.h
@@ -18,4 +18,9 @@
  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  */
 
+DEF_HELPER_1(wdr, void, env)
 DEF_HELPER_1(debug, void, env)
+DEF_HELPER_1(sleep, void, env)
+DEF_HELPER_1(unsupported, void, env)
+DEF_HELPER_3(outb, void, env, i32, i32)
+DEF_HELPER_2(inb, tl, env, i32)
-- 
2.4.9 (Apple Git-60)

  parent reply	other threads:[~2016-06-08 21:11 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-08 21:11 [Qemu-devel] [PATCH v5 00/10] 8bit AVR cores Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 02/10] target-avr: adding AVR CPU features/flavors Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 03/10] target-avr: adding a sample AVR board Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 04/10] target-avr: adding instructions encodings Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 05/10] target-avr: adding AVR interrupt handling Michael Rolnik
2016-06-08 21:11 ` Michael Rolnik [this message]
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 07/10] target-avr: adding instruction decoder Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 08/10] target-avr: adding instruction translation Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 09/10] target-avr: updating translate.c to use instructions translation Michael Rolnik
2016-06-08 21:11 ` [Qemu-devel] [PATCH v5 10/10] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features Michael Rolnik

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1465420282-68685-7-git-send-email-rolnik@amazon.com \
    --to=mrolnik@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=rth@twiddle.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.