* [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence
@ 2016-09-07 12:39 Andy Shevchenko
2016-09-07 14:53 ` Bryan O'Donoghue
2016-09-08 6:28 ` [tip:x86/platform] " tip-bot for Andy Shevchenko
0 siblings, 2 replies; 4+ messages in thread
From: Andy Shevchenko @ 2016-09-07 12:39 UTC (permalink / raw)
To: Ingo Molnar, linux-kernel, Thomas Gleixner, H . Peter Anvin, x86
Cc: Andy Shevchenko
Tell SCU that we are about powering off the device.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
v3:
- fix type of variable (lkp)
v2:
- change abbrevation from PMU to PWRMU
arch/x86/include/asm/intel-mid.h | 2 ++
arch/x86/include/asm/intel_scu_ipc.h | 2 ++
arch/x86/platform/intel-mid/intel-mid.c | 5 +++++
arch/x86/platform/intel-mid/pwr.c | 24 +++++++++++++++++++++++-
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
index 9d6b097..5b6753d 100644
--- a/arch/x86/include/asm/intel-mid.h
+++ b/arch/x86/include/asm/intel-mid.h
@@ -18,6 +18,8 @@
extern int intel_mid_pci_init(void);
extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
+extern void intel_mid_pwr_power_off(void);
+
#define INTEL_MID_PWR_LSS_OFFSET 4
#define INTEL_MID_PWR_LSS_TYPE (1 << 7)
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 925b605..4fb1d0a 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -3,6 +3,8 @@
#include <linux/notifier.h>
+#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */
+
#define IPCMSG_WARM_RESET 0xF0
#define IPCMSG_COLD_RESET 0xF1
#define IPCMSG_SOFT_RESET 0xF2
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index ce119d2..7850128 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -70,6 +70,11 @@ EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
static void intel_mid_power_off(void)
{
+ /* Shut down South Complex via PWRMU */
+ intel_mid_pwr_power_off();
+
+ /* Only for Tangier, the rest will ignore this command */
+ intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
};
static void intel_mid_reboot(void)
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 0548741..2dfe998 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -48,7 +48,15 @@
#define PM_CMD_CM_IMMEDIATE (1 << 9)
#define PM_CMD_CM_DELAY (2 << 9)
#define PM_CMD_CM_TRIGGER (3 << 9)
-#define PM_CMD_D3cold (1 << 21)
+
+/* System states */
+#define PM_CMD_SYS_STATE_S5 (5 << 16)
+
+/* Trigger variants */
+#define PM_CMD_CFG_TRIGGER_NC (3 << 19)
+
+/* Message to wait for TRIGGER_NC case */
+#define TRIGGER_NC_MSG_2 (2 << 22)
/* List of commands */
#define CMD_SET_CFG 0x01
@@ -264,6 +272,20 @@ int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
}
EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
+void intel_mid_pwr_power_off(void)
+{
+ struct mid_pwr *pwr = midpwr;
+ u32 cmd = PM_CMD_SYS_STATE_S5 |
+ PM_CMD_CMD(CMD_SET_CFG) |
+ PM_CMD_CM_TRIGGER |
+ PM_CMD_CFG_TRIGGER_NC |
+ TRIGGER_NC_MSG_2;
+
+ /* Send command to SCU */
+ writel(cmd, pwr->regs + PM_CMD);
+ mid_pwr_wait(pwr);
+}
+
int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
{
int vndr;
--
2.9.3
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence
2016-09-07 12:39 [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence Andy Shevchenko
@ 2016-09-07 14:53 ` Bryan O'Donoghue
2016-09-07 15:08 ` Andy Shevchenko
2016-09-08 6:28 ` [tip:x86/platform] " tip-bot for Andy Shevchenko
1 sibling, 1 reply; 4+ messages in thread
From: Bryan O'Donoghue @ 2016-09-07 14:53 UTC (permalink / raw)
To: Andy Shevchenko, Ingo Molnar, linux-kernel, Thomas Gleixner,
H . Peter Anvin, x86
On Wed, 2016-09-07 at 15:39 +0300, Andy Shevchenko wrote:
> +#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier
> */
Andy, I'm wondering are these magic numbers documented somewhere ?
---
bod
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence
2016-09-07 14:53 ` Bryan O'Donoghue
@ 2016-09-07 15:08 ` Andy Shevchenko
0 siblings, 0 replies; 4+ messages in thread
From: Andy Shevchenko @ 2016-09-07 15:08 UTC (permalink / raw)
To: Bryan O'Donoghue, Ingo Molnar, linux-kernel, Thomas Gleixner,
H . Peter Anvin, x86
On Wed, 2016-09-07 at 15:53 +0100, Bryan O'Donoghue wrote:
> On Wed, 2016-09-07 at 15:39 +0300, Andy Shevchenko wrote:
> >
> > +#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier
> > */
>
> Andy, I'm wondering are these magic numbers documented somewhere ?
This one somewhere in SCU HAS, I can check it later (if I have access to
it).
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply [flat|nested] 4+ messages in thread
* [tip:x86/platform] x86/platform/intel-mid: Implement power off sequence
2016-09-07 12:39 [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence Andy Shevchenko
2016-09-07 14:53 ` Bryan O'Donoghue
@ 2016-09-08 6:28 ` tip-bot for Andy Shevchenko
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Andy Shevchenko @ 2016-09-08 6:28 UTC (permalink / raw)
To: linux-tip-commits
Cc: tglx, andriy.shevchenko, hpa, peterz, linux-kernel, torvalds,
mingo
Commit-ID: bda7b072de999280ef78aaea4335ec58afc4bdb2
Gitweb: http://git.kernel.org/tip/bda7b072de999280ef78aaea4335ec58afc4bdb2
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Wed, 7 Sep 2016 15:39:55 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 8 Sep 2016 08:03:58 +0200
x86/platform/intel-mid: Implement power off sequence
Tell SCU that we are about powering off the device.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20160907123955.21228-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/intel-mid.h | 2 ++
arch/x86/include/asm/intel_scu_ipc.h | 2 ++
arch/x86/platform/intel-mid/intel-mid.c | 5 +++++
arch/x86/platform/intel-mid/pwr.c | 24 +++++++++++++++++++++++-
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
index 9d6b097..5b6753d 100644
--- a/arch/x86/include/asm/intel-mid.h
+++ b/arch/x86/include/asm/intel-mid.h
@@ -18,6 +18,8 @@
extern int intel_mid_pci_init(void);
extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
+extern void intel_mid_pwr_power_off(void);
+
#define INTEL_MID_PWR_LSS_OFFSET 4
#define INTEL_MID_PWR_LSS_TYPE (1 << 7)
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 925b605..4fb1d0a 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -3,6 +3,8 @@
#include <linux/notifier.h>
+#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */
+
#define IPCMSG_WARM_RESET 0xF0
#define IPCMSG_COLD_RESET 0xF1
#define IPCMSG_SOFT_RESET 0xF2
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index ce119d2..7850128 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -70,6 +70,11 @@ EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
static void intel_mid_power_off(void)
{
+ /* Shut down South Complex via PWRMU */
+ intel_mid_pwr_power_off();
+
+ /* Only for Tangier, the rest will ignore this command */
+ intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
};
static void intel_mid_reboot(void)
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 0548741..2dfe998 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -48,7 +48,15 @@
#define PM_CMD_CM_IMMEDIATE (1 << 9)
#define PM_CMD_CM_DELAY (2 << 9)
#define PM_CMD_CM_TRIGGER (3 << 9)
-#define PM_CMD_D3cold (1 << 21)
+
+/* System states */
+#define PM_CMD_SYS_STATE_S5 (5 << 16)
+
+/* Trigger variants */
+#define PM_CMD_CFG_TRIGGER_NC (3 << 19)
+
+/* Message to wait for TRIGGER_NC case */
+#define TRIGGER_NC_MSG_2 (2 << 22)
/* List of commands */
#define CMD_SET_CFG 0x01
@@ -264,6 +272,20 @@ int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
}
EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
+void intel_mid_pwr_power_off(void)
+{
+ struct mid_pwr *pwr = midpwr;
+ u32 cmd = PM_CMD_SYS_STATE_S5 |
+ PM_CMD_CMD(CMD_SET_CFG) |
+ PM_CMD_CM_TRIGGER |
+ PM_CMD_CFG_TRIGGER_NC |
+ TRIGGER_NC_MSG_2;
+
+ /* Send command to SCU */
+ writel(cmd, pwr->regs + PM_CMD);
+ mid_pwr_wait(pwr);
+}
+
int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
{
int vndr;
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-09-08 6:30 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2016-09-07 12:39 [PATCH v3 1/1] x86/platform/intel-mid: Implement power off sequence Andy Shevchenko
2016-09-07 14:53 ` Bryan O'Donoghue
2016-09-07 15:08 ` Andy Shevchenko
2016-09-08 6:28 ` [tip:x86/platform] " tip-bot for Andy Shevchenko
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