* [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
@ 2016-11-01 11:11 Ander Conselvan de Oliveira
2016-11-01 11:36 ` Imre Deak
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-01 11:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Hardware engineers confirmed that writing to it has no effect, as implied by
the FIXME comment.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 4a6164a..e95b291 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
}
- val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
- val &= ~OCL2_LDOFUSE_PWR_DIS;
- /*
- * On PHY1 disable power on the second channel, since no port is
- * connected there. On PHY0 both channels have a port, so leave it
- * enabled.
- * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
- * power down the second channel on PHY0 as well.
- *
- * FIXME: Clarify programming of the following, the register is
- * read-only with bit 6 fixed at 0 at least in stepping A.
- */
- if (!phy_info->dual_channel)
- val |= OCL2_LDOFUSE_PWR_DIS;
- I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
-
if (phy_info->rcomp_phy != -1) {
uint32_t grc_code;
/*
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
2016-11-01 11:11 [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence Ander Conselvan de Oliveira
@ 2016-11-01 11:36 ` Imre Deak
2016-11-02 6:44 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-01 12:16 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-11-02 7:15 ` ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2) Patchwork
2 siblings, 1 reply; 7+ messages in thread
From: Imre Deak @ 2016-11-01 11:36 UTC (permalink / raw)
To: Ander Conselvan de Oliveira, intel-gfx
On ti, 2016-11-01 at 13:11 +0200, Ander Conselvan de Oliveira wrote:
> Hardware engineers confirmed that writing to it has no effect, as implied by
> the FIXME comment.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
You could also remove the corresponding comment
from bxt_ddi_phy_verify_state(), either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 4a6164a..e95b291 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
> }
>
> - val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> - val &= ~OCL2_LDOFUSE_PWR_DIS;
> - /*
> - * On PHY1 disable power on the second channel, since no port is
> - * connected there. On PHY0 both channels have a port, so leave it
> - * enabled.
> - * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
> - * power down the second channel on PHY0 as well.
> - *
> - * FIXME: Clarify programming of the following, the register is
> - * read-only with bit 6 fixed at 0 at least in stepping A.
> - */
> - if (!phy_info->dual_channel)
> - val |= OCL2_LDOFUSE_PWR_DIS;
> - I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> -
> if (phy_info->rcomp_phy != -1) {
> uint32_t grc_code;
> /*
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
2016-11-01 11:36 ` Imre Deak
@ 2016-11-02 6:44 ` Ander Conselvan de Oliveira
0 siblings, 0 replies; 7+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-02 6:44 UTC (permalink / raw)
To: imre.deak, intel-gfx; +Cc: Ander Conselvan de Oliveira
Hardware engineers confirmed that writing to it has no effect, as implied by
the FIXME comment.
v2: Also remove comment from bxt_ddi_phy_verify_state(). (Imre)
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_dpio_phy.c | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 4a6164a..7a8e82d 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
}
- val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
- val &= ~OCL2_LDOFUSE_PWR_DIS;
- /*
- * On PHY1 disable power on the second channel, since no port is
- * connected there. On PHY0 both channels have a port, so leave it
- * enabled.
- * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
- * power down the second channel on PHY0 as well.
- *
- * FIXME: Clarify programming of the following, the register is
- * read-only with bit 6 fixed at 0 at least in stepping A.
- */
- if (!phy_info->dual_channel)
- val |= OCL2_LDOFUSE_PWR_DIS;
- I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
-
if (phy_info->rcomp_phy != -1) {
uint32_t grc_code;
/*
@@ -508,11 +492,6 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
"BXT_PORT_CL2CM_DW6(%d)", phy);
- /*
- * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
- * at least on stepping A this bit is read-only and fixed at 0.
- */
-
if (phy_info->rcomp_phy != -1) {
u32 grc_code = dev_priv->bxt_phy_grc;
--
2.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
2016-11-01 11:11 [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence Ander Conselvan de Oliveira
2016-11-01 11:36 ` Imre Deak
@ 2016-11-01 12:16 ` Patchwork
2016-11-02 7:15 ` ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2) Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2016-11-01 12:16 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
URL : https://patchwork.freedesktop.org/series/14669/
State : warning
== Summary ==
Series 14669v1 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/1/mbox/
Test kms_flip:
Subgroup basic-plain-flip:
pass -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup bad-pipe:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup nonblocking-crc-pipe-a:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (fi-ilk-650)
fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40
fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54
fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23
fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23
fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34
f38d5bab1be4078239d2cf7b20c84a574e522263 drm-intel-nightly: 2016y-11m-01d-11h-22m-30s UTC integration manifest
c5d6745 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2872/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2)
2016-11-01 11:11 [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence Ander Conselvan de Oliveira
2016-11-01 11:36 ` Imre Deak
2016-11-01 12:16 ` ✗ Fi.CI.BAT: warning for " Patchwork
@ 2016-11-02 7:15 ` Patchwork
2016-11-02 7:24 ` Saarinen, Jani
2 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2016-11-02 7:15 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2)
URL : https://patchwork.freedesktop.org/series/14669/
State : warning
== Summary ==
Series 14669v2 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/2/mbox/
Test drv_module_reload_basic:
pass -> DMESG-WARN (fi-skl-6770hq)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-varying-size:
pass -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-3:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup bad-source:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (fi-ilk-650)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (fi-ilk-650)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-ilk-650)
fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54
fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23
fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23
fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:241 pass:226 dwarn:1 dfail:0 fail:0 skip:14
fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34
c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y-11m-01d-16h-36m-25s UTC integration manifest
4a635f6 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2884/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2)
2016-11-02 7:15 ` ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2) Patchwork
@ 2016-11-02 7:24 ` Saarinen, Jani
2016-11-02 7:41 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 7+ messages in thread
From: Saarinen, Jani @ 2016-11-02 7:24 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Conselvan De Oliveira, Ander
> == Series Details ==
>
> Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init
> sequence (rev2)
> URL : https://patchwork.freedesktop.org/series/14669/
> State : warning
>
> == Summary ==
>
> Series 14669v2 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy
> init sequence
> https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/2/mbox/
>
> Test drv_module_reload_basic:
> pass -> DMESG-WARN (fi-skl-6770hq)
Still using IGT 1.16-g5bfbbea that has no Jani's patches. But CI builds done today should have that fix.
> Test kms_cursor_legacy:
> Subgroup basic-busy-flip-before-cursor-varying-size:
> pass -> DMESG-WARN (fi-ilk-650)
> Test kms_pipe_crc_basic:
> Subgroup bad-nb-words-3:
> dmesg-warn -> PASS (fi-ilk-650)
> Subgroup bad-source:
> dmesg-warn -> PASS (fi-ilk-650)
> Subgroup nonblocking-crc-pipe-a-frame-sequence:
> dmesg-warn -> PASS (fi-ilk-650)
> Subgroup nonblocking-crc-pipe-b-frame-sequence:
> pass -> DMESG-WARN (fi-ilk-650)
> Subgroup read-crc-pipe-b:
> pass -> DMESG-WARN (fi-ilk-650)
> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS (fi-ilk-650)
For ILK-650 Dwarns: https://bugs.freedesktop.org/show_bug.cgi?id=98531
> fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54
>
> c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y-
> 11m-01d-16h-36m-25s UTC integration manifest
> 4a635f6 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init
> sequence
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2884/
Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2)
2016-11-02 7:24 ` Saarinen, Jani
@ 2016-11-02 7:41 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 7+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-11-02 7:41 UTC (permalink / raw)
To: Saarinen, Jani, intel-gfx@lists.freedesktop.org
On Wed, 2016-11-02 at 07:24 +0000, Saarinen, Jani wrote:
> >
> > == Series Details ==
> >
> > Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init
> > sequence (rev2)
> > URL : https://patchwork.freedesktop.org/series/14669/
> > State : warning
> >
> > == Summary ==
> >
> > Series 14669v2 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy
> > init sequence
> > https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/2/mbox/
> >
> > Test drv_module_reload_basic:
> > pass -> DMESG-WARN (fi-skl-6770hq)
> Still using IGT 1.16-g5bfbbea that has no Jani's patches. But CI builds done
> today should have that fix.
>
> >
> > Test kms_cursor_legacy:
> > Subgroup basic-busy-flip-before-cursor-varying-size:
> > pass -> DMESG-WARN (fi-ilk-650)
> > Test kms_pipe_crc_basic:
> > Subgroup bad-nb-words-3:
> > dmesg-warn -> PASS (fi-ilk-650)
> > Subgroup bad-source:
> > dmesg-warn -> PASS (fi-ilk-650)
> > Subgroup nonblocking-crc-pipe-a-frame-sequence:
> > dmesg-warn -> PASS (fi-ilk-650)
> > Subgroup nonblocking-crc-pipe-b-frame-sequence:
> > pass -> DMESG-WARN (fi-ilk-650)
> > Subgroup read-crc-pipe-b:
> > pass -> DMESG-WARN (fi-ilk-650)
> > Subgroup suspend-read-crc-pipe-a:
> > dmesg-warn -> PASS (fi-ilk-650)
> For ILK-650 Dwarns: https://bugs.freedesktop.org/show_bug.cgi?id=98531
Thanks. Patch pushed.
Ander
>
> >
> > fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54
> >
> > c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y-
> > 11m-01d-16h-36m-25s UTC integration manifest
> > 4a635f6 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init
> > sequence
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2884/
>
> Jani Saarinen
> Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-11-02 7:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-01 11:11 [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence Ander Conselvan de Oliveira
2016-11-01 11:36 ` Imre Deak
2016-11-02 6:44 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-01 12:16 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-11-02 7:15 ` ✗ Fi.CI.BAT: warning for drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence (rev2) Patchwork
2016-11-02 7:24 ` Saarinen, Jani
2016-11-02 7:41 ` Ander Conselvan De Oliveira
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