From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au,
nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v5 3/4] target-ppc: Implement bcdcfz. instruction
Date: Tue, 8 Nov 2016 14:50:24 -0200 [thread overview]
Message-ID: <1478623825-8460-4-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1478623825-8460-1-git-send-email-joserz@linux.vnet.ibm.com>
bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 44 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 7 ++++++
3 files changed, 52 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 33286c6..8546bb9 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
+DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 33d1941..3ecf9d6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2724,6 +2724,50 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int cr = 0;
+ int invalid = 0;
+ int zone_digit = 0;
+ int zone_lead = ps ? 0xF : 0x3;
+ int digit = 0;
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+ int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4;
+
+ if (unlikely((sgnb < 0xA) && ps)) {
+ invalid = 1;
+ }
+
+ for (i = 0; i < 16; i++) {
+ zone_digit = (i * 2) ? b->u8[BCD_DIG_BYTE(i * 2)] >> 4 : zone_lead;
+ digit = b->u8[BCD_DIG_BYTE(i * 2)] & 0xF;
+ if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
+ invalid = 1;
+ break;
+ }
+
+ bcd_put_digit(&ret, digit, i + 1);
+ }
+
+ if ((ps && (sgnb == 0xB || sgnb == 0xD)) ||
+ (!ps && (sgnb & 0x4))) {
+ bcd_put_digit(&ret, BCD_NEG_PREF, 0);
+ } else {
+ bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0);
+ }
+
+ cr = bcd_cmp_zero(&ret);
+
+ if (unlikely(invalid)) {
+ cr = 1 << CRF_SO;
+ }
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index d5953a6..7e902a9 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -972,6 +972,7 @@ GEN_BCD(bcdadd)
GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
GEN_BCD2(bcdctn)
+GEN_BCD2(bcdcfz)
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -979,6 +980,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
case 5:
gen_bcdctn(ctx);
break;
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
case 7:
gen_bcdcfn(ctx);
break;
@@ -991,6 +995,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
case 7:
gen_bcdcfn(ctx);
break;
--
2.7.4
next prev parent reply other threads:[~2016-11-08 16:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-08 16:50 [Qemu-devel] [PATCH v5 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani
2016-11-08 16:50 ` Jose Ricardo Ziviani [this message]
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 4/4] target-ppc: Implement bcdctz. instruction Jose Ricardo Ziviani
2016-11-09 1:16 ` [Qemu-devel] [PATCH v5 0/4] POWER9 TCG enablements - BCD functions part I David Gibson
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