From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au,
nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v5 4/4] target-ppc: Implement bcdctz. instruction
Date: Tue, 8 Nov 2016 14:50:25 -0200 [thread overview]
Message-ID: <1478623825-8460-5-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1478623825-8460-1-git-send-email-joserz@linux.vnet.ibm.com>
bcdctz. converts from BCD to Zoned numeric format. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 7 ++++++
3 files changed, 51 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8546bb9..5412da5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -374,6 +374,7 @@ DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
+DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 3ecf9d6..c107cee 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2768,6 +2768,49 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int cr = 0;
+ uint8_t digit = 0;
+ int sgnb = bcd_get_sgn(b);
+ int zone_lead = (ps) ? 0xF0 : 0x30;
+ int invalid = (sgnb == 0);
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+ int ox_flag = ((b->u64[HI_IDX] >> 4) != 0);
+
+ for (i = 0; i < 16; i++) {
+ digit = bcd_get_digit(b, i + 1, &invalid);
+
+ if (unlikely(invalid)) {
+ break;
+ }
+
+ ret.u8[BCD_DIG_BYTE(i * 2)] = zone_lead + digit;
+ }
+
+ if (ps) {
+ bcd_put_digit(&ret, (sgnb == 1) ? 0xC : 0xD, 1);
+ } else {
+ bcd_put_digit(&ret, (sgnb == 1) ? 0x3 : 0x7, 1);
+ }
+
+ cr = bcd_cmp_zero(b);
+
+ if (ox_flag) {
+ cr |= 1 << CRF_SO;
+ }
+
+ if (unlikely(invalid)) {
+ cr = 1 << CRF_SO;
+ }
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 7e902a9..b05c874 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -973,10 +973,14 @@ GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
GEN_BCD2(bcdctn)
GEN_BCD2(bcdcfz)
+GEN_BCD2(bcdctz)
static void gen_xpnd04_1(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 4:
+ gen_bcdctz(ctx);
+ break;
case 5:
gen_bcdctn(ctx);
break;
@@ -995,6 +999,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 4:
+ gen_bcdctz(ctx);
+ break;
case 6:
gen_bcdcfz(ctx);
break;
--
2.7.4
next prev parent reply other threads:[~2016-11-08 16:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-08 16:50 [Qemu-devel] [PATCH v5 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani
2016-11-08 16:50 ` [Qemu-devel] [PATCH v5 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani
2016-11-08 16:50 ` Jose Ricardo Ziviani [this message]
2016-11-09 1:16 ` [Qemu-devel] [PATCH v5 0/4] POWER9 TCG enablements - BCD functions part I David Gibson
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