diff for duplicates of <1478646779.7430.66.camel@kernel.crashing.org> diff --git a/a/1.txt b/N1/1.txt index 6c57784..53f1d0c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,23 +1,33 @@ -T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g -Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg -aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2 -IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP -biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh -ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs -ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz -aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s -bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl -cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw -bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg -b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n -bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl -ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu -ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90 -IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh -dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz -IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg -aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy -cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f -CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m -cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp -bnV4LWFybS1rZXJuZWwK +On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote: +> +> My understanding of ISA (which may be flawed) is that it's not part of +> the PCI host bridge, but rather on x86 it happens to share the IO space +> with PCI. + +Sort-of. On some systems it actually goes through PCI and there's a +PCI->ISA bridge that uses substractive decoding to the legacy devices. + +> So, how about this becomes: +> +> Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which +> provides access to some legacy ISA devices. +> +> I believe that we could theoretically have multiple independent LPC/ISA +> busses, as is possible with PCI on !x86 systems. If the current ISA code +> assumes a singleton bus, I think that's something that needs to be fixed +> up more generically. +> +> I don't see why we should need any architecture-specific code here. Why +> can we not fix up the ISA bus code in drivers/of/address.c such that it +> handles multiple ISA bus instances, and translates all sub-device +> addresses relative to the specific bus instance? + +What in that code prevents that today ? + +Cheers, +Ben. + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 4c47acb..e2ffa46 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,57 +1,67 @@ "ref\01478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com\0" "ref\01478576829-112707-3-git-send-email-yuanzhichang@hisilicon.com\0" "ref\020161108114953.GB15297@leverpostej\0" - "From\0Benjamin Herrenschmidt <benh@kernel.crashing.org>\0" + "From\0Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>\0" "Subject\0Re: [PATCH V5 2/3] ARM64 LPC: Add missing range exception for special ISA\0" "Date\0Wed, 09 Nov 2016 10:12:59 +1100\0" - "To\0Mark Rutland <mark.rutland@arm.com>" - " zhichang.yuan <yuanzhichang@hisilicon.com>\0" - "Cc\0gabriele.paoloni@huawei.com" - catalin.marinas@arm.com - will.deacon@arm.com - linuxarm@huawei.com - lorenzo.pieralisi@arm.com - arnd@arndb.de - xuwei5@hisilicon.com - linux-serial@vger.kernel.org - linux-pci@vger.kernel.org - devicetree@vger.kernel.org - minyard@acm.org - marc.zyngier@arm.com - liviu.dudau@arm.com - john.garry@huawei.com - zourongrong@gmail.com - robh+dt@kernel.org - bhelgaas@google.com - kantyzc@163.com - zhichang.yuan02@gmail.com - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " olof@lixom.net\0" + "To\0Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>" + " zhichang.yuan <yuanzhichang-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" + "Cc\0catalin.marinas-5wv7dgnIgG8@public.gmane.org" + will.deacon-5wv7dgnIgG8@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org + olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + minyard-HInyCGIudOg@public.gmane.org + liviu.dudau-5wv7dgnIgG8@public.gmane.org + zourongrong-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + zhichang.yuan02-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + kantyzc-9Onoh4P/yGk@public.gmane.org + xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + " marc.zyngier-5wv7dgnIgG8@public.gmane.org\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g\n" - "Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg\n" - "aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2\n" - "IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP\n" - "biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh\n" - "ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs\n" - "ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz\n" - "aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s\n" - "bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl\n" - "cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw\n" - "bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg\n" - "b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n\n" - "bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl\n" - "ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu\n" - "ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90\n" - "IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh\n" - "dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz\n" - "IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg\n" - "aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy\n" - "cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f\n" - "CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m\n" - "cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp\n" - bnV4LWFybS1rZXJuZWwK + "On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote:\n" + "> \n" + "> My understanding of ISA (which may be flawed) is that it's not part of\n" + "> the PCI host bridge, but rather on x86 it happens to share the IO space\n" + "> with PCI.\n" + "\n" + "Sort-of. On some systems it actually goes through PCI and there's a\n" + "PCI->ISA bridge that uses substractive decoding to the legacy devices.\n" + "\n" + "> So, how about this becomes:\n" + "> \n" + "> \302\240 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which\n" + "> \302\240 provides access to some legacy ISA devices.\n" + "> \n" + "> I believe that we could theoretically have multiple independent LPC/ISA\n" + "> busses, as is possible with PCI on !x86 systems. If the current ISA code\n" + "> assumes a singleton bus, I think that's something that needs to be fixed\n" + "> up more generically.\n" + "> \n" + "> I don't see why we should need any architecture-specific code here. Why\n" + "> can we not fix up the ISA bus code in drivers/of/address.c such that it\n" + "> handles multiple ISA bus instances, and translates all sub-device\n" + "> addresses relative to the specific bus instance?\n" + "\n" + "What in that code prevents that today ?\n" + "\n" + "Cheers,\n" + "Ben.\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -b2f510203dd393e29466eb6edac084172172678e02abab2d647a805356aedd97 +78afb3fd0356e0bd7e65414831940d25972fa08e276a3ede2d600791aaf3dfd2
diff --git a/a/1.txt b/N2/1.txt index 6c57784..b1dee18 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,23 +1,28 @@ -T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g -Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg -aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2 -IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP -biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh -ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs -ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz -aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s -bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl -cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw -bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg -b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n -bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl -ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu -ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90 -IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh -dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz -IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg -aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy -cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f -CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m -cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp -bnV4LWFybS1rZXJuZWwK +On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote: +> +> My understanding of ISA (which may be flawed) is that it's not part of +> the PCI host bridge, but rather on x86 it happens to share the IO space +> with PCI. + +Sort-of. On some systems it actually goes through PCI and there's a +PCI->ISA bridge that uses substractive decoding to the legacy devices. + +> So, how about this becomes: +> +> ? Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which +> ? provides access to some legacy ISA devices. +> +> I believe that we could theoretically have multiple independent LPC/ISA +> busses, as is possible with PCI on !x86 systems. If the current ISA code +> assumes a singleton bus, I think that's something that needs to be fixed +> up more generically. +> +> I don't see why we should need any architecture-specific code here. Why +> can we not fix up the ISA bus code in drivers/of/address.c such that it +> handles multiple ISA bus instances, and translates all sub-device +> addresses relative to the specific bus instance? + +What in that code prevents that today ? + +Cheers, +Ben. diff --git a/a/content_digest b/N2/content_digest index 4c47acb..f73a5c4 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,57 +1,39 @@ "ref\01478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com\0" "ref\01478576829-112707-3-git-send-email-yuanzhichang@hisilicon.com\0" "ref\020161108114953.GB15297@leverpostej\0" - "From\0Benjamin Herrenschmidt <benh@kernel.crashing.org>\0" - "Subject\0Re: [PATCH V5 2/3] ARM64 LPC: Add missing range exception for special ISA\0" + "From\0benh@kernel.crashing.org (Benjamin Herrenschmidt)\0" + "Subject\0[PATCH V5 2/3] ARM64 LPC: Add missing range exception for special ISA\0" "Date\0Wed, 09 Nov 2016 10:12:59 +1100\0" - "To\0Mark Rutland <mark.rutland@arm.com>" - " zhichang.yuan <yuanzhichang@hisilicon.com>\0" - "Cc\0gabriele.paoloni@huawei.com" - catalin.marinas@arm.com - will.deacon@arm.com - linuxarm@huawei.com - lorenzo.pieralisi@arm.com - arnd@arndb.de - xuwei5@hisilicon.com - linux-serial@vger.kernel.org - linux-pci@vger.kernel.org - devicetree@vger.kernel.org - minyard@acm.org - marc.zyngier@arm.com - liviu.dudau@arm.com - john.garry@huawei.com - zourongrong@gmail.com - robh+dt@kernel.org - bhelgaas@google.com - kantyzc@163.com - zhichang.yuan02@gmail.com - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " olof@lixom.net\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g\n" - "Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg\n" - "aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2\n" - "IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP\n" - "biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh\n" - "ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs\n" - "ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz\n" - "aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s\n" - "bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl\n" - "cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw\n" - "bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg\n" - "b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n\n" - "bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl\n" - "ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu\n" - "ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90\n" - "IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh\n" - "dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz\n" - "IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg\n" - "aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy\n" - "cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f\n" - "CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m\n" - "cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp\n" - bnV4LWFybS1rZXJuZWwK + "On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote:\n" + "> \n" + "> My understanding of ISA (which may be flawed) is that it's not part of\n" + "> the PCI host bridge, but rather on x86 it happens to share the IO space\n" + "> with PCI.\n" + "\n" + "Sort-of. On some systems it actually goes through PCI and there's a\n" + "PCI->ISA bridge that uses substractive decoding to the legacy devices.\n" + "\n" + "> So, how about this becomes:\n" + "> \n" + "> ? Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which\n" + "> ? provides access to some legacy ISA devices.\n" + "> \n" + "> I believe that we could theoretically have multiple independent LPC/ISA\n" + "> busses, as is possible with PCI on !x86 systems. If the current ISA code\n" + "> assumes a singleton bus, I think that's something that needs to be fixed\n" + "> up more generically.\n" + "> \n" + "> I don't see why we should need any architecture-specific code here. Why\n" + "> can we not fix up the ISA bus code in drivers/of/address.c such that it\n" + "> handles multiple ISA bus instances, and translates all sub-device\n" + "> addresses relative to the specific bus instance?\n" + "\n" + "What in that code prevents that today ?\n" + "\n" + "Cheers,\n" + Ben. -b2f510203dd393e29466eb6edac084172172678e02abab2d647a805356aedd97 +28e203cae3d7c829acafe2d5581df3bfc83ecf296fc82d530fce8d0cb4940c4e
diff --git a/a/1.txt b/N3/1.txt index 6c57784..e310be2 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,23 +1,28 @@ -T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g -Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg -aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2 -IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP -biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh -ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs -ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz -aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s -bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl -cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw -bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg -b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n -bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl -ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu -ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90 -IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh -dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz -IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg -aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy -cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f -CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m -cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp -bnV4LWFybS1rZXJuZWwK +On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote: +> +> My understanding of ISA (which may be flawed) is that it's not part of +> the PCI host bridge, but rather on x86 it happens to share the IO space +> with PCI. + +Sort-of. On some systems it actually goes through PCI and there's a +PCI->ISA bridge that uses substractive decoding to the legacy devices. + +> So, how about this becomes: +> +> Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which +> provides access to some legacy ISA devices. +> +> I believe that we could theoretically have multiple independent LPC/ISA +> busses, as is possible with PCI on !x86 systems. If the current ISA code +> assumes a singleton bus, I think that's something that needs to be fixed +> up more generically. +> +> I don't see why we should need any architecture-specific code here. Why +> can we not fix up the ISA bus code in drivers/of/address.c such that it +> handles multiple ISA bus instances, and translates all sub-device +> addresses relative to the specific bus instance? + +What in that code prevents that today ? + +Cheers, +Ben. diff --git a/a/content_digest b/N3/content_digest index 4c47acb..b380a0f 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -6,52 +6,57 @@ "Date\0Wed, 09 Nov 2016 10:12:59 +1100\0" "To\0Mark Rutland <mark.rutland@arm.com>" " zhichang.yuan <yuanzhichang@hisilicon.com>\0" - "Cc\0gabriele.paoloni@huawei.com" - catalin.marinas@arm.com + "Cc\0catalin.marinas@arm.com" will.deacon@arm.com - linuxarm@huawei.com - lorenzo.pieralisi@arm.com + robh+dt@kernel.org + bhelgaas@google.com + olof@lixom.net arnd@arndb.de - xuwei5@hisilicon.com - linux-serial@vger.kernel.org - linux-pci@vger.kernel.org + linux-arm-kernel@lists.infradead.org + lorenzo.pieralisi@arm.com + linux-kernel@vger.kernel.org + linuxarm@huawei.com devicetree@vger.kernel.org + linux-pci@vger.kernel.org + linux-serial@vger.kernel.org minyard@acm.org - marc.zyngier@arm.com liviu.dudau@arm.com - john.garry@huawei.com zourongrong@gmail.com - robh+dt@kernel.org - bhelgaas@google.com - kantyzc@163.com + john.garry@huawei.com + gabriele.paoloni@huawei.com zhichang.yuan02@gmail.com - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " olof@lixom.net\0" + kantyzc@163.com + xuwei5@hisilicon.com + " marc.zyngier@arm.com\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE2LTExLTA4IGF0IDExOjQ5ICswMDAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4g\n" - "Cj4gTXkgdW5kZXJzdGFuZGluZyBvZiBJU0EgKHdoaWNoIG1heSBiZSBmbGF3ZWQpIGlzIHRoYXQg\n" - "aXQncyBub3QgcGFydCBvZgo+IHRoZSBQQ0kgaG9zdCBicmlkZ2UsIGJ1dCByYXRoZXIgb24geDg2\n" - "IGl0IGhhcHBlbnMgdG8gc2hhcmUgdGhlIElPIHNwYWNlCj4gd2l0aCBQQ0kuCgpTb3J0LW9mLiBP\n" - "biBzb21lIHN5c3RlbXMgaXQgYWN0dWFsbHkgZ29lcyB0aHJvdWdoIFBDSSBhbmQgdGhlcmUncyBh\n" - "ClBDSS0+SVNBIGJyaWRnZSB0aGF0IHVzZXMgc3Vic3RyYWN0aXZlIGRlY29kaW5nIHRvIHRoZSBs\n" - "ZWdhY3kgZGV2aWNlcy4KCj4gU28sIGhvdyBhYm91dCB0aGlzIGJlY29tZXM6Cj4gCj4gwqAgSGlz\n" - "aWxpY29uIEhpcDA2IFNvQ3MgaW1wbGVtZW50IGEgTG93IFBpbiBDb3VudCAoTFBDKSBjb250cm9s\n" - "bGVyLCB3aGljaAo+IMKgIHByb3ZpZGVzIGFjY2VzcyB0byBzb21lIGxlZ2FjeSBJU0EgZGV2aWNl\n" - "cy4KPiAKPiBJIGJlbGlldmUgdGhhdCB3ZSBjb3VsZCB0aGVvcmV0aWNhbGx5IGhhdmUgbXVsdGlw\n" - "bGUgaW5kZXBlbmRlbnQgTFBDL0lTQQo+IGJ1c3NlcywgYXMgaXMgcG9zc2libGUgd2l0aCBQQ0kg\n" - "b24gIXg4NiBzeXN0ZW1zLiBJZiB0aGUgY3VycmVudCBJU0EgY29kZQo+IGFzc3VtZXMgYSBzaW5n\n" - "bGV0b24gYnVzLCBJIHRoaW5rIHRoYXQncyBzb21ldGhpbmcgdGhhdCBuZWVkcyB0byBiZSBmaXhl\n" - "ZAo+IHVwIG1vcmUgZ2VuZXJpY2FsbHkuCj4gCj4gSSBkb24ndCBzZWUgd2h5IHdlIHNob3VsZCBu\n" - "ZWVkIGFueSBhcmNoaXRlY3R1cmUtc3BlY2lmaWMgY29kZSBoZXJlLiBXaHkKPiBjYW4gd2Ugbm90\n" - "IGZpeCB1cCB0aGUgSVNBIGJ1cyBjb2RlIGluIGRyaXZlcnMvb2YvYWRkcmVzcy5jIHN1Y2ggdGhh\n" - "dCBpdAo+IGhhbmRsZXMgbXVsdGlwbGUgSVNBIGJ1cyBpbnN0YW5jZXMsIGFuZCB0cmFuc2xhdGVz\n" - "IGFsbCBzdWItZGV2aWNlCj4gYWRkcmVzc2VzIHJlbGF0aXZlIHRvIHRoZSBzcGVjaWZpYyBidXMg\n" - "aW5zdGFuY2U/CgpXaGF0IGluIHRoYXQgY29kZSBwcmV2ZW50cyB0aGF0IHRvZGF5ID8KCkNoZWVy\n" - "cywKQmVuLgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f\n" - "CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m\n" - "cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp\n" - bnV4LWFybS1rZXJuZWwK + "On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote:\n" + "> \n" + "> My understanding of ISA (which may be flawed) is that it's not part of\n" + "> the PCI host bridge, but rather on x86 it happens to share the IO space\n" + "> with PCI.\n" + "\n" + "Sort-of. On some systems it actually goes through PCI and there's a\n" + "PCI->ISA bridge that uses substractive decoding to the legacy devices.\n" + "\n" + "> So, how about this becomes:\n" + "> \n" + "> \302\240 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which\n" + "> \302\240 provides access to some legacy ISA devices.\n" + "> \n" + "> I believe that we could theoretically have multiple independent LPC/ISA\n" + "> busses, as is possible with PCI on !x86 systems. If the current ISA code\n" + "> assumes a singleton bus, I think that's something that needs to be fixed\n" + "> up more generically.\n" + "> \n" + "> I don't see why we should need any architecture-specific code here. Why\n" + "> can we not fix up the ISA bus code in drivers/of/address.c such that it\n" + "> handles multiple ISA bus instances, and translates all sub-device\n" + "> addresses relative to the specific bus instance?\n" + "\n" + "What in that code prevents that today ?\n" + "\n" + "Cheers,\n" + Ben. -b2f510203dd393e29466eb6edac084172172678e02abab2d647a805356aedd97 +81cf5f81ba6334aac5511977614c4dce2421c412dedb58bb1ca63e30ba1fe174
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