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From: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1.
Date: Wed, 9 Nov 2016 15:41:42 +0800	[thread overview]
Message-ID: <1478677305-12579-2-git-send-email-Rex.Zhu@amd.com> (raw)
In-Reply-To: <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>

when uvd is idle, we gate uvd clock.
and uvd is busy, we ungate uvd clock.

Change-Id: Ic2fa6149389b0113faf36ec7aad857e77d01af33
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index cf2ee93..a1fc4fc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -149,7 +149,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 	if (bgate) {
 		cgs_set_clockgating_state(hwmgr->device,
 				AMD_IP_BLOCK_TYPE_UVD,
-				AMD_CG_STATE_UNGATE);
+				AMD_CG_STATE_GATE);
 		cgs_set_powergating_state(hwmgr->device,
 						AMD_IP_BLOCK_TYPE_UVD,
 						AMD_PG_STATE_GATE);
@@ -162,7 +162,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 						AMD_CG_STATE_UNGATE);
 		cgs_set_clockgating_state(hwmgr->device,
 				AMD_IP_BLOCK_TYPE_UVD,
-				AMD_CG_STATE_GATE);
+				AMD_CG_STATE_UNGATE);
 		smu7_update_uvd_dpm(hwmgr, false);
 	}
 
-- 
1.9.1

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  parent reply	other threads:[~2016-11-09  7:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-09  7:41 [PATCH 1/5] drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0 Rex Zhu
     [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09  7:41   ` Rex Zhu [this message]
2016-11-09  7:41   ` [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature Rex Zhu
2016-11-09  7:41   ` [PATCH 4/5] drm/amdgpu: refine uvd 6.0 " Rex Zhu
     [not found]     ` <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09 16:03       ` Deucher, Alexander
     [not found]         ` <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-11-09 17:38           ` StDenis, Tom
2016-11-09  7:41   ` [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji Rex Zhu

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