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From: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji.
Date: Wed, 9 Nov 2016 15:41:45 +0800	[thread overview]
Message-ID: <1478677305-12579-5-git-send-email-Rex.Zhu@amd.com> (raw)
In-Reply-To: <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>

Change-Id: I96b937c8b97589d1f98a8351f3653b89163c84a0
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a230b39..d09c25a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -927,7 +927,8 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_ROM_MGCG |
 			AMD_CG_SUPPORT_MC_MGCG |
-			AMD_CG_SUPPORT_MC_LS;
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_UVD_MGCG;
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x3c;
 		break;
-- 
1.9.1

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      parent reply	other threads:[~2016-11-09  7:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-09  7:41 [PATCH 1/5] drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0 Rex Zhu
     [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09  7:41   ` [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1 Rex Zhu
2016-11-09  7:41   ` [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature Rex Zhu
2016-11-09  7:41   ` [PATCH 4/5] drm/amdgpu: refine uvd 6.0 " Rex Zhu
     [not found]     ` <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09 16:03       ` Deucher, Alexander
     [not found]         ` <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-11-09 17:38           ` StDenis, Tom
2016-11-09  7:41   ` Rex Zhu [this message]

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