[PATCH v5 2/2] DW DMAC: add multi-block property to device tree

[andriy.shevchenko@linux.intel.com (Andy Shevchenko)]

On Thu, 2016-11-24@18:04 +0300, Eugeniy Paltsev wrote:
> Several versions of DW DMAC have multi block transfers hardware
> support. Hardware support of multi block transfers is disabled
> by default if we use DT to configure DMAC and software emulation
> of multi block transfers used instead.
> Add multi-block property, so it is possible to enable hardware
> multi block transfers (if present) via DT.
> 
> Switch from per device is_nollp variable to multi_block array
> to be able enable/disable multi block transfers separately per
> channel.

Thanks for an update. Basically I'm fine with this one.

So, we still have question about autoconfiguration in SPEAr SoCs, and
your ARC SoC but it's a different story. I would expect once you will
clarify it.

Another one is minor listed below, otherwise

Acked-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>

> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>

> --- a/drivers/dma/dw/platform.c
> +++ b/drivers/dma/dw/platform.c
> @@ -102,7 +102,7 @@ dw_dma_parse_dt(struct platform_device *pdev)
> ?{
> ?	struct device_node *np = pdev->dev.of_node;
> ?	struct dw_dma_platform_data *pdata;
> -	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
> +	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS],
> chan[DW_DMA_MAX_NR_CHANNELS];

chan here will confuse people...

> @@ -152,6 +154,11 @@ dw_dma_parse_dt(struct platform_device *pdev)
> ?			pdata->data_width[tmp] = BIT(arr[tmp] &
> 0x07);
> ?	}
> ?
> +	if (!of_property_read_u32_array(np, "multi-block", chan,
> nr_channels)) {
> +		for (tmp = 0; tmp < nr_channels; tmp++)
> +			pdata->multi_block[tmp] = chan[tmp];

...mb (as short of multi-block) would suit better.

-- 
Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Intel Finland Oy