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From: Andrew Jeffery <andrew@aj.id.au>
To: openbmc@lists.ozlabs.org
Subject: Re: [PATCH linux v2] arm: aspeed: zaius: Disable LPC reset for UART1
Date: Sat, 28 Jan 2017 18:30:13 +1030	[thread overview]
Message-ID: <1485590413.2450.7.camel@aj.id.au> (raw)
In-Reply-To: <CAPLgG==oWWy8pTpLszLOECXK7pQMXW8uE_NgpFz7Awx51q5ohA@mail.gmail.com>

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On Fri, 2017-01-27 at 15:32 -0800, Rick Altherr wrote:
> I still don't follow.  Is this changing it to drop bytes until the
> host powers on?  Is this change making it so the device won't open?

I understand it to be the other way around: 

In the existing configuration UART1 will drop bytes by being held in
reset until the host initialises the LPC bus (i.e. releases LPCRST#)
during boot.

Xo's change reconfigures the SoC so that UART1 reset state doesn't
depend on LPCRST# (i.e. the host initialising the LPC bus), so it is
immediately useful in that it won't discard bytes.

Xo?

Andrew

> 
> > On Fri, Jan 27, 2017 at 3:23 PM, Xo Wang <xow@google.com> wrote:
> > Currently, UART1 on Zaius BMC is unusable until brought out of reset by
> > powering the host on. In this reset state, ttyS0 can still be opened
> > and UART1 silently drops bytes, which is not obviously expected
> > behavior.
> > 
> > Clear the LPC block control bit that enables LPCRST# as a reset source
> > for UART1.
> > 
> > Signed-off-by: Xo Wang <xow@google.com
> > ---
> >  arch/arm/mach-aspeed/aspeed.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> > index 4bd3680d742d..fa99d8bde5e0 100644
> > --- a/arch/arm/mach-aspeed/aspeed.c
> > +++ b/arch/arm/mach-aspeed/aspeed.c
> > @@ -185,6 +185,13 @@ static void __init do_zaius_setup(void)
> > 
> >         /* Set SPI1 CE0 decoding window to 0x30000000 */
> >         writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
> > +
> > +       /* Disable LPC reset for UART1, otherwise held in reset by LPCRST#,
> > +        * silently dropping bytes until released (usually by host power on)
> > +        * */
> > +       reg = readl(AST_IO(AST_BASE_LPC | 0x98));
> > +       /* Clear "Enable UART1 reset source from LPC" */
> > +       writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
> >  }
> > 
> >  static void __init do_witherspoon_setup(void)
> > --
> > 2.11.0.483.g087da7b7c-goog
> > 
> > _______________________________________________
> > openbmc mailing list
> > openbmc@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/openbmc
> > 
> 
> _______________________________________________
> openbmc mailing list
> openbmc@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/openbmc

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  reply	other threads:[~2017-01-28  8:00 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-27 23:23 [PATCH linux v2] arm: aspeed: zaius: Disable LPC reset for UART1 Xo Wang
2017-01-27 23:32 ` Rick Altherr
2017-01-28  8:00   ` Andrew Jeffery [this message]
2017-01-31 22:23     ` Xo Wang
2017-01-31 22:24       ` Rick Altherr

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