[PATCH linux v2] arm: aspeed: zaius: Disable LPC reset for UART1

[Xo Wang <xow@google.com>]

Currently, UART1 on Zaius BMC is unusable until brought out of reset by
powering the host on. In this reset state, ttyS0 can still be opened
and UART1 silently drops bytes, which is not obviously expected
behavior.

Clear the LPC block control bit that enables LPCRST# as a reset source
for UART1.

Signed-off-by: Xo Wang <xow@google.com
---
 arch/arm/mach-aspeed/aspeed.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 4bd3680d742d..fa99d8bde5e0 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -185,6 +185,13 @@ static void __init do_zaius_setup(void)
 
 	/* Set SPI1 CE0 decoding window to 0x30000000 */
 	writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
+
+	/* Disable LPC reset for UART1, otherwise held in reset by LPCRST#,
+	 * silently dropping bytes until released (usually by host power on)
+	 * */
+	reg = readl(AST_IO(AST_BASE_LPC | 0x98));
+	/* Clear "Enable UART1 reset source from LPC" */
+	writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
 }
 
 static void __init do_witherspoon_setup(void)
-- 
2.11.0.483.g087da7b7c-goog