From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
To: David Gibson <david@gibson.dropbear.id.au>,
Balbir Singh <bsingharora@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, sam.bobroff@au1.ibm.com
Subject: Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9
Date: Thu, 23 Feb 2017 15:21:38 +1100 [thread overview]
Message-ID: <1487823698.23895.3.camel@gmail.com> (raw)
In-Reply-To: <20170223034710.GJ12577@umbus.fritz.box>
On Thu, 2017-02-23 at 14:47 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote:
> >
> > On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh
> > wrote:
> > >
> > > The logical partitioning control register controls a threads
> > > operation
> > > based on the partition it is currently executing. Add new
> > > definitions and
> > > update the mask used when writing to the LPCR based on the POWER9
> > > spec.
> > >
> > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > > ---
> > > target/ppc/cpu.h | 18 ++++++++++++++++++
> > > target/ppc/mmu-hash64.c | 8 ++++++++
> > > target/ppc/translate_init.c | 24 ++++++++++++++++++------
> > > 3 files changed, 44 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > > index bb96dd5..425e79d 100644
> > > --- a/target/ppc/cpu.h
> > > +++ b/target/ppc/cpu.h
> > > @@ -384,12 +384,19 @@ struct ppc_slb_t {
> > > #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
> > > #define LPCR_VRMASD_SHIFT (63 - 16)
> > > #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
> > > +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask
> > > */
> > > +#define LPCR_PECE_U_SHIFT (63 - 19)
> > > +#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
> > > +#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt
> > > Exit Enable */
> > > #define LPCR_RMLS_SHIFT (63 - 37)
> > > #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
> > > #define LPCR_ILE (1ull << (63 - 38))
> > > #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt
> > > location */
> > > #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
> > > +#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process
> > > Table */
> > > +#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced
> > > Virtualisation */
> > > #define LPCR_ONL (1ull << (63 - 45))
> > > +#define LPCR_LD (1ull << (63 - 46)) /* Large
> > > Decrementer */
> > > #define LPCR_P7_PECE0 (1ull << (63 - 49))
> > > #define LPCR_P7_PECE1 (1ull << (63 - 50))
> > > #define LPCR_P7_PECE2 (1ull << (63 - 51))
> > > @@ -398,11 +405,22 @@ struct ppc_slb_t {
> > > #define LPCR_P8_PECE2 (1ull << (63 - 49))
> > > #define LPCR_P8_PECE3 (1ull << (63 - 50))
> > > #define LPCR_P8_PECE4 (1ull << (63 - 51))
> > > +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask
> > > */
> > > +#define LPCR_PECE_L_SHIFT (63 - 51)
> > > +#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
> > > +#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged
> > > Doorbell Exit EN */
> > > +#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell
> > > Exit Enable */
> > > +#define LPCR_EEE (1ull << (63 - 49)) /* External Exit
> > > Enable */
> > > +#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer
> > > Exit Enable */
> > > +#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit
> > > Enable */
> > > #define LPCR_MER (1ull << (63 - 52))
> > > +#define LPCR_GTSE (1ull << (63 - 53)) /* Guest
> > > Translation Shootdown */
> > > #define LPCR_TC (1ull << (63 - 54))
> > > +#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern
> > > Interrupt Control */
> > > #define LPCR_LPES0 (1ull << (63 - 60))
> > > #define LPCR_LPES1 (1ull << (63 - 61))
> > > #define LPCR_RMI (1ull << (63 - 62))
> > > +#define LPCR_HVICE (1ull << (63 - 62)) /* HV
> > > Virtualisation Int Enable */
> > > #define LPCR_HDICE (1ull << (63 - 63))
> > This patch is missing
> >
> > #define LPCR_HR (1ull << (63 - 43)) /* HV uses Radix
> > Tree Translation */
> >
> > See arch/powerpc/include/asm/reg.h in the Linux kernel.
> Suraj, if you're resending anyway, add this. It doesn't matter for
> non-powernv, of course, but we might as well put the #define in to
> document it.
>
Yeah adding a define can't hurt
next prev parent reply other threads:[~2017-02-23 4:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-20 4:04 [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-02-20 5:16 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-23 3:43 ` David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define Suraj Jitindar Singh
2017-02-20 5:47 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-02-20 7:31 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-23 3:47 ` David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh [this message]
2017-02-23 3:45 ` [Qemu-devel] " David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-21 4:22 ` Balbir Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState Suraj Jitindar Singh
2017-02-23 3:50 ` David Gibson
2017-02-23 4:22 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation Suraj Jitindar Singh
2017-02-23 3:57 ` David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-23 4:08 ` David Gibson
2017-02-23 4:24 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models Suraj Jitindar Singh
2017-02-23 4:09 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1487823698.23895.3.camel@gmail.com \
--to=sjitindarsingh@gmail.com \
--cc=bsingharora@gmail.com \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=sam.bobroff@au1.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.