* [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access
@ 2017-03-10 0:09 Chris Wilson
2017-03-10 0:53 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2017-03-10 0:09 UTC (permalink / raw)
To: intel-gfx
If the object is coherent, we can simply update the cache domain on the
whole object rather than calculate the before/after clflushes. The
advantage is that we then get correct tracking of ellided flushes when
changing coherency later.
Testcase: igt/gem_pwrite_snooped
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 45 +++++++++++++++++++++--------------------
2 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3002996ddbed..8de104b63209 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3353,9 +3353,9 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
unsigned int *needs_clflush);
-#define CLFLUSH_BEFORE 0x1
-#define CLFLUSH_AFTER 0x2
-#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
+#define CLFLUSH_BEFORE BIT(0)
+#define CLFLUSH_AFTER BIT(1)
+#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index aca1eaddafb4..202bb850f260 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -788,6 +788,15 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
if (ret)
return ret;
+ if (i915_gem_object_is_coherent(obj) ||
+ !static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ ret = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (ret)
+ goto err_unpin;
+ else
+ goto out;
+ }
+
i915_gem_object_flush_gtt_write_domain(obj);
/* If we're not in the cpu read domain, set ourself into the gtt
@@ -796,16 +805,9 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
* anyway again before the next pread happens.
*/
if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
- *needs_clflush = !i915_gem_object_is_coherent(obj);
-
- if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
- ret = i915_gem_object_set_to_cpu_domain(obj, false);
- if (ret)
- goto err_unpin;
-
- *needs_clflush = 0;
- }
+ *needs_clflush = CLFLUSH_BEFORE;
+out:
/* return with the pages pinned */
return 0;
@@ -838,6 +840,15 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
if (ret)
return ret;
+ if (i915_gem_object_is_coherent(obj) ||
+ !static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ ret = i915_gem_object_set_to_cpu_domain(obj, true);
+ if (ret)
+ goto err_unpin;
+ else
+ goto out;
+ }
+
i915_gem_object_flush_gtt_write_domain(obj);
/* If we're not in the cpu write domain, set ourself into the
@@ -846,25 +857,15 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
* right away and we therefore have to clflush anyway.
*/
if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
- *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
+ *needs_clflush |= CLFLUSH_AFTER;
/* Same trick applies to invalidate partially written cachelines read
* before writing.
*/
if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
- *needs_clflush |= !i915_gem_object_is_coherent(obj);
-
- if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
- ret = i915_gem_object_set_to_cpu_domain(obj, true);
- if (ret)
- goto err_unpin;
-
- *needs_clflush = 0;
- }
-
- if ((*needs_clflush & CLFLUSH_AFTER) == 0)
- obj->cache_dirty = true;
+ *needs_clflush |= CLFLUSH_BEFORE;
+out:
intel_fb_obj_invalidate(obj, ORIGIN_CPU);
obj->mm.dirty = true;
/* return with the pages pinned */
--
2.11.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Move whole object to CPU domain for coherent shmem access
2017-03-10 0:09 [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access Chris Wilson
@ 2017-03-10 0:53 ` Patchwork
2017-03-10 9:05 ` Patchwork
2017-03-13 9:06 ` [PATCH] " Joonas Lahtinen
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-03-10 0:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move whole object to CPU domain for coherent shmem access
URL : https://patchwork.freedesktop.org/series/21020/
State : failure
== Summary ==
Series 21020v1 drm/i915: Move whole object to CPU domain for coherent shmem access
https://patchwork.freedesktop.org/api/1.0/series/21020/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-wb-pro-default:
pass -> INCOMPLETE (fi-bxt-t5700)
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 463s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 603s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 540s
fi-bxt-t5700 total:58 pass:50 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 439s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 490s
fi-kbl-7500u total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time: 475s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 510s
fi-skl-6700hq total:51 pass:43 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 508s
efa9a3649bd94a4f35911aaecc723e041d8b99c5 drm-tip: 2017y-03m-09d-21h-28m-20s UTC integration manifest
90a0145 drm/i915: Move whole object to CPU domain for coherent shmem access
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4127/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Move whole object to CPU domain for coherent shmem access
2017-03-10 0:09 [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access Chris Wilson
2017-03-10 0:53 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-03-10 9:05 ` Patchwork
2017-03-13 9:06 ` [PATCH] " Joonas Lahtinen
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-03-10 9:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move whole object to CPU domain for coherent shmem access
URL : https://patchwork.freedesktop.org/series/21020/
State : failure
== Summary ==
Series 21020v1 drm/i915: Move whole object to CPU domain for coherent shmem access
https://patchwork.freedesktop.org/api/1.0/series/21020/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-wb-pro-default:
pass -> INCOMPLETE (fi-bxt-t5700)
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 463s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 603s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 540s
fi-bxt-t5700 total:58 pass:50 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 505s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 438s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 432s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 439s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 507s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 490s
fi-kbl-7500u total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time: 475s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 510s
fi-skl-6700hq total:51 pass:43 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 508s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 544s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 564s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 410s
efa9a3649bd94a4f35911aaecc723e041d8b99c5 drm-tip: 2017y-03m-09d-21h-28m-20s UTC integration manifest
90a0145 drm/i915: Move whole object to CPU domain for coherent shmem access
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4127/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access
2017-03-10 0:09 [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access Chris Wilson
2017-03-10 0:53 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-03-10 9:05 ` Patchwork
@ 2017-03-13 9:06 ` Joonas Lahtinen
2017-03-13 14:30 ` Chris Wilson
2 siblings, 1 reply; 5+ messages in thread
From: Joonas Lahtinen @ 2017-03-13 9:06 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On pe, 2017-03-10 at 00:09 +0000, Chris Wilson wrote:
> If the object is coherent, we can simply update the cache domain on the
> whole object rather than calculate the before/after clflushes. The
> advantage is that we then get correct tracking of ellided flushes when
> changing coherency later.
>
> Testcase: igt/gem_pwrite_snooped
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access
2017-03-13 9:06 ` [PATCH] " Joonas Lahtinen
@ 2017-03-13 14:30 ` Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2017-03-13 14:30 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Mon, Mar 13, 2017 at 11:06:20AM +0200, Joonas Lahtinen wrote:
> On pe, 2017-03-10 at 00:09 +0000, Chris Wilson wrote:
> > If the object is coherent, we can simply update the cache domain on the
> > whole object rather than calculate the before/after clflushes. The
> > advantage is that we then get correct tracking of ellided flushes when
> > changing coherency later.
> >
> > Testcase: igt/gem_pwrite_snooped
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Thanks, pushed
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-03-10 0:09 [PATCH] drm/i915: Move whole object to CPU domain for coherent shmem access Chris Wilson
2017-03-10 0:53 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-03-10 9:05 ` Patchwork
2017-03-13 9:06 ` [PATCH] " Joonas Lahtinen
2017-03-13 14:30 ` Chris Wilson
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