diff for duplicates of <1490786446.32756.4.camel@synopsys.com>

diff --git a/a/1.txt b/N1/1.txt
index 4e4b732..00418b0 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,31 +1,48 @@
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+Hi Stephen, Michael,
+
+On Fri, 2017-03-03@15:50 -0800, Stephen Boyd wrote:
+> On 03/03, Vlad Zakharov wrote:
+> > 
+> > Hi Michael, Stephen,
+> > 
+> > On Tue, 2017-02-21@16:11 +0300, Vlad Zakharov wrote:
+> > > 
+> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
+> > > dividers and corresponding control registers mapped to different addresses.
+> > > So we add one common driver for such PLLs.
+> > > 
+> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
+> > > ODIV. Output clock value is managed using these dividers.
+> > > 
+> > > We add pre-defined tables with supported rate values and appropriate
+> > > configurations of IDIV, FBDIV and ODIV for each value.
+> > > 
+> > > As of today we add support for PLLs that generate clock for the
+> > > following devices:
+> > > ?* ARC core on AXC CPU tiles.
+> > > ?* ARC PGU on ARC SDP Mainboard.
+> > > and more to come later.
+> > > 
+> > > Acked-by: Rob Herring <robh at kernel.org>
+> > > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com>
+> > > Signed-off-by: Jose Abreu <joabreu at synopsys.com>
+> > > Cc: Michael Turquette <mturquette at baylibre.com>
+> > > Cc: Stephen Boyd <sboyd at codeaurora.org>
+> > > Cc: Mark Rutland <mark.rutland at arm.com>
+> > 
+> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
+> > 
+> 
+> I haven't reviewed it yet. The merge window is upon us right now
+> so I'll probably get to going through the queue this weekend/next
+> week.
+> 
+
+Please treat this message as a polite reminder to review my patch.
+It is required for some subsystems on our boards, e.g. for ARC PGU.
+
+Thanks.
+
+-- 
+Best regards,
+Vlad Zakharov <vzakhar at synopsys.com>
diff --git a/a/content_digest b/N1/content_digest
index 4a1664b..e0ecaf8 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,51 +1,59 @@
  "ref\01487682670-4164-1-git-send-email-vzakhar@synopsys.com\0"
  "ref\01488547113.2557.44.camel@synopsys.com\0"
  "ref\020170303235005.GV25384@codeaurora.org\0"
- "From\0Vlad Zakharov <Vladislav.Zakharov@synopsys.com>\0"
- "Subject\0Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver\0"
+ "From\0Vladislav.Zakharov@synopsys.com (Vlad Zakharov)\0"
+ "Subject\0[PATCH v2] clk/axs10x: introduce AXS10X pll driver\0"
  "Date\0Wed, 29 Mar 2017 11:20:46 +0000\0"
- "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>"
-  mturquette@baylibre.com <mturquette@baylibre.com>
- " Vladislav.Zakharov@synopsys.com <Vladislav.Zakharov@synopsys.com>\0"
- "Cc\0robh@kernel.org <robh@kernel.org>"
-  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
-  Jose.Abreu@synopsys.com <Jose.Abreu@synopsys.com>
-  mark.rutland@arm.com <mark.rutland@arm.com>
-  linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>
-  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
- " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0"
+ "To\0linux-snps-arc@lists.infradead.org\0"
  "\00:1\0"
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+ "Hi Stephen, Michael,\n"
+ "\n"
+ "On Fri, 2017-03-03@15:50 -0800, Stephen Boyd wrote:\n"
+ "> On 03/03, Vlad Zakharov wrote:\n"
+ "> > \n"
+ "> > Hi Michael, Stephen,\n"
+ "> > \n"
+ "> > On Tue, 2017-02-21@16:11 +0300, Vlad Zakharov wrote:\n"
+ "> > > \n"
+ "> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same\n"
+ "> > > dividers and corresponding control registers mapped to different addresses.\n"
+ "> > > So we add one common driver for such PLLs.\n"
+ "> > > \n"
+ "> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and\n"
+ "> > > ODIV. Output clock value is managed using these dividers.\n"
+ "> > > \n"
+ "> > > We add pre-defined tables with supported rate values and appropriate\n"
+ "> > > configurations of IDIV, FBDIV and ODIV for each value.\n"
+ "> > > \n"
+ "> > > As of today we add support for PLLs that generate clock for the\n"
+ "> > > following devices:\n"
+ "> > > ?* ARC core on AXC CPU tiles.\n"
+ "> > > ?* ARC PGU on ARC SDP Mainboard.\n"
+ "> > > and more to come later.\n"
+ "> > > \n"
+ "> > > Acked-by: Rob Herring <robh at kernel.org>\n"
+ "> > > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com>\n"
+ "> > > Signed-off-by: Jose Abreu <joabreu at synopsys.com>\n"
+ "> > > Cc: Michael Turquette <mturquette at baylibre.com>\n"
+ "> > > Cc: Stephen Boyd <sboyd at codeaurora.org>\n"
+ "> > > Cc: Mark Rutland <mark.rutland at arm.com>\n"
+ "> > \n"
+ "> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.\n"
+ "> > \n"
+ "> \n"
+ "> I haven't reviewed it yet. The merge window is upon us right now\n"
+ "> so I'll probably get to going through the queue this weekend/next\n"
+ "> week.\n"
+ "> \n"
+ "\n"
+ "Please treat this message as a polite reminder to review my patch.\n"
+ "It is required for some subsystems on our boards, e.g. for ARC PGU.\n"
+ "\n"
+ "Thanks.\n"
+ "\n"
+ "-- \n"
+ "Best regards,\n"
+ Vlad Zakharov <vzakhar at synopsys.com>
 
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