From: Vlad Zakharov <Vladislav.Zakharov@synopsys.com>
To: "sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Vladislav.Zakharov@synopsys.com"
<Vladislav.Zakharov@synopsys.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>
Subject: Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver
Date: Wed, 29 Mar 2017 11:20:46 +0000 [thread overview]
Message-ID: <1490786446.32756.4.camel@synopsys.com> (raw)
In-Reply-To: <20170303235005.GV25384@codeaurora.org>
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WARNING: multiple messages have this Message-ID (diff)
From: Vladislav.Zakharov@synopsys.com (Vlad Zakharov)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH v2] clk/axs10x: introduce AXS10X pll driver
Date: Wed, 29 Mar 2017 11:20:46 +0000 [thread overview]
Message-ID: <1490786446.32756.4.camel@synopsys.com> (raw)
In-Reply-To: <20170303235005.GV25384@codeaurora.org>
Hi Stephen, Michael,
On Fri, 2017-03-03@15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21@16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > > dividers and corresponding control registers mapped to different addresses.
> > > So we add one common driver for such PLLs.
> > >
> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > > ODIV. Output clock value is managed using these dividers.
> > >
> > > We add pre-defined tables with supported rate values and appropriate
> > > configurations of IDIV, FBDIV and ODIV for each value.
> > >
> > > As of today we add support for PLLs that generate clock for the
> > > following devices:
> > > ?* ARC core on AXC CPU tiles.
> > > ?* ARC PGU on ARC SDP Mainboard.
> > > and more to come later.
> > >
> > > Acked-by: Rob Herring <robh at kernel.org>
> > > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com>
> > > Signed-off-by: Jose Abreu <joabreu at synopsys.com>
> > > Cc: Michael Turquette <mturquette at baylibre.com>
> > > Cc: Stephen Boyd <sboyd at codeaurora.org>
> > > Cc: Mark Rutland <mark.rutland at arm.com>
> >
> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
> >
>
> I haven't reviewed it yet. The merge window is upon us right now
> so I'll probably get to going through the queue this weekend/next
> week.
>
Please treat this message as a polite reminder to review my patch.
It is required for some subsystems on our boards, e.g. for ARC PGU.
Thanks.
--
Best regards,
Vlad Zakharov <vzakhar at synopsys.com>
WARNING: multiple messages have this Message-ID (diff)
From: Vlad Zakharov <Vladislav.Zakharov@synopsys.com>
To: "sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Vladislav.Zakharov@synopsys.com"
<Vladislav.Zakharov@synopsys.com>
Cc: "Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
"robh@kernel.org" <robh@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver
Date: Wed, 29 Mar 2017 11:20:46 +0000 [thread overview]
Message-ID: <1490786446.32756.4.camel@synopsys.com> (raw)
In-Reply-To: <20170303235005.GV25384@codeaurora.org>
Hi Stephen, Michael,
On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > > dividers and corresponding control registers mapped to different addresses.
> > > So we add one common driver for such PLLs.
> > >
> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > > ODIV. Output clock value is managed using these dividers.
> > >
> > > We add pre-defined tables with supported rate values and appropriate
> > > configurations of IDIV, FBDIV and ODIV for each value.
> > >
> > > As of today we add support for PLLs that generate clock for the
> > > following devices:
> > > * ARC core on AXC CPU tiles.
> > > * ARC PGU on ARC SDP Mainboard.
> > > and more to come later.
> > >
> > > Acked-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
> > > Signed-off-by: Jose Abreu <joabreu@synopsys.com>
> > > Cc: Michael Turquette <mturquette@baylibre.com>
> > > Cc: Stephen Boyd <sboyd@codeaurora.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> >
> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
> >
>
> I haven't reviewed it yet. The merge window is upon us right now
> so I'll probably get to going through the queue this weekend/next
> week.
>
Please treat this message as a polite reminder to review my patch.
It is required for some subsystems on our boards, e.g. for ARC PGU.
Thanks.
--
Best regards,
Vlad Zakharov <vzakhar@synopsys.com>
_______________________________________________
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
WARNING: multiple messages have this Message-ID (diff)
From: Vlad Zakharov <Vladislav.Zakharov@synopsys.com>
To: "sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Vladislav.Zakharov@synopsys.com"
<Vladislav.Zakharov@synopsys.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>
Subject: Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver
Date: Wed, 29 Mar 2017 11:20:46 +0000 [thread overview]
Message-ID: <1490786446.32756.4.camel@synopsys.com> (raw)
In-Reply-To: <20170303235005.GV25384@codeaurora.org>
Hi Stephen, Michael,
On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > > dividers and corresponding control registers mapped to different addresses.
> > > So we add one common driver for such PLLs.
> > >
> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > > ODIV. Output clock value is managed using these dividers.
> > >
> > > We add pre-defined tables with supported rate values and appropriate
> > > configurations of IDIV, FBDIV and ODIV for each value.
> > >
> > > As of today we add support for PLLs that generate clock for the
> > > following devices:
> > > * ARC core on AXC CPU tiles.
> > > * ARC PGU on ARC SDP Mainboard.
> > > and more to come later.
> > >
> > > Acked-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
> > > Signed-off-by: Jose Abreu <joabreu@synopsys.com>
> > > Cc: Michael Turquette <mturquette@baylibre.com>
> > > Cc: Stephen Boyd <sboyd@codeaurora.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> >
> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
> >
>
> I haven't reviewed it yet. The merge window is upon us right now
> so I'll probably get to going through the queue this weekend/next
> week.
>
Please treat this message as a polite reminder to review my patch.
It is required for some subsystems on our boards, e.g. for ARC PGU.
Thanks.
--
Best regards,
Vlad Zakharov <vzakhar@synopsys.com>
next prev parent reply other threads:[~2017-03-29 11:20 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-21 13:11 [PATCH v2] clk/axs10x: introduce AXS10X pll driver Vlad Zakharov
2017-02-21 13:11 ` Vlad Zakharov
2017-03-03 13:18 ` Vlad Zakharov
2017-03-03 13:18 ` Vlad Zakharov
2017-03-03 13:18 ` Vlad Zakharov
2017-03-03 13:18 ` Vlad Zakharov
2017-03-03 23:50 ` Stephen Boyd
2017-03-03 23:50 ` Stephen Boyd
2017-03-03 23:50 ` Stephen Boyd
2017-03-29 11:20 ` Vlad Zakharov [this message]
2017-03-29 11:20 ` Vlad Zakharov
2017-03-29 11:20 ` Vlad Zakharov
2017-03-29 11:20 ` Vlad Zakharov
2017-04-03 10:54 ` Jose Abreu
2017-04-03 10:54 ` Jose Abreu
2017-04-03 10:54 ` Jose Abreu
2017-04-05 1:35 ` Stephen Boyd
2017-04-05 1:35 ` Stephen Boyd
2017-04-05 1:35 ` Stephen Boyd
2017-04-05 16:06 ` Vlad Zakharov
2017-04-05 16:06 ` Vlad Zakharov
2017-04-05 16:06 ` Vlad Zakharov
2017-04-19 16:49 ` sboyd
2017-04-19 16:49 ` sboyd
2017-04-20 15:13 ` Vlad Zakharov
2017-04-20 15:13 ` Vlad Zakharov
2017-04-20 15:13 ` Vlad Zakharov
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