diff for duplicates of <1491148665.3480.8.camel@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index dc8c2d4..0fd3684 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -30,11 +30,11 @@ Thx Martin Cheers > --- -> ?drivers/clk/meson/gxbb.c??????????????| 64 ++------------------------------ +> drivers/clk/meson/gxbb.c | 64 ++------------------------------ > --- -> ?drivers/clk/meson/gxbb.h??????????????|??2 +- -> ?include/dt-bindings/clock/gxbb-clkc.h |??1 - -> ?3 files changed, 4 insertions(+), 63 deletions(-) +> drivers/clk/meson/gxbb.h | 2 +- +> include/dt-bindings/clock/gxbb-clkc.h | 1 - +> 3 files changed, 4 insertions(+), 63 deletions(-) > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index ad5f027af1a2..7cf88ca9bdce 100644 @@ -42,9 +42,9 @@ Cheers > +++ b/drivers/clk/meson/gxbb.c > @@ -278,20 +278,6 @@ static const struct pll_rate_table > gxl_gp0_pll_rate_table[] = { -> ? { /* sentinel */ }, -> ?}; -> ? +> { /* sentinel */ }, +> }; +> > -static const struct clk_div_table cpu_div_table[] = { > - { .val = 1, .div = 1 }, > - { .val = 2, .div = 2 }, @@ -59,20 +59,20 @@ Cheers > - { /* sentinel */ }, > -}; > - -> ?static struct meson_clk_pll gxbb_fixed_pll = { -> ? .m = { -> ? .reg_off = HHI_MPLL_CNTL, +> static struct meson_clk_pll gxbb_fixed_pll = { +> .m = { +> .reg_off = HHI_MPLL_CNTL, > @@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = { -> ?}; -> ? -> ?/* +> }; +> +> /* > - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL > - * post-dividers and should be modeled with their respective PLLs via the > - * forthcoming coordinated clock rates feature > + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers > + * and should be modeled with their respective PLLs via the forthcoming > + * coordinated clock rates feature -> ? */ +> */ > -static struct meson_clk_cpu gxbb_cpu_clk = { > - .reg_off = HHI_SYS_CPU_CLK_CNTL1, > - .div_table = cpu_div_table, @@ -84,90 +84,90 @@ Cheers > - .num_parents = 1, > - }, > -}; -> ? -> ?static u32 mux_table_clk81[] = { 6, 5, 7 }; -> ? +> +> static u32 mux_table_clk81[] = { 6, 5, 7 }; +> > @@ -1045,7 +1020,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); -> ?static struct clk_hw_onecell_data gxbb_hw_onecell_data = { -> ? .hws = { -> ? [CLKID_SYS_PLL] ????= &gxbb_sys_pll.hw, -> - [CLKID_CPUCLK] ????= &gxbb_cpu_clk.hw, -> ? [CLKID_HDMI_PLL] ????= &gxbb_hdmi_pll.hw, -> ? [CLKID_FIXED_PLL] ????= &gxbb_fixed_pll.hw, -> ? [CLKID_FCLK_DIV2] ????= &gxbb_fclk_div2.hw, +> static struct clk_hw_onecell_data gxbb_hw_onecell_data = { +> .hws = { +> [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, +> - [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, +> [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, +> [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, +> [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, > @@ -1165,7 +1139,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = > { -> ?static struct clk_hw_onecell_data gxl_hw_onecell_data = { -> ? .hws = { -> ? [CLKID_SYS_PLL] ????= &gxbb_sys_pll.hw, -> - [CLKID_CPUCLK] ????= &gxbb_cpu_clk.hw, -> ? [CLKID_HDMI_PLL] ????= &gxbb_hdmi_pll.hw, -> ? [CLKID_FIXED_PLL] ????= &gxbb_fixed_pll.hw, -> ? [CLKID_FCLK_DIV2] ????= &gxbb_fclk_div2.hw, +> static struct clk_hw_onecell_data gxl_hw_onecell_data = { +> .hws = { +> [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, +> - [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, +> [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, +> [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, +> [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, > @@ -1430,7 +1403,6 @@ struct clkc_data { -> ? unsigned int clk_dividers_count; -> ? struct meson_clk_audio_divider *const *clk_audio_dividers; -> ? unsigned int clk_audio_dividers_count; +> unsigned int clk_dividers_count; +> struct meson_clk_audio_divider *const *clk_audio_dividers; +> unsigned int clk_audio_dividers_count; > - struct meson_clk_cpu *cpu_clk; -> ? struct clk_hw_onecell_data *hw_onecell_data; -> ?}; -> ? +> struct clk_hw_onecell_data *hw_onecell_data; +> }; +> > @@ -1447,7 +1419,6 @@ static const struct clkc_data gxbb_clkc_data = { -> ? .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), -> ? .clk_audio_dividers = gxbb_audio_dividers, -> ? .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), +> .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), +> .clk_audio_dividers = gxbb_audio_dividers, +> .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), > - .cpu_clk = &gxbb_cpu_clk, -> ? .hw_onecell_data = &gxbb_hw_onecell_data, -> ?}; -> ? +> .hw_onecell_data = &gxbb_hw_onecell_data, +> }; +> > @@ -1464,7 +1435,6 @@ static const struct clkc_data gxl_clkc_data = { -> ? .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), -> ? .clk_audio_dividers = gxbb_audio_dividers, -> ? .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), +> .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), +> .clk_audio_dividers = gxbb_audio_dividers, +> .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), > - .cpu_clk = &gxbb_cpu_clk, -> ? .hw_onecell_data = &gxl_hw_onecell_data, -> ?}; -> ? +> .hw_onecell_data = &gxl_hw_onecell_data, +> }; +> > @@ -1479,8 +1449,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) -> ? const struct clkc_data *clkc_data; -> ? void __iomem *clk_base; -> ? int ret, clkid, i; +> const struct clkc_data *clkc_data; +> void __iomem *clk_base; +> int ret, clkid, i; > - struct clk_hw *parent_hw; > - struct clk *parent_clk; -> ? struct device *dev = &pdev->dev; -> ? -> ? clkc_data = of_device_get_match_data(&pdev->dev); +> struct device *dev = &pdev->dev; +> +> clkc_data = of_device_get_match_data(&pdev->dev); > @@ -1502,9 +1470,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) -> ? for (i = 0; i < clkc_data->clk_mplls_count; i++) -> ? clkc_data->clk_mplls[i]->base = clk_base; -> ? +> for (i = 0; i < clkc_data->clk_mplls_count; i++) +> clkc_data->clk_mplls[i]->base = clk_base; +> > - /* Populate the base address for CPU clk */ > - clkc_data->cpu_clk->base = clk_base; > - -> ? /* Populate base address for gates */ -> ? for (i = 0; i < clkc_data->clk_gates_count; i++) -> ? clkc_data->clk_gates[i]->reg = clk_base + +> /* Populate base address for gates */ +> for (i = 0; i < clkc_data->clk_gates_count; i++) +> clkc_data->clk_gates[i]->reg = clk_base + > @@ -1538,29 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device > *pdev) -> ? goto iounmap; -> ? } -> ? +> goto iounmap; +> } +> > - /* -> - ?* Register CPU clk notifier -> - ?* -> - ?* FIXME this is wrong for a lot of reasons. First, the muxes should +> - * Register CPU clk notifier +> - * +> - * FIXME this is wrong for a lot of reasons. First, the muxes should > be -> - ?* struct clk_hw objects. Second, we shouldn't program the muxes in -> - ?* notifier handlers. The tricky programming sequence will be handled -> - ?* by the forthcoming coordinated clock rates mechanism once that -> - ?* feature is released. -> - ?* -> - ?* Furthermore, looking up the parent this way is terrible. At some -> - ?* point we will stop allocating a default struct clk when +> - * struct clk_hw objects. Second, we shouldn't program the muxes in +> - * notifier handlers. The tricky programming sequence will be handled +> - * by the forthcoming coordinated clock rates mechanism once that +> - * feature is released. +> - * +> - * Furthermore, looking up the parent this way is terrible. At some +> - * point we will stop allocating a default struct clk when > registering -> - ?* a new clk_hw, and this hack will no longer work. Releasing the ccr -> - ?* feature before that time solves the problem :-) -> - ?*/ +> - * a new clk_hw, and this hack will no longer work. Releasing the ccr +> - * feature before that time solves the problem :-) +> - */ > - parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw); > - parent_clk = parent_hw->clk; > - ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb); @@ -177,32 +177,32 @@ Cheers > - goto iounmap; > - } > - -> ? return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, -> ? clkc_data->hw_onecell_data); -> ? +> return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, +> clkc_data->hw_onecell_data); +> > diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h > index 17c6aef033ff..36330c2d4433 100644 > --- a/drivers/clk/meson/gxbb.h > +++ b/drivers/clk/meson/gxbb.h > @@ -171,7 +171,7 @@ -> ? * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h -> ? */ -> ?#define CLKID_SYS_PLL ??0 +> * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h +> */ +> #define CLKID_SYS_PLL 0 > -/* CLKID_CPUCLK */ > +/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */ -> ?/* CLKID_HDMI_PLL */ -> ?#define CLKID_FIXED_PLL ??3 -> ?/* CLKID_FCLK_DIV2 */ +> /* CLKID_HDMI_PLL */ +> #define CLKID_FIXED_PLL 3 +> /* CLKID_FCLK_DIV2 */ > diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt- > bindings/clock/gxbb-clkc.h > index 4516bc4253b5..54faf83a4851 100644 > --- a/include/dt-bindings/clock/gxbb-clkc.h > +++ b/include/dt-bindings/clock/gxbb-clkc.h > @@ -5,7 +5,6 @@ -> ?#ifndef __GXBB_CLKC_H -> ?#define __GXBB_CLKC_H -> ? +> #ifndef __GXBB_CLKC_H +> #define __GXBB_CLKC_H +> > -#define CLKID_CPUCLK 1 -> ?#define CLKID_HDMI_PLL 2 -> ?#define CLKID_FCLK_DIV2 4 -> ?#define CLKID_FCLK_DIV3 5 +> #define CLKID_HDMI_PLL 2 +> #define CLKID_FCLK_DIV2 4 +> #define CLKID_FCLK_DIV3 5 diff --git a/a/content_digest b/N1/content_digest index 547391c..3180945 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,18 @@ "ref\020170401125519.7339-1-martin.blumenstingl@googlemail.com\0" "ref\020170401125519.7339-2-martin.blumenstingl@googlemail.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH 1/1] clk: meson: gxbb: remove the \"cpu_clk\" from the GXBB and GXL driver\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH 1/1] clk: meson: gxbb: remove the \"cpu_clk\" from the GXBB and GXL driver\0" "Date\0Sun, 02 Apr 2017 17:57:45 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Martin Blumenstingl <martin.blumenstingl@googlemail.com>" + devicetree@vger.kernel.org + linux-amlogic@lists.infradead.org + " linux-clk@vger.kernel.org\0" + "Cc\0khilman@baylibre.com" + carlo@caione.org + sboyd@codeaurora.org + mturquette@baylibre.com + linux-arm-kernel@lists.infradead.org + " Neil Armstrong <narmstrong@baylibre.com>\0" "\00:1\0" "b\0" "On Sat, 2017-04-01 at 14:55 +0200, Martin Blumenstingl wrote:\n" @@ -38,11 +47,11 @@ "Cheers\n" "\n" "> ---\n" - "> ?drivers/clk/meson/gxbb.c??????????????| 64 ++------------------------------\n" + "> \302\240drivers/clk/meson/gxbb.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 64 ++------------------------------\n" "> ---\n" - "> ?drivers/clk/meson/gxbb.h??????????????|??2 +-\n" - "> ?include/dt-bindings/clock/gxbb-clkc.h |??1 -\n" - "> ?3 files changed, 4 insertions(+), 63 deletions(-)\n" + "> \302\240drivers/clk/meson/gxbb.h\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2402 +-\n" + "> \302\240include/dt-bindings/clock/gxbb-clkc.h |\302\240\302\2401 -\n" + "> \302\2403 files changed, 4 insertions(+), 63 deletions(-)\n" "> \n" "> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c\n" "> index ad5f027af1a2..7cf88ca9bdce 100644\n" @@ -50,9 +59,9 @@ "> +++ b/drivers/clk/meson/gxbb.c\n" "> @@ -278,20 +278,6 @@ static const struct pll_rate_table\n" "> gxl_gp0_pll_rate_table[] = {\n" - "> ?\t{ /* sentinel */ },\n" - "> ?};\n" - "> ?\n" + "> \302\240\t{ /* sentinel */ },\n" + "> \302\240};\n" + "> \302\240\n" "> -static const struct clk_div_table cpu_div_table[] = {\n" "> -\t{ .val = 1, .div = 1 },\n" "> -\t{ .val = 2, .div = 2 },\n" @@ -67,20 +76,20 @@ "> -\t{ /* sentinel */ },\n" "> -};\n" "> -\n" - "> ?static struct meson_clk_pll gxbb_fixed_pll = {\n" - "> ?\t.m = {\n" - "> ?\t\t.reg_off = HHI_MPLL_CNTL,\n" + "> \302\240static struct meson_clk_pll gxbb_fixed_pll = {\n" + "> \302\240\t.m = {\n" + "> \302\240\t\t.reg_off = HHI_MPLL_CNTL,\n" "> @@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = {\n" - "> ?};\n" - "> ?\n" - "> ?/*\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240/*\n" "> - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL\n" "> - * post-dividers and should be modeled with their respective PLLs via the\n" "> - * forthcoming coordinated clock rates feature\n" "> + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers\n" "> + * and should be modeled with their respective PLLs via the forthcoming\n" "> + * coordinated clock rates feature\n" - "> ? */\n" + "> \302\240 */\n" "> -static struct meson_clk_cpu gxbb_cpu_clk = {\n" "> -\t.reg_off = HHI_SYS_CPU_CLK_CNTL1,\n" "> -\t.div_table = cpu_div_table,\n" @@ -92,90 +101,90 @@ "> -\t\t.num_parents = 1,\n" "> -\t},\n" "> -};\n" - "> ?\n" - "> ?static u32 mux_table_clk81[]\t= { 6, 5, 7 };\n" - "> ?\n" + "> \302\240\n" + "> \302\240static u32 mux_table_clk81[]\t= { 6, 5, 7 };\n" + "> \302\240\n" "> @@ -1045,7 +1020,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);\n" - "> ?static struct clk_hw_onecell_data gxbb_hw_onecell_data = {\n" - "> ?\t.hws = {\n" - "> ?\t\t[CLKID_SYS_PLL]\t\t????= &gxbb_sys_pll.hw,\n" - "> -\t\t[CLKID_CPUCLK]\t\t????= &gxbb_cpu_clk.hw,\n" - "> ?\t\t[CLKID_HDMI_PLL]\t????= &gxbb_hdmi_pll.hw,\n" - "> ?\t\t[CLKID_FIXED_PLL]\t????= &gxbb_fixed_pll.hw,\n" - "> ?\t\t[CLKID_FCLK_DIV2]\t????= &gxbb_fclk_div2.hw,\n" + "> \302\240static struct clk_hw_onecell_data gxbb_hw_onecell_data = {\n" + "> \302\240\t.hws = {\n" + "> \302\240\t\t[CLKID_SYS_PLL]\t\t\302\240\302\240\302\240\302\240= &gxbb_sys_pll.hw,\n" + "> -\t\t[CLKID_CPUCLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_cpu_clk.hw,\n" + "> \302\240\t\t[CLKID_HDMI_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_hdmi_pll.hw,\n" + "> \302\240\t\t[CLKID_FIXED_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_fixed_pll.hw,\n" + "> \302\240\t\t[CLKID_FCLK_DIV2]\t\302\240\302\240\302\240\302\240= &gxbb_fclk_div2.hw,\n" "> @@ -1165,7 +1139,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data =\n" "> {\n" - "> ?static struct clk_hw_onecell_data gxl_hw_onecell_data = {\n" - "> ?\t.hws = {\n" - "> ?\t\t[CLKID_SYS_PLL]\t\t????= &gxbb_sys_pll.hw,\n" - "> -\t\t[CLKID_CPUCLK]\t\t????= &gxbb_cpu_clk.hw,\n" - "> ?\t\t[CLKID_HDMI_PLL]\t????= &gxbb_hdmi_pll.hw,\n" - "> ?\t\t[CLKID_FIXED_PLL]\t????= &gxbb_fixed_pll.hw,\n" - "> ?\t\t[CLKID_FCLK_DIV2]\t????= &gxbb_fclk_div2.hw,\n" + "> \302\240static struct clk_hw_onecell_data gxl_hw_onecell_data = {\n" + "> \302\240\t.hws = {\n" + "> \302\240\t\t[CLKID_SYS_PLL]\t\t\302\240\302\240\302\240\302\240= &gxbb_sys_pll.hw,\n" + "> -\t\t[CLKID_CPUCLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_cpu_clk.hw,\n" + "> \302\240\t\t[CLKID_HDMI_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_hdmi_pll.hw,\n" + "> \302\240\t\t[CLKID_FIXED_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_fixed_pll.hw,\n" + "> \302\240\t\t[CLKID_FCLK_DIV2]\t\302\240\302\240\302\240\302\240= &gxbb_fclk_div2.hw,\n" "> @@ -1430,7 +1403,6 @@ struct clkc_data {\n" - "> ?\tunsigned int clk_dividers_count;\n" - "> ?\tstruct meson_clk_audio_divider *const *clk_audio_dividers;\n" - "> ?\tunsigned int clk_audio_dividers_count;\n" + "> \302\240\tunsigned int clk_dividers_count;\n" + "> \302\240\tstruct meson_clk_audio_divider *const *clk_audio_dividers;\n" + "> \302\240\tunsigned int clk_audio_dividers_count;\n" "> -\tstruct meson_clk_cpu *cpu_clk;\n" - "> ?\tstruct clk_hw_onecell_data *hw_onecell_data;\n" - "> ?};\n" - "> ?\n" + "> \302\240\tstruct clk_hw_onecell_data *hw_onecell_data;\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1447,7 +1419,6 @@ static const struct clkc_data gxbb_clkc_data = {\n" - "> ?\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" - "> ?\t.clk_audio_dividers = gxbb_audio_dividers,\n" - "> ?\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" + "> \302\240\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" + "> \302\240\t.clk_audio_dividers = gxbb_audio_dividers,\n" + "> \302\240\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" "> -\t.cpu_clk = &gxbb_cpu_clk,\n" - "> ?\t.hw_onecell_data = &gxbb_hw_onecell_data,\n" - "> ?};\n" - "> ?\n" + "> \302\240\t.hw_onecell_data = &gxbb_hw_onecell_data,\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1464,7 +1435,6 @@ static const struct clkc_data gxl_clkc_data = {\n" - "> ?\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" - "> ?\t.clk_audio_dividers = gxbb_audio_dividers,\n" - "> ?\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" + "> \302\240\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" + "> \302\240\t.clk_audio_dividers = gxbb_audio_dividers,\n" + "> \302\240\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" "> -\t.cpu_clk = &gxbb_cpu_clk,\n" - "> ?\t.hw_onecell_data = &gxl_hw_onecell_data,\n" - "> ?};\n" - "> ?\n" + "> \302\240\t.hw_onecell_data = &gxl_hw_onecell_data,\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1479,8 +1449,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)\n" - "> ?\tconst struct clkc_data *clkc_data;\n" - "> ?\tvoid __iomem *clk_base;\n" - "> ?\tint ret, clkid, i;\n" + "> \302\240\tconst struct clkc_data *clkc_data;\n" + "> \302\240\tvoid __iomem *clk_base;\n" + "> \302\240\tint ret, clkid, i;\n" "> -\tstruct clk_hw *parent_hw;\n" "> -\tstruct clk *parent_clk;\n" - "> ?\tstruct device *dev = &pdev->dev;\n" - "> ?\n" - "> ?\tclkc_data = of_device_get_match_data(&pdev->dev);\n" + "> \302\240\tstruct device *dev = &pdev->dev;\n" + "> \302\240\n" + "> \302\240\tclkc_data = of_device_get_match_data(&pdev->dev);\n" "> @@ -1502,9 +1470,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)\n" - "> ?\tfor (i = 0; i < clkc_data->clk_mplls_count; i++)\n" - "> ?\t\tclkc_data->clk_mplls[i]->base = clk_base;\n" - "> ?\n" + "> \302\240\tfor (i = 0; i < clkc_data->clk_mplls_count; i++)\n" + "> \302\240\t\tclkc_data->clk_mplls[i]->base = clk_base;\n" + "> \302\240\n" "> -\t/* Populate the base address for CPU clk */\n" "> -\tclkc_data->cpu_clk->base = clk_base;\n" "> -\n" - "> ?\t/* Populate base address for gates */\n" - "> ?\tfor (i = 0; i < clkc_data->clk_gates_count; i++)\n" - "> ?\t\tclkc_data->clk_gates[i]->reg = clk_base +\n" + "> \302\240\t/* Populate base address for gates */\n" + "> \302\240\tfor (i = 0; i < clkc_data->clk_gates_count; i++)\n" + "> \302\240\t\tclkc_data->clk_gates[i]->reg = clk_base +\n" "> @@ -1538,29 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device\n" "> *pdev)\n" - "> ?\t\t\tgoto iounmap;\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t\t\tgoto iounmap;\n" + "> \302\240\t}\n" + "> \302\240\n" "> -\t/*\n" - "> -\t?* Register CPU clk notifier\n" - "> -\t?*\n" - "> -\t?* FIXME this is wrong for a lot of reasons. First, the muxes should\n" + "> -\t\302\240* Register CPU clk notifier\n" + "> -\t\302\240*\n" + "> -\t\302\240* FIXME this is wrong for a lot of reasons. First, the muxes should\n" "> be\n" - "> -\t?* struct clk_hw objects. Second, we shouldn't program the muxes in\n" - "> -\t?* notifier handlers. The tricky programming sequence will be handled\n" - "> -\t?* by the forthcoming coordinated clock rates mechanism once that\n" - "> -\t?* feature is released.\n" - "> -\t?*\n" - "> -\t?* Furthermore, looking up the parent this way is terrible. At some\n" - "> -\t?* point we will stop allocating a default struct clk when\n" + "> -\t\302\240* struct clk_hw objects. Second, we shouldn't program the muxes in\n" + "> -\t\302\240* notifier handlers. The tricky programming sequence will be handled\n" + "> -\t\302\240* by the forthcoming coordinated clock rates mechanism once that\n" + "> -\t\302\240* feature is released.\n" + "> -\t\302\240*\n" + "> -\t\302\240* Furthermore, looking up the parent this way is terrible. At some\n" + "> -\t\302\240* point we will stop allocating a default struct clk when\n" "> registering\n" - "> -\t?* a new clk_hw, and this hack will no longer work. Releasing the ccr\n" - "> -\t?* feature before that time solves the problem :-)\n" - "> -\t?*/\n" + "> -\t\302\240* a new clk_hw, and this hack will no longer work. Releasing the ccr\n" + "> -\t\302\240* feature before that time solves the problem :-)\n" + "> -\t\302\240*/\n" "> -\tparent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw);\n" "> -\tparent_clk = parent_hw->clk;\n" "> -\tret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb);\n" @@ -185,34 +194,34 @@ "> -\t\tgoto iounmap;\n" "> -\t}\n" "> -\n" - "> ?\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n" - "> ?\t\t\tclkc_data->hw_onecell_data);\n" - "> ?\n" + "> \302\240\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n" + "> \302\240\t\t\tclkc_data->hw_onecell_data);\n" + "> \302\240\n" "> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h\n" "> index 17c6aef033ff..36330c2d4433 100644\n" "> --- a/drivers/clk/meson/gxbb.h\n" "> +++ b/drivers/clk/meson/gxbb.h\n" "> @@ -171,7 +171,7 @@\n" - "> ? * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h\n" - "> ? */\n" - "> ?#define CLKID_SYS_PLL\t\t??0\n" + "> \302\240 * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h\n" + "> \302\240 */\n" + "> \302\240#define CLKID_SYS_PLL\t\t\302\240\302\2400\n" "> -/* CLKID_CPUCLK */\n" "> +/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */\n" - "> ?/* CLKID_HDMI_PLL */\n" - "> ?#define CLKID_FIXED_PLL\t\t??3\n" - "> ?/* CLKID_FCLK_DIV2 */\n" + "> \302\240/* CLKID_HDMI_PLL */\n" + "> \302\240#define CLKID_FIXED_PLL\t\t\302\240\302\2403\n" + "> \302\240/* CLKID_FCLK_DIV2 */\n" "> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-\n" "> bindings/clock/gxbb-clkc.h\n" "> index 4516bc4253b5..54faf83a4851 100644\n" "> --- a/include/dt-bindings/clock/gxbb-clkc.h\n" "> +++ b/include/dt-bindings/clock/gxbb-clkc.h\n" "> @@ -5,7 +5,6 @@\n" - "> ?#ifndef __GXBB_CLKC_H\n" - "> ?#define __GXBB_CLKC_H\n" - "> ?\n" + "> \302\240#ifndef __GXBB_CLKC_H\n" + "> \302\240#define __GXBB_CLKC_H\n" + "> \302\240\n" "> -#define CLKID_CPUCLK\t\t1\n" - "> ?#define CLKID_HDMI_PLL\t\t2\n" - "> ?#define CLKID_FCLK_DIV2\t\t4\n" - "> ?#define CLKID_FCLK_DIV3\t\t5" + "> \302\240#define CLKID_HDMI_PLL\t\t2\n" + "> \302\240#define CLKID_FCLK_DIV2\t\t4\n" + "> \302\240#define CLKID_FCLK_DIV3\t\t5" -04dcfc59893d912f9bcf96ce92ad9df517eeff346445aedd95da55ce16ae68b3 +5fbb3e845699e6f9c3636e09d1b28bae0d0dde9253bd0e8d980f8192cb0b323e
diff --git a/a/content_digest b/N2/content_digest index 547391c..2cf8c66 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,7 +3,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH 1/1] clk: meson: gxbb: remove the \"cpu_clk\" from the GXBB and GXL driver\0" "Date\0Sun, 02 Apr 2017 17:57:45 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Sat, 2017-04-01 at 14:55 +0200, Martin Blumenstingl wrote:\n" @@ -215,4 +215,4 @@ "> ?#define CLKID_FCLK_DIV2\t\t4\n" "> ?#define CLKID_FCLK_DIV3\t\t5" -04dcfc59893d912f9bcf96ce92ad9df517eeff346445aedd95da55ce16ae68b3 +d9a20af3780467f1567b93fe6ebed6a4e1c836cf5c54908044cc501e9e5f4174
diff --git a/a/1.txt b/N3/1.txt index dc8c2d4..a73847a 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -21,7 +21,7 @@ On Sat, 2017-04-01 at 14:55 +0200, Martin Blumenstingl wrote: > now a hole in the clk_hw_onecell_data (which is not a problem because > this case is already handled in gxbb_clkc_probe). > -> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> Looks good to me. I'll wait for the Ack of one of the DT maintainers to apply it. @@ -30,11 +30,11 @@ Thx Martin Cheers > --- -> ?drivers/clk/meson/gxbb.c??????????????| 64 ++------------------------------ +> drivers/clk/meson/gxbb.c | 64 ++------------------------------ > --- -> ?drivers/clk/meson/gxbb.h??????????????|??2 +- -> ?include/dt-bindings/clock/gxbb-clkc.h |??1 - -> ?3 files changed, 4 insertions(+), 63 deletions(-) +> drivers/clk/meson/gxbb.h | 2 +- +> include/dt-bindings/clock/gxbb-clkc.h | 1 - +> 3 files changed, 4 insertions(+), 63 deletions(-) > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index ad5f027af1a2..7cf88ca9bdce 100644 @@ -42,9 +42,9 @@ Cheers > +++ b/drivers/clk/meson/gxbb.c > @@ -278,20 +278,6 @@ static const struct pll_rate_table > gxl_gp0_pll_rate_table[] = { -> ? { /* sentinel */ }, -> ?}; -> ? +> { /* sentinel */ }, +> }; +> > -static const struct clk_div_table cpu_div_table[] = { > - { .val = 1, .div = 1 }, > - { .val = 2, .div = 2 }, @@ -59,20 +59,20 @@ Cheers > - { /* sentinel */ }, > -}; > - -> ?static struct meson_clk_pll gxbb_fixed_pll = { -> ? .m = { -> ? .reg_off = HHI_MPLL_CNTL, +> static struct meson_clk_pll gxbb_fixed_pll = { +> .m = { +> .reg_off = HHI_MPLL_CNTL, > @@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = { -> ?}; -> ? -> ?/* +> }; +> +> /* > - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL > - * post-dividers and should be modeled with their respective PLLs via the > - * forthcoming coordinated clock rates feature > + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers > + * and should be modeled with their respective PLLs via the forthcoming > + * coordinated clock rates feature -> ? */ +> */ > -static struct meson_clk_cpu gxbb_cpu_clk = { > - .reg_off = HHI_SYS_CPU_CLK_CNTL1, > - .div_table = cpu_div_table, @@ -84,90 +84,90 @@ Cheers > - .num_parents = 1, > - }, > -}; -> ? -> ?static u32 mux_table_clk81[] = { 6, 5, 7 }; -> ? +> +> static u32 mux_table_clk81[] = { 6, 5, 7 }; +> > @@ -1045,7 +1020,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); -> ?static struct clk_hw_onecell_data gxbb_hw_onecell_data = { -> ? .hws = { -> ? [CLKID_SYS_PLL] ????= &gxbb_sys_pll.hw, -> - [CLKID_CPUCLK] ????= &gxbb_cpu_clk.hw, -> ? [CLKID_HDMI_PLL] ????= &gxbb_hdmi_pll.hw, -> ? [CLKID_FIXED_PLL] ????= &gxbb_fixed_pll.hw, -> ? [CLKID_FCLK_DIV2] ????= &gxbb_fclk_div2.hw, +> static struct clk_hw_onecell_data gxbb_hw_onecell_data = { +> .hws = { +> [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, +> - [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, +> [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, +> [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, +> [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, > @@ -1165,7 +1139,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = > { -> ?static struct clk_hw_onecell_data gxl_hw_onecell_data = { -> ? .hws = { -> ? [CLKID_SYS_PLL] ????= &gxbb_sys_pll.hw, -> - [CLKID_CPUCLK] ????= &gxbb_cpu_clk.hw, -> ? [CLKID_HDMI_PLL] ????= &gxbb_hdmi_pll.hw, -> ? [CLKID_FIXED_PLL] ????= &gxbb_fixed_pll.hw, -> ? [CLKID_FCLK_DIV2] ????= &gxbb_fclk_div2.hw, +> static struct clk_hw_onecell_data gxl_hw_onecell_data = { +> .hws = { +> [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, +> - [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, +> [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, +> [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, +> [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, > @@ -1430,7 +1403,6 @@ struct clkc_data { -> ? unsigned int clk_dividers_count; -> ? struct meson_clk_audio_divider *const *clk_audio_dividers; -> ? unsigned int clk_audio_dividers_count; +> unsigned int clk_dividers_count; +> struct meson_clk_audio_divider *const *clk_audio_dividers; +> unsigned int clk_audio_dividers_count; > - struct meson_clk_cpu *cpu_clk; -> ? struct clk_hw_onecell_data *hw_onecell_data; -> ?}; -> ? +> struct clk_hw_onecell_data *hw_onecell_data; +> }; +> > @@ -1447,7 +1419,6 @@ static const struct clkc_data gxbb_clkc_data = { -> ? .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), -> ? .clk_audio_dividers = gxbb_audio_dividers, -> ? .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), +> .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), +> .clk_audio_dividers = gxbb_audio_dividers, +> .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), > - .cpu_clk = &gxbb_cpu_clk, -> ? .hw_onecell_data = &gxbb_hw_onecell_data, -> ?}; -> ? +> .hw_onecell_data = &gxbb_hw_onecell_data, +> }; +> > @@ -1464,7 +1435,6 @@ static const struct clkc_data gxl_clkc_data = { -> ? .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), -> ? .clk_audio_dividers = gxbb_audio_dividers, -> ? .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), +> .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), +> .clk_audio_dividers = gxbb_audio_dividers, +> .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), > - .cpu_clk = &gxbb_cpu_clk, -> ? .hw_onecell_data = &gxl_hw_onecell_data, -> ?}; -> ? +> .hw_onecell_data = &gxl_hw_onecell_data, +> }; +> > @@ -1479,8 +1449,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) -> ? const struct clkc_data *clkc_data; -> ? void __iomem *clk_base; -> ? int ret, clkid, i; +> const struct clkc_data *clkc_data; +> void __iomem *clk_base; +> int ret, clkid, i; > - struct clk_hw *parent_hw; > - struct clk *parent_clk; -> ? struct device *dev = &pdev->dev; -> ? -> ? clkc_data = of_device_get_match_data(&pdev->dev); +> struct device *dev = &pdev->dev; +> +> clkc_data = of_device_get_match_data(&pdev->dev); > @@ -1502,9 +1470,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) -> ? for (i = 0; i < clkc_data->clk_mplls_count; i++) -> ? clkc_data->clk_mplls[i]->base = clk_base; -> ? +> for (i = 0; i < clkc_data->clk_mplls_count; i++) +> clkc_data->clk_mplls[i]->base = clk_base; +> > - /* Populate the base address for CPU clk */ > - clkc_data->cpu_clk->base = clk_base; > - -> ? /* Populate base address for gates */ -> ? for (i = 0; i < clkc_data->clk_gates_count; i++) -> ? clkc_data->clk_gates[i]->reg = clk_base + +> /* Populate base address for gates */ +> for (i = 0; i < clkc_data->clk_gates_count; i++) +> clkc_data->clk_gates[i]->reg = clk_base + > @@ -1538,29 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device > *pdev) -> ? goto iounmap; -> ? } -> ? +> goto iounmap; +> } +> > - /* -> - ?* Register CPU clk notifier -> - ?* -> - ?* FIXME this is wrong for a lot of reasons. First, the muxes should +> - * Register CPU clk notifier +> - * +> - * FIXME this is wrong for a lot of reasons. First, the muxes should > be -> - ?* struct clk_hw objects. Second, we shouldn't program the muxes in -> - ?* notifier handlers. The tricky programming sequence will be handled -> - ?* by the forthcoming coordinated clock rates mechanism once that -> - ?* feature is released. -> - ?* -> - ?* Furthermore, looking up the parent this way is terrible. At some -> - ?* point we will stop allocating a default struct clk when +> - * struct clk_hw objects. Second, we shouldn't program the muxes in +> - * notifier handlers. The tricky programming sequence will be handled +> - * by the forthcoming coordinated clock rates mechanism once that +> - * feature is released. +> - * +> - * Furthermore, looking up the parent this way is terrible. At some +> - * point we will stop allocating a default struct clk when > registering -> - ?* a new clk_hw, and this hack will no longer work. Releasing the ccr -> - ?* feature before that time solves the problem :-) -> - ?*/ +> - * a new clk_hw, and this hack will no longer work. Releasing the ccr +> - * feature before that time solves the problem :-) +> - */ > - parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw); > - parent_clk = parent_hw->clk; > - ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb); @@ -177,32 +177,36 @@ Cheers > - goto iounmap; > - } > - -> ? return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, -> ? clkc_data->hw_onecell_data); -> ? +> return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, +> clkc_data->hw_onecell_data); +> > diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h > index 17c6aef033ff..36330c2d4433 100644 > --- a/drivers/clk/meson/gxbb.h > +++ b/drivers/clk/meson/gxbb.h > @@ -171,7 +171,7 @@ -> ? * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h -> ? */ -> ?#define CLKID_SYS_PLL ??0 +> * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h +> */ +> #define CLKID_SYS_PLL 0 > -/* CLKID_CPUCLK */ > +/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */ -> ?/* CLKID_HDMI_PLL */ -> ?#define CLKID_FIXED_PLL ??3 -> ?/* CLKID_FCLK_DIV2 */ +> /* CLKID_HDMI_PLL */ +> #define CLKID_FIXED_PLL 3 +> /* CLKID_FCLK_DIV2 */ > diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt- > bindings/clock/gxbb-clkc.h > index 4516bc4253b5..54faf83a4851 100644 > --- a/include/dt-bindings/clock/gxbb-clkc.h > +++ b/include/dt-bindings/clock/gxbb-clkc.h > @@ -5,7 +5,6 @@ -> ?#ifndef __GXBB_CLKC_H -> ?#define __GXBB_CLKC_H -> ? +> #ifndef __GXBB_CLKC_H +> #define __GXBB_CLKC_H +> > -#define CLKID_CPUCLK 1 -> ?#define CLKID_HDMI_PLL 2 -> ?#define CLKID_FCLK_DIV2 4 -> ?#define CLKID_FCLK_DIV3 5 +> #define CLKID_HDMI_PLL 2 +> #define CLKID_FCLK_DIV2 4 +> #define CLKID_FCLK_DIV3 5 +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N3/content_digest index 547391c..7bb9482 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,9 +1,19 @@ "ref\020170401125519.7339-1-martin.blumenstingl@googlemail.com\0" "ref\020170401125519.7339-2-martin.blumenstingl@googlemail.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH 1/1] clk: meson: gxbb: remove the \"cpu_clk\" from the GXBB and GXL driver\0" + "ref\020170401125519.7339-2-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org\0" + "From\0Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH 1/1] clk: meson: gxbb: remove the \"cpu_clk\" from the GXBB and GXL driver\0" "Date\0Sun, 02 Apr 2017 17:57:45 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org" + carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org + sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" "\00:1\0" "b\0" "On Sat, 2017-04-01 at 14:55 +0200, Martin Blumenstingl wrote:\n" @@ -29,7 +39,7 @@ "> now a hole in the clk_hw_onecell_data (which is not a problem because\n" "> this case is already handled in gxbb_clkc_probe).\n" "> \n" - "> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" + "> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>\n" "\n" "Looks good to me.\n" "I'll wait for the Ack of one of the DT maintainers to apply it.\n" @@ -38,11 +48,11 @@ "Cheers\n" "\n" "> ---\n" - "> ?drivers/clk/meson/gxbb.c??????????????| 64 ++------------------------------\n" + "> \302\240drivers/clk/meson/gxbb.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 64 ++------------------------------\n" "> ---\n" - "> ?drivers/clk/meson/gxbb.h??????????????|??2 +-\n" - "> ?include/dt-bindings/clock/gxbb-clkc.h |??1 -\n" - "> ?3 files changed, 4 insertions(+), 63 deletions(-)\n" + "> \302\240drivers/clk/meson/gxbb.h\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2402 +-\n" + "> \302\240include/dt-bindings/clock/gxbb-clkc.h |\302\240\302\2401 -\n" + "> \302\2403 files changed, 4 insertions(+), 63 deletions(-)\n" "> \n" "> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c\n" "> index ad5f027af1a2..7cf88ca9bdce 100644\n" @@ -50,9 +60,9 @@ "> +++ b/drivers/clk/meson/gxbb.c\n" "> @@ -278,20 +278,6 @@ static const struct pll_rate_table\n" "> gxl_gp0_pll_rate_table[] = {\n" - "> ?\t{ /* sentinel */ },\n" - "> ?};\n" - "> ?\n" + "> \302\240\t{ /* sentinel */ },\n" + "> \302\240};\n" + "> \302\240\n" "> -static const struct clk_div_table cpu_div_table[] = {\n" "> -\t{ .val = 1, .div = 1 },\n" "> -\t{ .val = 2, .div = 2 },\n" @@ -67,20 +77,20 @@ "> -\t{ /* sentinel */ },\n" "> -};\n" "> -\n" - "> ?static struct meson_clk_pll gxbb_fixed_pll = {\n" - "> ?\t.m = {\n" - "> ?\t\t.reg_off = HHI_MPLL_CNTL,\n" + "> \302\240static struct meson_clk_pll gxbb_fixed_pll = {\n" + "> \302\240\t.m = {\n" + "> \302\240\t\t.reg_off = HHI_MPLL_CNTL,\n" "> @@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = {\n" - "> ?};\n" - "> ?\n" - "> ?/*\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240/*\n" "> - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL\n" "> - * post-dividers and should be modeled with their respective PLLs via the\n" "> - * forthcoming coordinated clock rates feature\n" "> + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers\n" "> + * and should be modeled with their respective PLLs via the forthcoming\n" "> + * coordinated clock rates feature\n" - "> ? */\n" + "> \302\240 */\n" "> -static struct meson_clk_cpu gxbb_cpu_clk = {\n" "> -\t.reg_off = HHI_SYS_CPU_CLK_CNTL1,\n" "> -\t.div_table = cpu_div_table,\n" @@ -92,90 +102,90 @@ "> -\t\t.num_parents = 1,\n" "> -\t},\n" "> -};\n" - "> ?\n" - "> ?static u32 mux_table_clk81[]\t= { 6, 5, 7 };\n" - "> ?\n" + "> \302\240\n" + "> \302\240static u32 mux_table_clk81[]\t= { 6, 5, 7 };\n" + "> \302\240\n" "> @@ -1045,7 +1020,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);\n" - "> ?static struct clk_hw_onecell_data gxbb_hw_onecell_data = {\n" - "> ?\t.hws = {\n" - "> ?\t\t[CLKID_SYS_PLL]\t\t????= &gxbb_sys_pll.hw,\n" - "> -\t\t[CLKID_CPUCLK]\t\t????= &gxbb_cpu_clk.hw,\n" - "> ?\t\t[CLKID_HDMI_PLL]\t????= &gxbb_hdmi_pll.hw,\n" - "> ?\t\t[CLKID_FIXED_PLL]\t????= &gxbb_fixed_pll.hw,\n" - "> ?\t\t[CLKID_FCLK_DIV2]\t????= &gxbb_fclk_div2.hw,\n" + "> \302\240static struct clk_hw_onecell_data gxbb_hw_onecell_data = {\n" + "> \302\240\t.hws = {\n" + "> \302\240\t\t[CLKID_SYS_PLL]\t\t\302\240\302\240\302\240\302\240= &gxbb_sys_pll.hw,\n" + "> -\t\t[CLKID_CPUCLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_cpu_clk.hw,\n" + "> \302\240\t\t[CLKID_HDMI_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_hdmi_pll.hw,\n" + "> \302\240\t\t[CLKID_FIXED_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_fixed_pll.hw,\n" + "> \302\240\t\t[CLKID_FCLK_DIV2]\t\302\240\302\240\302\240\302\240= &gxbb_fclk_div2.hw,\n" "> @@ -1165,7 +1139,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data =\n" "> {\n" - "> ?static struct clk_hw_onecell_data gxl_hw_onecell_data = {\n" - "> ?\t.hws = {\n" - "> ?\t\t[CLKID_SYS_PLL]\t\t????= &gxbb_sys_pll.hw,\n" - "> -\t\t[CLKID_CPUCLK]\t\t????= &gxbb_cpu_clk.hw,\n" - "> ?\t\t[CLKID_HDMI_PLL]\t????= &gxbb_hdmi_pll.hw,\n" - "> ?\t\t[CLKID_FIXED_PLL]\t????= &gxbb_fixed_pll.hw,\n" - "> ?\t\t[CLKID_FCLK_DIV2]\t????= &gxbb_fclk_div2.hw,\n" + "> \302\240static struct clk_hw_onecell_data gxl_hw_onecell_data = {\n" + "> \302\240\t.hws = {\n" + "> \302\240\t\t[CLKID_SYS_PLL]\t\t\302\240\302\240\302\240\302\240= &gxbb_sys_pll.hw,\n" + "> -\t\t[CLKID_CPUCLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_cpu_clk.hw,\n" + "> \302\240\t\t[CLKID_HDMI_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_hdmi_pll.hw,\n" + "> \302\240\t\t[CLKID_FIXED_PLL]\t\302\240\302\240\302\240\302\240= &gxbb_fixed_pll.hw,\n" + "> \302\240\t\t[CLKID_FCLK_DIV2]\t\302\240\302\240\302\240\302\240= &gxbb_fclk_div2.hw,\n" "> @@ -1430,7 +1403,6 @@ struct clkc_data {\n" - "> ?\tunsigned int clk_dividers_count;\n" - "> ?\tstruct meson_clk_audio_divider *const *clk_audio_dividers;\n" - "> ?\tunsigned int clk_audio_dividers_count;\n" + "> \302\240\tunsigned int clk_dividers_count;\n" + "> \302\240\tstruct meson_clk_audio_divider *const *clk_audio_dividers;\n" + "> \302\240\tunsigned int clk_audio_dividers_count;\n" "> -\tstruct meson_clk_cpu *cpu_clk;\n" - "> ?\tstruct clk_hw_onecell_data *hw_onecell_data;\n" - "> ?};\n" - "> ?\n" + "> \302\240\tstruct clk_hw_onecell_data *hw_onecell_data;\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1447,7 +1419,6 @@ static const struct clkc_data gxbb_clkc_data = {\n" - "> ?\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" - "> ?\t.clk_audio_dividers = gxbb_audio_dividers,\n" - "> ?\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" + "> \302\240\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" + "> \302\240\t.clk_audio_dividers = gxbb_audio_dividers,\n" + "> \302\240\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" "> -\t.cpu_clk = &gxbb_cpu_clk,\n" - "> ?\t.hw_onecell_data = &gxbb_hw_onecell_data,\n" - "> ?};\n" - "> ?\n" + "> \302\240\t.hw_onecell_data = &gxbb_hw_onecell_data,\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1464,7 +1435,6 @@ static const struct clkc_data gxl_clkc_data = {\n" - "> ?\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" - "> ?\t.clk_audio_dividers = gxbb_audio_dividers,\n" - "> ?\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" + "> \302\240\t.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),\n" + "> \302\240\t.clk_audio_dividers = gxbb_audio_dividers,\n" + "> \302\240\t.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),\n" "> -\t.cpu_clk = &gxbb_cpu_clk,\n" - "> ?\t.hw_onecell_data = &gxl_hw_onecell_data,\n" - "> ?};\n" - "> ?\n" + "> \302\240\t.hw_onecell_data = &gxl_hw_onecell_data,\n" + "> \302\240};\n" + "> \302\240\n" "> @@ -1479,8 +1449,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)\n" - "> ?\tconst struct clkc_data *clkc_data;\n" - "> ?\tvoid __iomem *clk_base;\n" - "> ?\tint ret, clkid, i;\n" + "> \302\240\tconst struct clkc_data *clkc_data;\n" + "> \302\240\tvoid __iomem *clk_base;\n" + "> \302\240\tint ret, clkid, i;\n" "> -\tstruct clk_hw *parent_hw;\n" "> -\tstruct clk *parent_clk;\n" - "> ?\tstruct device *dev = &pdev->dev;\n" - "> ?\n" - "> ?\tclkc_data = of_device_get_match_data(&pdev->dev);\n" + "> \302\240\tstruct device *dev = &pdev->dev;\n" + "> \302\240\n" + "> \302\240\tclkc_data = of_device_get_match_data(&pdev->dev);\n" "> @@ -1502,9 +1470,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)\n" - "> ?\tfor (i = 0; i < clkc_data->clk_mplls_count; i++)\n" - "> ?\t\tclkc_data->clk_mplls[i]->base = clk_base;\n" - "> ?\n" + "> \302\240\tfor (i = 0; i < clkc_data->clk_mplls_count; i++)\n" + "> \302\240\t\tclkc_data->clk_mplls[i]->base = clk_base;\n" + "> \302\240\n" "> -\t/* Populate the base address for CPU clk */\n" "> -\tclkc_data->cpu_clk->base = clk_base;\n" "> -\n" - "> ?\t/* Populate base address for gates */\n" - "> ?\tfor (i = 0; i < clkc_data->clk_gates_count; i++)\n" - "> ?\t\tclkc_data->clk_gates[i]->reg = clk_base +\n" + "> \302\240\t/* Populate base address for gates */\n" + "> \302\240\tfor (i = 0; i < clkc_data->clk_gates_count; i++)\n" + "> \302\240\t\tclkc_data->clk_gates[i]->reg = clk_base +\n" "> @@ -1538,29 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device\n" "> *pdev)\n" - "> ?\t\t\tgoto iounmap;\n" - "> ?\t}\n" - "> ?\n" + "> \302\240\t\t\tgoto iounmap;\n" + "> \302\240\t}\n" + "> \302\240\n" "> -\t/*\n" - "> -\t?* Register CPU clk notifier\n" - "> -\t?*\n" - "> -\t?* FIXME this is wrong for a lot of reasons. First, the muxes should\n" + "> -\t\302\240* Register CPU clk notifier\n" + "> -\t\302\240*\n" + "> -\t\302\240* FIXME this is wrong for a lot of reasons. First, the muxes should\n" "> be\n" - "> -\t?* struct clk_hw objects. Second, we shouldn't program the muxes in\n" - "> -\t?* notifier handlers. The tricky programming sequence will be handled\n" - "> -\t?* by the forthcoming coordinated clock rates mechanism once that\n" - "> -\t?* feature is released.\n" - "> -\t?*\n" - "> -\t?* Furthermore, looking up the parent this way is terrible. At some\n" - "> -\t?* point we will stop allocating a default struct clk when\n" + "> -\t\302\240* struct clk_hw objects. Second, we shouldn't program the muxes in\n" + "> -\t\302\240* notifier handlers. The tricky programming sequence will be handled\n" + "> -\t\302\240* by the forthcoming coordinated clock rates mechanism once that\n" + "> -\t\302\240* feature is released.\n" + "> -\t\302\240*\n" + "> -\t\302\240* Furthermore, looking up the parent this way is terrible. At some\n" + "> -\t\302\240* point we will stop allocating a default struct clk when\n" "> registering\n" - "> -\t?* a new clk_hw, and this hack will no longer work. Releasing the ccr\n" - "> -\t?* feature before that time solves the problem :-)\n" - "> -\t?*/\n" + "> -\t\302\240* a new clk_hw, and this hack will no longer work. Releasing the ccr\n" + "> -\t\302\240* feature before that time solves the problem :-)\n" + "> -\t\302\240*/\n" "> -\tparent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw);\n" "> -\tparent_clk = parent_hw->clk;\n" "> -\tret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb);\n" @@ -185,34 +195,38 @@ "> -\t\tgoto iounmap;\n" "> -\t}\n" "> -\n" - "> ?\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n" - "> ?\t\t\tclkc_data->hw_onecell_data);\n" - "> ?\n" + "> \302\240\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n" + "> \302\240\t\t\tclkc_data->hw_onecell_data);\n" + "> \302\240\n" "> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h\n" "> index 17c6aef033ff..36330c2d4433 100644\n" "> --- a/drivers/clk/meson/gxbb.h\n" "> +++ b/drivers/clk/meson/gxbb.h\n" "> @@ -171,7 +171,7 @@\n" - "> ? * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h\n" - "> ? */\n" - "> ?#define CLKID_SYS_PLL\t\t??0\n" + "> \302\240 * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h\n" + "> \302\240 */\n" + "> \302\240#define CLKID_SYS_PLL\t\t\302\240\302\2400\n" "> -/* CLKID_CPUCLK */\n" "> +/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */\n" - "> ?/* CLKID_HDMI_PLL */\n" - "> ?#define CLKID_FIXED_PLL\t\t??3\n" - "> ?/* CLKID_FCLK_DIV2 */\n" + "> \302\240/* CLKID_HDMI_PLL */\n" + "> \302\240#define CLKID_FIXED_PLL\t\t\302\240\302\2403\n" + "> \302\240/* CLKID_FCLK_DIV2 */\n" "> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-\n" "> bindings/clock/gxbb-clkc.h\n" "> index 4516bc4253b5..54faf83a4851 100644\n" "> --- a/include/dt-bindings/clock/gxbb-clkc.h\n" "> +++ b/include/dt-bindings/clock/gxbb-clkc.h\n" "> @@ -5,7 +5,6 @@\n" - "> ?#ifndef __GXBB_CLKC_H\n" - "> ?#define __GXBB_CLKC_H\n" - "> ?\n" + "> \302\240#ifndef __GXBB_CLKC_H\n" + "> \302\240#define __GXBB_CLKC_H\n" + "> \302\240\n" "> -#define CLKID_CPUCLK\t\t1\n" - "> ?#define CLKID_HDMI_PLL\t\t2\n" - "> ?#define CLKID_FCLK_DIV2\t\t4\n" - "> ?#define CLKID_FCLK_DIV3\t\t5" + "> \302\240#define CLKID_HDMI_PLL\t\t2\n" + "> \302\240#define CLKID_FCLK_DIV2\t\t4\n" + "> \302\240#define CLKID_FCLK_DIV3\t\t5\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -04dcfc59893d912f9bcf96ce92ad9df517eeff346445aedd95da55ce16ae68b3 +298efa514f9b07227870fcef2bd2d7b64fe7eb063e4781b57242c333c4c348b4
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