* [PATCH] drm/i915/guc: write wopcm related register once during uc init
@ 2017-04-07 0:18 Daniele Ceraolo Spurio
2017-04-07 0:39 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-04-13 10:59 ` [PATCH] " Joonas Lahtinen
0 siblings, 2 replies; 5+ messages in thread
From: Daniele Ceraolo Spurio @ 2017-04-07 0:18 UTC (permalink / raw)
To: intel-gfx
The wopcm registers are write-once, so any write after the first one
will just be ignored. The registers survive a GPU reset but not
always a suspend/resume cycle, so to keep things simple keep the
writes in the intel_uc_init_hw function instead of moving it earlier
to make sure we attempt them every time we try to load GuC.
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 4 ----
drivers/gpu/drm/i915/intel_huc.c | 5 -----
drivers/gpu/drm/i915/intel_uc.c | 5 +++++
3 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2793c01..7678873 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -280,10 +280,6 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- /* init WOPCM */
- I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
- I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
-
/* Enable MIA caching. GuC clock gating is disabled. */
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 385cacb..8cf34bc 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -99,11 +99,6 @@ static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- /* init WOPCM */
- I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
- I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
- HUC_LOADING_AGENT_GUC);
-
/* Set the source address for the uCode */
offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c117424..c14793e 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -274,6 +274,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
goto err_guc;
}
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET,
+ GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
+
/* WaEnableuKernelHeaderValidFix:skl */
/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
if (IS_GEN9(dev_priv))
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/guc: write wopcm related register once during uc init
2017-04-07 0:18 [PATCH] drm/i915/guc: write wopcm related register once during uc init Daniele Ceraolo Spurio
@ 2017-04-07 0:39 ` Patchwork
2017-04-13 11:02 ` Joonas Lahtinen
2017-04-13 10:59 ` [PATCH] " Joonas Lahtinen
1 sibling, 1 reply; 5+ messages in thread
From: Patchwork @ 2017-04-07 0:39 UTC (permalink / raw)
To: daniele.ceraolospurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/guc: write wopcm related register once during uc init
URL : https://patchwork.freedesktop.org/series/22625/
State : success
== Summary ==
Series 22625v1 drm/i915/guc: write wopcm related register once during uc init
https://patchwork.freedesktop.org/api/1.0/series/22625/revisions/1/mbox/
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 434s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time: 427s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time: 578s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 507s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 548s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time: 492s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 476s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 411s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 407s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 424s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 496s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 460s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 455s
fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 572s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 450s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 578s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 464s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 495s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time: 434s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 529s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 405s
7aafd5c8395fea9a79fbee82de4ffc63c04790d6 drm-tip: 2017y-04m-06d-21h-02m-00s UTC integration manifest
56dc4ac drm/i915/guc: write wopcm related register once during uc init
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4433/
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/guc: write wopcm related register once during uc init
2017-04-07 0:18 [PATCH] drm/i915/guc: write wopcm related register once during uc init Daniele Ceraolo Spurio
2017-04-07 0:39 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-04-13 10:59 ` Joonas Lahtinen
1 sibling, 0 replies; 5+ messages in thread
From: Joonas Lahtinen @ 2017-04-13 10:59 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On to, 2017-04-06 at 17:18 -0700, Daniele Ceraolo Spurio wrote:
> The wopcm registers are write-once, so any write after the first one
> will just be ignored. The registers survive a GPU reset but not
> always a suspend/resume cycle, so to keep things simple keep the
> writes in the intel_uc_init_hw function instead of moving it earlier
> to make sure we attempt them every time we try to load GuC.
>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
This is an improvement, so:
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To be exact, shouldn't we read the value and see if it has been written
previously (bit 1). i915 module can be removed and added multiple
times.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-04-07 0:18 [PATCH] drm/i915/guc: write wopcm related register once during uc init Daniele Ceraolo Spurio
2017-04-07 0:39 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-04-13 11:02 ` Joonas Lahtinen
2017-04-13 11:15 ` Joonas Lahtinen
2017-04-13 10:59 ` [PATCH] " Joonas Lahtinen
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