* [PATCH 0/2] Lattice MachXO2 Passive SPI FPGA Manager support @ 2017-04-23 15:20 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Hi all, this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI. Tested on my raspberry pi3 + bugblat's pif2 fpga hat. Paolo Pisati (2): dt: bindings: fpga: add lattice machxo2 slave spi binding description fpga: lattice machxo2: Add Lattice MachXO2 support .../bindings/fpga/lattice-machxo2-spi.txt | 29 +++ drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt create mode 100644 drivers/fpga/machxo2-spi.c -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] Lattice MachXO2 Passive SPI FPGA Manager support @ 2017-04-23 15:20 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree, linux-fpga, linux-kernel Hi all, this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI. Tested on my raspberry pi3 + bugblat's pif2 fpga hat. Paolo Pisati (2): dt: bindings: fpga: add lattice machxo2 slave spi binding description fpga: lattice machxo2: Add Lattice MachXO2 support .../bindings/fpga/lattice-machxo2-spi.txt | 29 +++ drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt create mode 100644 drivers/fpga/machxo2-spi.c -- 2.7.4 ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1492960845-342-1-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2017-04-23 15:20 ` Paolo Pisati @ 2017-04-23 15:20 ` Paolo Pisati -1 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..c3ef26bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <60000000>; + reg = <0>; + }; + }; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description @ 2017-04-23 15:20 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree, linux-fpga, linux-kernel Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..c3ef26bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <60000000>; + reg = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2017-04-23 15:20 ` Paolo Pisati (?) @ 2017-04-28 17:54 ` Rob Herring -1 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2017-04-28 17:54 UTC (permalink / raw) To: Paolo Pisati Cc: Mark Rutland, Alan Tull, Moritz Fischer, devicetree, linux-fpga, linux-kernel On Sun, Apr 23, 2017 at 05:20:44PM +0200, Paolo Pisati wrote: > Add dt binding documentation details for Lattice MachXO2 FPGA configuration > over Slave SPI interface. > > Signed-off-by: Paolo Pisati <p.pisati@gmail.com> > --- > .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support 2017-04-23 15:20 ` Paolo Pisati @ 2017-04-23 15:20 ` Paolo Pisati -1 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Add support for the Lattice MachXO2 FPGA chip in Slave SPI configuration. Signed-off-by: Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/fpga/machxo2-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index c81cb7d..cce135b 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI help FPGA manager driver support for Lattice iCE40 FPGAs over SPI. +config FPGA_MGR_MACHXO2_SPI + tristate "Lattice MachXO2 SPI" + depends on SPI + help + FPGA manager driver support for Lattice MachXO2 configuration + over slave SPI interface. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index c6f5d74..cdab1fe 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c new file mode 100644 index 0000000..5ee56bd --- /dev/null +++ b/drivers/fpga/machxo2-spi.c @@ -0,0 +1,199 @@ +/** + * Lattice MachXO2 Slave SPI Driver + * + * Copyright (C) 2017 Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Manage Lattice FPGA firmware that is loaded over SPI using + * the slave serial configuration interface. + */ + +#include <linux/delay.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/spi/spi.h> + + +/* MachXO2 Programming Guide - sysCONFIG Programming Commands */ + +#define ISC_ENABLE 0x000008c6 +#define ISC_ERASE 0x0000040e +#define ISC_PROGRAMDONE 0x0000005e +#define LSC_CHECKBUSY 0x000000f0 +#define LSC_INITADDRESS 0x00000046 +#define LSC_PROGINCRNV 0x01000070 +#define LSC_REFRESH 0x00000079 + +/* + * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data + * Sheet' sysCONFIG Port Timing Specifications (3-36) + */ +#define MACHXO2_MAX_SPEED 66000000 + +#define MACHXO2_LOW_DELAY 5 /* us */ +#define MACHXO2_HIGH_DELAY 200 /* us */ + +#define MACHXO2_OP_SIZE sizeof(uint32_t) +#define MACHXO2_PAGE_SIZE 16 +#define MACHXO2_BUF_SIZE (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE) + + +static int waituntilnotbusy(struct spi_device *spi) +{ + uint8_t rx, busyflag = 0x80; + uint32_t checkbusy = LSC_CHECKBUSY; + + do { + if (spi_write_then_read(spi, &checkbusy, MACHXO2_OP_SIZE, + &rx, sizeof(rx))) + return -EIO; + } while (rx & busyflag); + return 0; +} + +static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static int machxo2_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct spi_device *spi = mgr->priv; + uint32_t enable = ISC_ENABLE; + uint32_t erase = ISC_ERASE; + uint32_t initaddr = LSC_INITADDRESS; + + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + dev_err(&mgr->dev, + "Partial reconfiguration is not supported\n"); + return -ENOTSUPP; + } + + if (spi_write(spi, &enable, MACHXO2_OP_SIZE)) + goto fail; + udelay(MACHXO2_LOW_DELAY); + if (spi_write(spi, &erase, MACHXO2_OP_SIZE)) + goto fail; + waituntilnotbusy(spi); + if (spi_write(spi, &initaddr, MACHXO2_OP_SIZE)) + goto fail; + return 0; + +fail: + dev_err(&mgr->dev, "Error during FPGA init.\n"); + return -EIO; +} + +static int machxo2_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct spi_device *spi = mgr->priv; + uint32_t progincr = LSC_PROGINCRNV; + uint8_t payload[MACHXO2_BUF_SIZE]; + int i; + + if (count % MACHXO2_PAGE_SIZE != 0) { + dev_err(&mgr->dev, "Malformed payload.\n"); + return -EINVAL; + } + + memcpy(payload, &progincr, MACHXO2_OP_SIZE); + for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) { + memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE); + if (spi_write(spi, payload, MACHXO2_BUF_SIZE)) { + dev_err(&mgr->dev, "Error loading the bitstream.\n"); + return -EIO; + } + udelay(MACHXO2_HIGH_DELAY); + } + + return 0; +} + +static int machxo2_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct spi_device *spi = mgr->priv; + uint32_t progdone = ISC_PROGRAMDONE; + uint32_t refresh = LSC_REFRESH; + + if (spi_write(spi, &progdone, MACHXO2_OP_SIZE)) + goto fail; + /* yep, LSC_REFRESH is 3 bytes long actually */ + if (spi_write(spi, &refresh, MACHXO2_OP_SIZE-1)) + goto fail; + return 0; + +fail: + dev_err(&mgr->dev, "Refresh failed.\n"); + return -EIO; +} + +static const struct fpga_manager_ops machxo2_ops = { + .state = machxo2_spi_state, + .write_init = machxo2_write_init, + .write = machxo2_write, + .write_complete = machxo2_write_complete, +}; + +static int machxo2_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + int ret = 0; + + if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { + dev_err(dev, "Speed is too high\n"); + return -EINVAL; + } + + ret = fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", + &machxo2_ops, spi); + if (ret) + dev_err(dev, "Unable to register FPGA manager"); + + return ret; +} + +static int machxo2_spi_remove(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + + fpga_mgr_unregister(dev); + return 0; +} + +static const struct of_device_id of_match[] = { + { .compatible = "lattice,machxo2-slave-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_match); + +static const struct spi_device_id lattice_ids[] = { + { "machxo2-slave-spi", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(spi, lattice_ids); + +static struct spi_driver machxo2_spi_driver = { + .driver = { + .name = "machxo2-slave-spi", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(of_match), + }, + .probe = machxo2_spi_probe, + .remove = machxo2_spi_remove, + .id_table = lattice_ids, +}; + +module_spi_driver(machxo2_spi_driver) + +MODULE_AUTHOR("Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>"); +MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI"); +MODULE_LICENSE("GPL v2"); -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support @ 2017-04-23 15:20 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-04-23 15:20 UTC (permalink / raw) To: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer Cc: devicetree, linux-fpga, linux-kernel Add support for the Lattice MachXO2 FPGA chip in Slave SPI configuration. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/fpga/machxo2-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index c81cb7d..cce135b 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI help FPGA manager driver support for Lattice iCE40 FPGAs over SPI. +config FPGA_MGR_MACHXO2_SPI + tristate "Lattice MachXO2 SPI" + depends on SPI + help + FPGA manager driver support for Lattice MachXO2 configuration + over slave SPI interface. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index c6f5d74..cdab1fe 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c new file mode 100644 index 0000000..5ee56bd --- /dev/null +++ b/drivers/fpga/machxo2-spi.c @@ -0,0 +1,199 @@ +/** + * Lattice MachXO2 Slave SPI Driver + * + * Copyright (C) 2017 Paolo Pisati <p.pisati@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Manage Lattice FPGA firmware that is loaded over SPI using + * the slave serial configuration interface. + */ + +#include <linux/delay.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/spi/spi.h> + + +/* MachXO2 Programming Guide - sysCONFIG Programming Commands */ + +#define ISC_ENABLE 0x000008c6 +#define ISC_ERASE 0x0000040e +#define ISC_PROGRAMDONE 0x0000005e +#define LSC_CHECKBUSY 0x000000f0 +#define LSC_INITADDRESS 0x00000046 +#define LSC_PROGINCRNV 0x01000070 +#define LSC_REFRESH 0x00000079 + +/* + * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data + * Sheet' sysCONFIG Port Timing Specifications (3-36) + */ +#define MACHXO2_MAX_SPEED 66000000 + +#define MACHXO2_LOW_DELAY 5 /* us */ +#define MACHXO2_HIGH_DELAY 200 /* us */ + +#define MACHXO2_OP_SIZE sizeof(uint32_t) +#define MACHXO2_PAGE_SIZE 16 +#define MACHXO2_BUF_SIZE (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE) + + +static int waituntilnotbusy(struct spi_device *spi) +{ + uint8_t rx, busyflag = 0x80; + uint32_t checkbusy = LSC_CHECKBUSY; + + do { + if (spi_write_then_read(spi, &checkbusy, MACHXO2_OP_SIZE, + &rx, sizeof(rx))) + return -EIO; + } while (rx & busyflag); + return 0; +} + +static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static int machxo2_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct spi_device *spi = mgr->priv; + uint32_t enable = ISC_ENABLE; + uint32_t erase = ISC_ERASE; + uint32_t initaddr = LSC_INITADDRESS; + + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + dev_err(&mgr->dev, + "Partial reconfiguration is not supported\n"); + return -ENOTSUPP; + } + + if (spi_write(spi, &enable, MACHXO2_OP_SIZE)) + goto fail; + udelay(MACHXO2_LOW_DELAY); + if (spi_write(spi, &erase, MACHXO2_OP_SIZE)) + goto fail; + waituntilnotbusy(spi); + if (spi_write(spi, &initaddr, MACHXO2_OP_SIZE)) + goto fail; + return 0; + +fail: + dev_err(&mgr->dev, "Error during FPGA init.\n"); + return -EIO; +} + +static int machxo2_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct spi_device *spi = mgr->priv; + uint32_t progincr = LSC_PROGINCRNV; + uint8_t payload[MACHXO2_BUF_SIZE]; + int i; + + if (count % MACHXO2_PAGE_SIZE != 0) { + dev_err(&mgr->dev, "Malformed payload.\n"); + return -EINVAL; + } + + memcpy(payload, &progincr, MACHXO2_OP_SIZE); + for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) { + memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE); + if (spi_write(spi, payload, MACHXO2_BUF_SIZE)) { + dev_err(&mgr->dev, "Error loading the bitstream.\n"); + return -EIO; + } + udelay(MACHXO2_HIGH_DELAY); + } + + return 0; +} + +static int machxo2_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct spi_device *spi = mgr->priv; + uint32_t progdone = ISC_PROGRAMDONE; + uint32_t refresh = LSC_REFRESH; + + if (spi_write(spi, &progdone, MACHXO2_OP_SIZE)) + goto fail; + /* yep, LSC_REFRESH is 3 bytes long actually */ + if (spi_write(spi, &refresh, MACHXO2_OP_SIZE-1)) + goto fail; + return 0; + +fail: + dev_err(&mgr->dev, "Refresh failed.\n"); + return -EIO; +} + +static const struct fpga_manager_ops machxo2_ops = { + .state = machxo2_spi_state, + .write_init = machxo2_write_init, + .write = machxo2_write, + .write_complete = machxo2_write_complete, +}; + +static int machxo2_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + int ret = 0; + + if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { + dev_err(dev, "Speed is too high\n"); + return -EINVAL; + } + + ret = fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", + &machxo2_ops, spi); + if (ret) + dev_err(dev, "Unable to register FPGA manager"); + + return ret; +} + +static int machxo2_spi_remove(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + + fpga_mgr_unregister(dev); + return 0; +} + +static const struct of_device_id of_match[] = { + { .compatible = "lattice,machxo2-slave-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_match); + +static const struct spi_device_id lattice_ids[] = { + { "machxo2-slave-spi", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(spi, lattice_ids); + +static struct spi_driver machxo2_spi_driver = { + .driver = { + .name = "machxo2-slave-spi", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(of_match), + }, + .probe = machxo2_spi_probe, + .remove = machxo2_spi_remove, + .id_table = lattice_ids, +}; + +module_spi_driver(machxo2_spi_driver) + +MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>"); +MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI"); +MODULE_LICENSE("GPL v2"); -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <1492960845-342-3-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support 2017-04-23 15:20 ` Paolo Pisati @ 2017-04-25 15:59 ` Alan Tull -1 siblings, 0 replies; 16+ messages in thread From: Alan Tull @ 2017-04-25 15:59 UTC (permalink / raw) To: Paolo Pisati Cc: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel On Sun, Apr 23, 2017 at 10:20 AM, Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: Hi Paolo, Thanks for submitting your driver. A few things... > Add support for the Lattice MachXO2 FPGA chip in Slave SPI configuration. > Please add a bit of a description here. Format should be subject line, skip a line, description, skip a line, then your signoff. > Signed-off-by: Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 207 insertions(+) > create mode 100644 drivers/fpga/machxo2-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index c81cb7d..cce135b 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI > help > FPGA manager driver support for Lattice iCE40 FPGAs over SPI. > > +config FPGA_MGR_MACHXO2_SPI > + tristate "Lattice MachXO2 SPI" > + depends on SPI > + help > + FPGA manager driver support for Lattice MachXO2 configuration > + over slave SPI interface. > + > config FPGA_MGR_SOCFPGA > tristate "Altera SOCFPGA FPGA Manager" > depends on ARCH_SOCFPGA || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index c6f5d74..cdab1fe 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o > > # FPGA Manager Drivers > obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c > new file mode 100644 > index 0000000..5ee56bd > --- /dev/null > +++ b/drivers/fpga/machxo2-spi.c > @@ -0,0 +1,199 @@ > +/** > + * Lattice MachXO2 Slave SPI Driver > + * > + * Copyright (C) 2017 Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Lattice FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > + > + Please run checkpatch and fix whatever it points out, such as not to use double blank lines. > +/* MachXO2 Programming Guide - sysCONFIG Programming Commands */ > + > +#define ISC_ENABLE 0x000008c6 > +#define ISC_ERASE 0x0000040e > +#define ISC_PROGRAMDONE 0x0000005e > +#define LSC_CHECKBUSY 0x000000f0 > +#define LSC_INITADDRESS 0x00000046 > +#define LSC_PROGINCRNV 0x01000070 > +#define LSC_REFRESH 0x00000079 > + > +/* > + * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data > + * Sheet' sysCONFIG Port Timing Specifications (3-36) > + */ > +#define MACHXO2_MAX_SPEED 66000000 > + > +#define MACHXO2_LOW_DELAY 5 /* us */ > +#define MACHXO2_HIGH_DELAY 200 /* us */ > + > +#define MACHXO2_OP_SIZE sizeof(uint32_t) > +#define MACHXO2_PAGE_SIZE 16 > +#define MACHXO2_BUF_SIZE (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE) > + > + > +static int waituntilnotbusy(struct spi_device *spi) Could you rename to something like wait_until_not_busy? > +{ > + uint8_t rx, busyflag = 0x80; Please create a macro for the 0x80 value and use it here. > + uint32_t checkbusy = LSC_CHECKBUSY; Another checkpatch: u32 is preferred over uint32_t. > + > + do { > + if (spi_write_then_read(spi, &checkbusy, MACHXO2_OP_SIZE, > + &rx, sizeof(rx))) > + return -EIO; Please pass down the spi_write_then_read error code like: ret = spi_write_then_read(...); if (ret) return ret; There's a few places below where I will point that out for spi_write as well. > + } while (rx & busyflag); Skip a line before the return. > + return 0; > +} > + > +static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) > +{ > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int machxo2_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t enable = ISC_ENABLE; > + uint32_t erase = ISC_ERASE; > + uint32_t initaddr = LSC_INITADDRESS; > + > + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { > + dev_err(&mgr->dev, > + "Partial reconfiguration is not supported\n"); > + return -ENOTSUPP; > + } > + > + if (spi_write(spi, &enable, MACHXO2_OP_SIZE)) > + goto fail; Please skip a line here. > + udelay(MACHXO2_LOW_DELAY); > + if (spi_write(spi, &erase, MACHXO2_OP_SIZE)) > + goto fail; Again, it's better to pass the spi_write error code. ret = spi_write(...) if (ret) goto fail; Then skip a line. > + waituntilnotbusy(spi); > + if (spi_write(spi, &initaddr, MACHXO2_OP_SIZE)) > + goto fail; Pass through the error code, same as above. > + return 0; > + > +fail: > + dev_err(&mgr->dev, "Error during FPGA init.\n"); > + return -EIO; return ret; > +} > + > +static int machxo2_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t progincr = LSC_PROGINCRNV; > + uint8_t payload[MACHXO2_BUF_SIZE]; > + int i; > + > + if (count % MACHXO2_PAGE_SIZE != 0) { > + dev_err(&mgr->dev, "Malformed payload.\n"); > + return -EINVAL; > + } > + > + memcpy(payload, &progincr, MACHXO2_OP_SIZE); > + for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) { > + memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE); > + if (spi_write(spi, payload, MACHXO2_BUF_SIZE)) { > + dev_err(&mgr->dev, "Error loading the bitstream.\n"); > + return -EIO; Pass through spi_write error code. > + } > + udelay(MACHXO2_HIGH_DELAY); > + } > + > + return 0; > +} > + > +static int machxo2_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t progdone = ISC_PROGRAMDONE; > + uint32_t refresh = LSC_REFRESH; > + > + if (spi_write(spi, &progdone, MACHXO2_OP_SIZE)) > + goto fail; Pass spi_write error code if error. And skip a line. > + /* yep, LSC_REFRESH is 3 bytes long actually */ > + if (spi_write(spi, &refresh, MACHXO2_OP_SIZE-1)) > + goto fail; Here too. Also add spaces around the minus sign. > + return 0; > + > +fail: > + dev_err(&mgr->dev, "Refresh failed.\n"); > + return -EIO; Will be return ret; > +} > + > +static const struct fpga_manager_ops machxo2_ops = { > + .state = machxo2_spi_state, > + .write_init = machxo2_write_init, > + .write = machxo2_write, > + .write_complete = machxo2_write_complete, > +}; > + > +static int machxo2_spi_probe(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + int ret = 0; > + > + if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { > + dev_err(dev, "Speed is too high\n"); > + return -EINVAL; > + } > + > + ret = fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", > + &machxo2_ops, spi); > + if (ret) > + dev_err(dev, "Unable to register FPGA manager"); You can just 'return fpga_mgr_register(...);' here. > + > + return ret; > +} > + > +static int machxo2_spi_remove(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + > + fpga_mgr_unregister(dev); Skip a line. > + return 0; > +} > + > +static const struct of_device_id of_match[] = { > + { .compatible = "lattice,machxo2-slave-spi", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, of_match); > + > +static const struct spi_device_id lattice_ids[] = { > + { "machxo2-slave-spi", 0 }, > + { }, > +}; > +MODULE_DEVICE_TABLE(spi, lattice_ids); > + > +static struct spi_driver machxo2_spi_driver = { > + .driver = { > + .name = "machxo2-slave-spi", > + .owner = THIS_MODULE, You don't need to specify THIS_MODULE here. spi_register_driver will add that for you. > + .of_match_table = of_match_ptr(of_match), > + }, > + .probe = machxo2_spi_probe, > + .remove = machxo2_spi_remove, > + .id_table = lattice_ids, > +}; > + > +module_spi_driver(machxo2_spi_driver) > + > +MODULE_AUTHOR("Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>"); > +MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI"); > +MODULE_LICENSE("GPL v2"); > -- > 2.7.4 > Thanks, Alan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support @ 2017-04-25 15:59 ` Alan Tull 0 siblings, 0 replies; 16+ messages in thread From: Alan Tull @ 2017-04-25 15:59 UTC (permalink / raw) To: Paolo Pisati Cc: Rob Herring, Mark Rutland, Alan Tull, Moritz Fischer, devicetree@vger.kernel.org, linux-fpga, linux-kernel On Sun, Apr 23, 2017 at 10:20 AM, Paolo Pisati <p.pisati@gmail.com> wrote: Hi Paolo, Thanks for submitting your driver. A few things... > Add support for the Lattice MachXO2 FPGA chip in Slave SPI configuration. > Please add a bit of a description here. Format should be subject line, skip a line, description, skip a line, then your signoff. > Signed-off-by: Paolo Pisati <p.pisati@gmail.com> > --- > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/machxo2-spi.c | 199 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 207 insertions(+) > create mode 100644 drivers/fpga/machxo2-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index c81cb7d..cce135b 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI > help > FPGA manager driver support for Lattice iCE40 FPGAs over SPI. > > +config FPGA_MGR_MACHXO2_SPI > + tristate "Lattice MachXO2 SPI" > + depends on SPI > + help > + FPGA manager driver support for Lattice MachXO2 configuration > + over slave SPI interface. > + > config FPGA_MGR_SOCFPGA > tristate "Altera SOCFPGA FPGA Manager" > depends on ARCH_SOCFPGA || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index c6f5d74..cdab1fe 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o > > # FPGA Manager Drivers > obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c > new file mode 100644 > index 0000000..5ee56bd > --- /dev/null > +++ b/drivers/fpga/machxo2-spi.c > @@ -0,0 +1,199 @@ > +/** > + * Lattice MachXO2 Slave SPI Driver > + * > + * Copyright (C) 2017 Paolo Pisati <p.pisati@gmail.com> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Lattice FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > + > + Please run checkpatch and fix whatever it points out, such as not to use double blank lines. > +/* MachXO2 Programming Guide - sysCONFIG Programming Commands */ > + > +#define ISC_ENABLE 0x000008c6 > +#define ISC_ERASE 0x0000040e > +#define ISC_PROGRAMDONE 0x0000005e > +#define LSC_CHECKBUSY 0x000000f0 > +#define LSC_INITADDRESS 0x00000046 > +#define LSC_PROGINCRNV 0x01000070 > +#define LSC_REFRESH 0x00000079 > + > +/* > + * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data > + * Sheet' sysCONFIG Port Timing Specifications (3-36) > + */ > +#define MACHXO2_MAX_SPEED 66000000 > + > +#define MACHXO2_LOW_DELAY 5 /* us */ > +#define MACHXO2_HIGH_DELAY 200 /* us */ > + > +#define MACHXO2_OP_SIZE sizeof(uint32_t) > +#define MACHXO2_PAGE_SIZE 16 > +#define MACHXO2_BUF_SIZE (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE) > + > + > +static int waituntilnotbusy(struct spi_device *spi) Could you rename to something like wait_until_not_busy? > +{ > + uint8_t rx, busyflag = 0x80; Please create a macro for the 0x80 value and use it here. > + uint32_t checkbusy = LSC_CHECKBUSY; Another checkpatch: u32 is preferred over uint32_t. > + > + do { > + if (spi_write_then_read(spi, &checkbusy, MACHXO2_OP_SIZE, > + &rx, sizeof(rx))) > + return -EIO; Please pass down the spi_write_then_read error code like: ret = spi_write_then_read(...); if (ret) return ret; There's a few places below where I will point that out for spi_write as well. > + } while (rx & busyflag); Skip a line before the return. > + return 0; > +} > + > +static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) > +{ > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int machxo2_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t enable = ISC_ENABLE; > + uint32_t erase = ISC_ERASE; > + uint32_t initaddr = LSC_INITADDRESS; > + > + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { > + dev_err(&mgr->dev, > + "Partial reconfiguration is not supported\n"); > + return -ENOTSUPP; > + } > + > + if (spi_write(spi, &enable, MACHXO2_OP_SIZE)) > + goto fail; Please skip a line here. > + udelay(MACHXO2_LOW_DELAY); > + if (spi_write(spi, &erase, MACHXO2_OP_SIZE)) > + goto fail; Again, it's better to pass the spi_write error code. ret = spi_write(...) if (ret) goto fail; Then skip a line. > + waituntilnotbusy(spi); > + if (spi_write(spi, &initaddr, MACHXO2_OP_SIZE)) > + goto fail; Pass through the error code, same as above. > + return 0; > + > +fail: > + dev_err(&mgr->dev, "Error during FPGA init.\n"); > + return -EIO; return ret; > +} > + > +static int machxo2_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t progincr = LSC_PROGINCRNV; > + uint8_t payload[MACHXO2_BUF_SIZE]; > + int i; > + > + if (count % MACHXO2_PAGE_SIZE != 0) { > + dev_err(&mgr->dev, "Malformed payload.\n"); > + return -EINVAL; > + } > + > + memcpy(payload, &progincr, MACHXO2_OP_SIZE); > + for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) { > + memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE); > + if (spi_write(spi, payload, MACHXO2_BUF_SIZE)) { > + dev_err(&mgr->dev, "Error loading the bitstream.\n"); > + return -EIO; Pass through spi_write error code. > + } > + udelay(MACHXO2_HIGH_DELAY); > + } > + > + return 0; > +} > + > +static int machxo2_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct spi_device *spi = mgr->priv; > + uint32_t progdone = ISC_PROGRAMDONE; > + uint32_t refresh = LSC_REFRESH; > + > + if (spi_write(spi, &progdone, MACHXO2_OP_SIZE)) > + goto fail; Pass spi_write error code if error. And skip a line. > + /* yep, LSC_REFRESH is 3 bytes long actually */ > + if (spi_write(spi, &refresh, MACHXO2_OP_SIZE-1)) > + goto fail; Here too. Also add spaces around the minus sign. > + return 0; > + > +fail: > + dev_err(&mgr->dev, "Refresh failed.\n"); > + return -EIO; Will be return ret; > +} > + > +static const struct fpga_manager_ops machxo2_ops = { > + .state = machxo2_spi_state, > + .write_init = machxo2_write_init, > + .write = machxo2_write, > + .write_complete = machxo2_write_complete, > +}; > + > +static int machxo2_spi_probe(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + int ret = 0; > + > + if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { > + dev_err(dev, "Speed is too high\n"); > + return -EINVAL; > + } > + > + ret = fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", > + &machxo2_ops, spi); > + if (ret) > + dev_err(dev, "Unable to register FPGA manager"); You can just 'return fpga_mgr_register(...);' here. > + > + return ret; > +} > + > +static int machxo2_spi_remove(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + > + fpga_mgr_unregister(dev); Skip a line. > + return 0; > +} > + > +static const struct of_device_id of_match[] = { > + { .compatible = "lattice,machxo2-slave-spi", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, of_match); > + > +static const struct spi_device_id lattice_ids[] = { > + { "machxo2-slave-spi", 0 }, > + { }, > +}; > +MODULE_DEVICE_TABLE(spi, lattice_ids); > + > +static struct spi_driver machxo2_spi_driver = { > + .driver = { > + .name = "machxo2-slave-spi", > + .owner = THIS_MODULE, You don't need to specify THIS_MODULE here. spi_register_driver will add that for you. > + .of_match_table = of_match_ptr(of_match), > + }, > + .probe = machxo2_spi_probe, > + .remove = machxo2_spi_remove, > + .id_table = lattice_ids, > +}; > + > +module_spi_driver(machxo2_spi_driver) > + > +MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>"); > +MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI"); > +MODULE_LICENSE("GPL v2"); > -- > 2.7.4 > Thanks, Alan ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 0/2] Lattice MachXO2 Slave SPI FPGA Manager support
@ 2017-07-06 10:01 Paolo Pisati
[not found] ` <1499335270-6512-1-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Paolo Pisati @ 2017-07-06 10:01 UTC (permalink / raw)
To: Alan Tull, Moritz Fischer
Cc: Rob Herring, Mark Rutland, linux-fpga, devicetree, linux-kernel
Hi all,
this series adds support for the Lattice MachXO2 FPGA chip, programmed
over Slave SPI.
Tested on my raspberry pi3 + bugblat's pif2 fpga hat.
Changes from v1:
* fixed all the warnings pointed out by 'checkpatch --strict' and
Alan Tull
Changes from v2:
* convert to BIT() macro and spi_message_init() / trans.delay_usecs
Changes from v3;
* loop unroll machxo2_write() and collate writes in a single spi_sync()
Changes from v4:
* rebased on 3.12
Paolo Pisati (2):
dt: bindings: fpga: add lattice machxo2 slave spi binding description
fpga: lattice machxo2: Add Lattice MachXO2 support
.../bindings/fpga/lattice-machxo2-spi.txt | 29 ++
drivers/fpga/Kconfig | 7 +
drivers/fpga/Makefile | 1 +
drivers/fpga/machxo2-spi.c | 298 +++++++++++++++++++++
4 files changed, 335 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
create mode 100644 drivers/fpga/machxo2-spi.c
--
2.7.4
^ permalink raw reply [flat|nested] 16+ messages in thread[parent not found: <1499335270-6512-1-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2017-07-06 10:01 [PATCH v5 0/2] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati @ 2017-07-06 10:01 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-07-06 10:01 UTC (permalink / raw) To: Alan Tull, Moritz Fischer Cc: Rob Herring, Mark Rutland, linux-fpga-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..c3ef26bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <60000000>; + reg = <0>; + }; + }; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description @ 2017-07-06 10:01 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2017-07-06 10:01 UTC (permalink / raw) To: Alan Tull, Moritz Fischer Cc: Rob Herring, Mark Rutland, linux-fpga, devicetree, linux-kernel Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..c3ef26bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <60000000>; + reg = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2 v6] Lattice MachXO2 Slave SPI FPGA Manager support @ 2018-03-16 15:54 Paolo Pisati 2018-03-16 15:54 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati 0 siblings, 1 reply; 16+ messages in thread From: Paolo Pisati @ 2018-03-16 15:54 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Hi all, this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI. Tested on a raspberry pi3, beaglebone black (little endian mode) and imx6 hummingboard (big endian mode) + bugblat's pif2 fpga hat (machxo2 7000HC) or tinyfpga A1/A2 (machxo2 256HC / 1200HC), in SPI slave mode with varying bus speed. Changes since v5: * fixed all the endianess issues * introduced a cleanup() path invoked in case of flash failure * moved back machxo2_write() to use a spi_sync() transaction per line write (in v5 i queued all the spi_write()s and executed a single spi_sync() at the end, but that, sometimes, resulted in the REFRESH command to fail with a CMD_ERR, depending on the SPI bus speed) Paolo Pisati (2): dt: bindings: fpga: add lattice machxo2 slave spi binding description fpga: lattice machxo2: Add Lattice MachXO2 support .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++ drivers/fpga/Kconfig | 8 + drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 410 +++++++++++++++++++++ 4 files changed, 448 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt create mode 100644 drivers/fpga/machxo2-spi.c -- 2.7.4 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2018-03-16 15:54 [PATCH 0/2 v6] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati @ 2018-03-16 15:54 ` Paolo Pisati 2018-03-16 16:31 ` Moritz Fischer 0 siblings, 1 reply; 16+ messages in thread From: Paolo Pisati @ 2018-03-16 15:54 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..a8c362e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2018-03-16 15:54 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati @ 2018-03-16 16:31 ` Moritz Fischer 2018-03-19 15:42 ` Alan Tull 0 siblings, 1 reply; 16+ messages in thread From: Moritz Fischer @ 2018-03-16 16:31 UTC (permalink / raw) To: Paolo Pisati Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland, linux-fpga, devicetree, linux-kernel On Fri, Mar 16, 2018 at 04:54:28PM +0100, Paolo Pisati wrote: > Add dt binding documentation details for Lattice MachXO2 FPGA configuration > over Slave SPI interface. > > Signed-off-by: Paolo Pisati <p.pisati@gmail.com> > Acked-by: Rob Herring <robh@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> > --- > .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt > > diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt > new file mode 100644 > index 0000000..a8c362e > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt > @@ -0,0 +1,29 @@ > +Lattice MachXO2 Slave SPI FPGA Manager > + > +Lattice MachXO2 FPGAs support a method of loading the bitstream over > +'slave SPI' interface. Nit: a 'slave SPI' > + > +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com > + > +Required properties: > +- compatible: should contain "lattice,machxo2-slave-spi" > +- reg: spi chip select of the FPGA > + > +Example for full FPGA configuration: > + > + fpga-region0 { > + compatible = "fpga-region"; > + fpga-mgr = <&fpga_mgr_spi>; > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + }; > + > + spi1: spi@2000 { > + ... > + > + fpga_mgr_spi: fpga-mgr@0 { > + compatible = "lattice,machxo2-slave-spi"; > + spi-max-frequency = <8000000>; > + reg = <0>; > + }; > + }; > -- > 2.7.4 > Thanks, Moritz ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2018-03-16 16:31 ` Moritz Fischer @ 2018-03-19 15:42 ` Alan Tull 0 siblings, 0 replies; 16+ messages in thread From: Alan Tull @ 2018-03-19 15:42 UTC (permalink / raw) To: Moritz Fischer Cc: Paolo Pisati, Rob Herring, Mark Rutland, linux-fpga, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel On Fri, Mar 16, 2018 at 11:31 AM, Moritz Fischer <mdf@kernel.org> wrote: > On Fri, Mar 16, 2018 at 04:54:28PM +0100, Paolo Pisati wrote: >> Add dt binding documentation details for Lattice MachXO2 FPGA configuration >> over Slave SPI interface. >> >> Signed-off-by: Paolo Pisati <p.pisati@gmail.com> >> Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Thanks, Alan >> --- >> .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt >> >> diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt >> new file mode 100644 >> index 0000000..a8c362e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt >> @@ -0,0 +1,29 @@ >> +Lattice MachXO2 Slave SPI FPGA Manager >> + >> +Lattice MachXO2 FPGAs support a method of loading the bitstream over >> +'slave SPI' interface. > Nit: a 'slave SPI' >> + >> +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com >> + >> +Required properties: >> +- compatible: should contain "lattice,machxo2-slave-spi" >> +- reg: spi chip select of the FPGA >> + >> +Example for full FPGA configuration: >> + >> + fpga-region0 { >> + compatible = "fpga-region"; >> + fpga-mgr = <&fpga_mgr_spi>; >> + #address-cells = <0x1>; >> + #size-cells = <0x1>; >> + }; >> + >> + spi1: spi@2000 { >> + ... >> + >> + fpga_mgr_spi: fpga-mgr@0 { >> + compatible = "lattice,machxo2-slave-spi"; >> + spi-max-frequency = <8000000>; >> + reg = <0>; >> + }; >> + }; >> -- >> 2.7.4 >> > > Thanks, > > Moritz ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2 v7] Lattice MachXO2 Slave SPI FPGA Manager support @ 2018-03-21 17:35 Paolo Pisati 2018-03-21 17:35 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati 0 siblings, 1 reply; 16+ messages in thread From: Paolo Pisati @ 2018-03-21 17:35 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Hi all, this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI. Tested on a raspberry pi3, beaglebone black (little endian mode) and imx6 hummingboard (big endian mode) + bugblat's pif2 fpga hat (machxo2 7000HC) or tinyfpga A1/A2 (machxo2 256HC / 1200HC), in SPI slave mode with varying bus speed. Changes since v6: * added the SPDX boilerplate * switched to pr_debug() and renamed MACHXO2_DEBUG to DEBUG Paolo Pisati (2): dt: bindings: fpga: add lattice machxo2 slave spi binding description fpga: lattice machxo2: Add Lattice MachXO2 support .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++ drivers/fpga/Kconfig | 8 + drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 405 +++++++++++++++++++++ 4 files changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt create mode 100644 drivers/fpga/machxo2-spi.c -- 2.7.4 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2018-03-21 17:35 [PATCH 0/2 v7] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati @ 2018-03-21 17:35 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2018-03-21 17:35 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..a8c362e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +a 'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2 v8] Lattice MachXO2 Slave SPI FPGA Manager support @ 2018-03-23 12:27 Paolo Pisati 2018-03-23 12:27 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati 0 siblings, 1 reply; 16+ messages in thread From: Paolo Pisati @ 2018-03-23 12:27 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Hi all, this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI. Tested on a raspberry pi3, beaglebone black (little endian mode) and imx6 hummingboard (big endian mode) + bugblat's pif2 fpga hat (machxo2 7000HC) or tinyfpga A1/A2 (machxo2 256HC / 1200HC), in SPI slave mode with varying bus speed. Changes since v7: * misc style fixes, among which: * static const u8 cmd[] * #ifdef DEBUG ... #endif reorder * introduction of get_err_string() * direct returns to reduce line count * indentation Paolo Pisati (2): dt: bindings: fpga: add lattice machxo2 slave spi binding description fpga: lattice machxo2: Add Lattice MachXO2 support .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++ drivers/fpga/Kconfig | 8 + drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 388 +++++++++++++++++++++ 4 files changed, 426 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt create mode 100644 drivers/fpga/machxo2-spi.c -- 2.7.4 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description 2018-03-23 12:27 [PATCH 0/2 v8] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati @ 2018-03-23 12:27 ` Paolo Pisati 0 siblings, 0 replies; 16+ messages in thread From: Paolo Pisati @ 2018-03-23 12:27 UTC (permalink / raw) To: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Cc: linux-fpga, devicetree, linux-kernel Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati <p.pisati@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 0000000..a8c362e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +a 'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
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2017-04-23 15:20 [PATCH 0/2] Lattice MachXO2 Passive SPI FPGA Manager support Paolo Pisati
2017-04-23 15:20 ` Paolo Pisati
[not found] ` <1492960845-342-1-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-23 15:20 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati
2017-04-23 15:20 ` Paolo Pisati
2017-04-28 17:54 ` Rob Herring
2017-04-23 15:20 ` [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support Paolo Pisati
2017-04-23 15:20 ` Paolo Pisati
[not found] ` <1492960845-342-3-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-25 15:59 ` Alan Tull
2017-04-25 15:59 ` Alan Tull
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2017-07-06 10:01 [PATCH v5 0/2] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati
[not found] ` <1499335270-6512-1-git-send-email-p.pisati-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-06 10:01 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati
2017-07-06 10:01 ` Paolo Pisati
2018-03-16 15:54 [PATCH 0/2 v6] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati
2018-03-16 15:54 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati
2018-03-16 16:31 ` Moritz Fischer
2018-03-19 15:42 ` Alan Tull
2018-03-21 17:35 [PATCH 0/2 v7] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati
2018-03-21 17:35 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati
2018-03-23 12:27 [PATCH 0/2 v8] Lattice MachXO2 Slave SPI FPGA Manager support Paolo Pisati
2018-03-23 12:27 ` [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description Paolo Pisati
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