* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 11:09 ` Marek Vasut
2017-05-05 10:26 ` [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method tien.fong.chee at intel.com
` (5 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Remove unused passing parameter of socfpga_bridges_reset function in
SoCFPGA Arria10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
.../include/mach/reset_manager_arria10.h | 2 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 7922db8..b6d7f4f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index d8c858c..66f1ec2 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
/* For SoCFPGA-VT, this is NOP. */
return 0;
}
#else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
int ret;
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-05 10:26 ` [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
@ 2017-05-05 11:09 ` Marek Vasut
2017-05-08 4:17 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-05 11:09 UTC (permalink / raw)
To: u-boot
On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Remove unused passing parameter of socfpga_bridges_reset function in
> SoCFPGA Arria10.
So how do you un-reset the bridges if you drop this $enable argument ?
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> .../include/mach/reset_manager_arria10.h | 2 +-
> arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> index 7922db8..b6d7f4f 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
> void socfpga_reset_assert_fpga_connected_peripherals(void);
> void socfpga_reset_deassert_osc1wd0(void);
> void socfpga_reset_uart(int assert);
> -int socfpga_bridges_reset(int enable);
> +int socfpga_bridges_reset(void);
>
> struct socfpga_reset_manager {
> u32 stat;
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> index d8c858c..66f1ec2 100644
> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
> }
>
> #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> -int socfpga_bridges_reset(int enable)
> +int socfpga_bridges_reset(void)
> {
> /* For SoCFPGA-VT, this is NOP. */
> return 0;
> }
> #else
> -int socfpga_bridges_reset(int enable)
> +int socfpga_bridges_reset(void)
> {
> int ret;
>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-05 11:09 ` Marek Vasut
@ 2017-05-08 4:17 ` Chee, Tien Fong
2017-05-08 9:52 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-08 4:17 UTC (permalink / raw)
To: u-boot
On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Remove unused passing parameter of socfpga_bridges_reset function
> > in
> > SoCFPGA Arria10.
> So how do you un-reset the bridges if you drop this $enable argument
> ?
>
This socfpga_reset_deassert_bridges_handoff() would be called, bridges
are released based on DTS.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > .../include/mach/reset_manager_arria10.h | 2 +-
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> > index 7922db8..b6d7f4f 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
> > void socfpga_reset_assert_fpga_connected_peripherals(void);
> > void socfpga_reset_deassert_osc1wd0(void);
> > void socfpga_reset_uart(int assert);
> > -int socfpga_bridges_reset(int enable);
> > +int socfpga_bridges_reset(void);
> >
> > struct socfpga_reset_manager {
> > u32 stat;
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index d8c858c..66f1ec2 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
> > }
> >
> > #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> > -int socfpga_bridges_reset(int enable)
> > +int socfpga_bridges_reset(void)
> > {
> > /* For SoCFPGA-VT, this is NOP. */
> > return 0;
> > }
> > #else
> > -int socfpga_bridges_reset(int enable)
> > +int socfpga_bridges_reset(void)
> > {
> > int ret;
> >
> >
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-08 4:17 ` Chee, Tien Fong
@ 2017-05-08 9:52 ` Marek Vasut
2017-05-09 4:23 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-08 9:52 UTC (permalink / raw)
To: u-boot
On 05/08/2017 06:17 AM, Chee, Tien Fong wrote:
> On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Remove unused passing parameter of socfpga_bridges_reset function
>>> in
>>> SoCFPGA Arria10.
>> So how do you un-reset the bridges if you drop this $enable argument
>> ?
>>
> This socfpga_reset_deassert_bridges_handoff() would be called, bridges
> are released based on DTS.
Seems the naming needs some work, it's quite chaotic and inobvious then.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>> .../include/mach/reset_manager_arria10.h | 2 +-
>>> arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
>>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-
>>> socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
>>> socfpga/include/mach/reset_manager_arria10.h
>>> index 7922db8..b6d7f4f 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>>> @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
>>> void socfpga_reset_assert_fpga_connected_peripherals(void);
>>> void socfpga_reset_deassert_osc1wd0(void);
>>> void socfpga_reset_uart(int assert);
>>> -int socfpga_bridges_reset(int enable);
>>> +int socfpga_bridges_reset(void);
>>>
>>> struct socfpga_reset_manager {
>>> u32 stat;
>>> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
>>> b/arch/arm/mach-socfpga/reset_manager_arria10.c
>>> index d8c858c..66f1ec2 100644
>>> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
>>> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
>>> @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
>>> }
>>>
>>> #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
>>> -int socfpga_bridges_reset(int enable)
>>> +int socfpga_bridges_reset(void)
>>> {
>>> /* For SoCFPGA-VT, this is NOP. */
>>> return 0;
>>> }
>>> #else
>>> -int socfpga_bridges_reset(int enable)
>>> +int socfpga_bridges_reset(void)
>>> {
>>> int ret;
>>>
>>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-08 9:52 ` Marek Vasut
@ 2017-05-09 4:23 ` Chee, Tien Fong
2017-05-09 7:56 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-09 4:23 UTC (permalink / raw)
To: u-boot
On Isn, 2017-05-08 at 11:52 +0200, Marek Vasut wrote:
> On 05/08/2017 06:17 AM, Chee, Tien Fong wrote:
> >
> > On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
> > >
> > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Remove unused passing parameter of socfpga_bridges_reset
> > > > function
> > > > in
> > > > SoCFPGA Arria10.
> > > So how do you un-reset the bridges if you drop this $enable
> > > argument
> > > ?
> > >
> > This socfpga_reset_deassert_bridges_handoff() would be called,
> > bridges
> > are released based on DTS.
> Seems the naming needs some work, it's quite chaotic and inobvious
> then.
>
It is okay for "socfpga_bridges_unreset_byfdt()?
> >
> > >
> > > >
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > > .../include/mach/reset_manager_arria10.h | 2 +-
> > > > arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
> > > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-
> > > > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
> > > > socfpga/include/mach/reset_manager_arria10.h
> > > > index 7922db8..b6d7f4f 100644
> > > > --- a/arch/arm/mach-
> > > > socfpga/include/mach/reset_manager_arria10.h
> > > > +++ b/arch/arm/mach-
> > > > socfpga/include/mach/reset_manager_arria10.h
> > > > @@ -17,7 +17,7 @@ int
> > > > socfpga_reset_deassert_bridges_handoff(void);
> > > > void socfpga_reset_assert_fpga_connected_peripherals(void);
> > > > void socfpga_reset_deassert_osc1wd0(void);
> > > > void socfpga_reset_uart(int assert);
> > > > -int socfpga_bridges_reset(int enable);
> > > > +int socfpga_bridges_reset(void);
> > > >
> > > > struct socfpga_reset_manager {
> > > > u32 stat;
> > > > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > index d8c858c..66f1ec2 100644
> > > > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
> > > > }
> > > >
> > > > #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> > > > -int socfpga_bridges_reset(int enable)
> > > > +int socfpga_bridges_reset(void)
> > > > {
> > > > /* For SoCFPGA-VT, this is NOP. */
> > > > return 0;
> > > > }
> > > > #else
> > > > -int socfpga_bridges_reset(int enable)
> > > > +int socfpga_bridges_reset(void)
> > > > {
> > > > int ret;
> > > >
> > > >
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-09 4:23 ` Chee, Tien Fong
@ 2017-05-09 7:56 ` Marek Vasut
2017-05-10 8:34 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-09 7:56 UTC (permalink / raw)
To: u-boot
On 05/09/2017 06:23 AM, Chee, Tien Fong wrote:
> On Isn, 2017-05-08 at 11:52 +0200, Marek Vasut wrote:
>> On 05/08/2017 06:17 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
>>>>
>>>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> Remove unused passing parameter of socfpga_bridges_reset
>>>>> function
>>>>> in
>>>>> SoCFPGA Arria10.
>>>> So how do you un-reset the bridges if you drop this $enable
>>>> argument
>>>> ?
>>>>
>>> This socfpga_reset_deassert_bridges_handoff() would be called,
>>> bridges
>>> are released based on DTS.
>> Seems the naming needs some work, it's quite chaotic and inobvious
>> then.
>>
> It is okay for "socfpga_bridges_unreset_byfdt()?
Just keep it as-is for now ...
>>>>
>>>>>
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>> ---
>>>>> .../include/mach/reset_manager_arria10.h | 2 +-
>>>>> arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
>>>>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-
>>>>> socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
>>>>> socfpga/include/mach/reset_manager_arria10.h
>>>>> index 7922db8..b6d7f4f 100644
>>>>> --- a/arch/arm/mach-
>>>>> socfpga/include/mach/reset_manager_arria10.h
>>>>> +++ b/arch/arm/mach-
>>>>> socfpga/include/mach/reset_manager_arria10.h
>>>>> @@ -17,7 +17,7 @@ int
>>>>> socfpga_reset_deassert_bridges_handoff(void);
>>>>> void socfpga_reset_assert_fpga_connected_peripherals(void);
>>>>> void socfpga_reset_deassert_osc1wd0(void);
>>>>> void socfpga_reset_uart(int assert);
>>>>> -int socfpga_bridges_reset(int enable);
>>>>> +int socfpga_bridges_reset(void);
>>>>>
>>>>> struct socfpga_reset_manager {
>>>>> u32 stat;
>>>>> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
>>>>> b/arch/arm/mach-socfpga/reset_manager_arria10.c
>>>>> index d8c858c..66f1ec2 100644
>>>>> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
>>>>> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
>>>>> @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
>>>>> }
>>>>>
>>>>> #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
>>>>> -int socfpga_bridges_reset(int enable)
>>>>> +int socfpga_bridges_reset(void)
>>>>> {
>>>>> /* For SoCFPGA-VT, this is NOP. */
>>>>> return 0;
>>>>> }
>>>>> #else
>>>>> -int socfpga_bridges_reset(int enable)
>>>>> +int socfpga_bridges_reset(void)
>>>>> {
>>>>> int ret;
>>>>>
>>>>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-09 7:56 ` Marek Vasut
@ 2017-05-10 8:34 ` Chee, Tien Fong
0 siblings, 0 replies; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-10 8:34 UTC (permalink / raw)
To: u-boot
On Sel, 2017-05-09 at 09:56 +0200, Marek Vasut wrote:
> On 05/09/2017 06:23 AM, Chee, Tien Fong wrote:
> >
> > On Isn, 2017-05-08 at 11:52 +0200, Marek Vasut wrote:
> > >
> > > On 05/08/2017 06:17 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > Remove unused passing parameter of socfpga_bridges_reset
> > > > > > function
> > > > > > in
> > > > > > SoCFPGA Arria10.
> > > > > So how do you un-reset the bridges if you drop this $enable
> > > > > argument
> > > > > ?
> > > > >
> > > > This socfpga_reset_deassert_bridges_handoff() would be called,
> > > > bridges
> > > > are released based on DTS.
> > > Seems the naming needs some work, it's quite chaotic and
> > > inobvious
> > > then.
> > >
> > It is okay for "socfpga_bridges_unreset_byfdt()?
> Just keep it as-is for now ...
>
Okay.
> >
> > >
> > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > ---
> > > > > > .../include/mach/reset_manager_arria10.h | 2
> > > > > > +-
> > > > > > arch/arm/mach-socfpga/reset_manager_arria10.c | 4
> > > > > > ++--
> > > > > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/mach-
> > > > > > socfpga/include/mach/reset_manager_arria10.h
> > > > > > b/arch/arm/mach-
> > > > > > socfpga/include/mach/reset_manager_arria10.h
> > > > > > index 7922db8..b6d7f4f 100644
> > > > > > --- a/arch/arm/mach-
> > > > > > socfpga/include/mach/reset_manager_arria10.h
> > > > > > +++ b/arch/arm/mach-
> > > > > > socfpga/include/mach/reset_manager_arria10.h
> > > > > > @@ -17,7 +17,7 @@ int
> > > > > > socfpga_reset_deassert_bridges_handoff(void);
> > > > > > void
> > > > > > socfpga_reset_assert_fpga_connected_peripherals(void);
> > > > > > void socfpga_reset_deassert_osc1wd0(void);
> > > > > > void socfpga_reset_uart(int assert);
> > > > > > -int socfpga_bridges_reset(int enable);
> > > > > > +int socfpga_bridges_reset(void);
> > > > > >
> > > > > > struct socfpga_reset_manager {
> > > > > > u32 stat;
> > > > > > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > > > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > > > index d8c858c..66f1ec2 100644
> > > > > > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > > > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > > > > > @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
> > > > > > }
> > > > > >
> > > > > > #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> > > > > > -int socfpga_bridges_reset(int enable)
> > > > > > +int socfpga_bridges_reset(void)
> > > > > > {
> > > > > > /* For SoCFPGA-VT, this is NOP. */
> > > > > > return 0;
> > > > > > }
> > > > > > #else
> > > > > > -int socfpga_bridges_reset(int enable)
> > > > > > +int socfpga_bridges_reset(void)
> > > > > > {
> > > > > > int ret;
> > > > > >
> > > > > >
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 11:11 ` Marek Vasut
2017-05-05 10:26 ` [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
` (4 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Convert Macro #define configuration to Kconfig method. All FPGA devices
enable configuration based on CONFIG_FPGA_ALTERA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
drivers/fpga/Kconfig | 5 ++++-
drivers/fpga/Makefile | 3 +--
include/altera.h | 2 +-
include/configs/socfpga_common.h | 3 ---
4 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index a760944..fc4ea0d 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -2,12 +2,15 @@ menu "FPGA support"
config FPGA
bool
+ help
+ Enable FPGA driver build.
config FPGA_ALTERA
bool "Enable Altera FPGA drivers"
+ default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
select FPGA
help
- Say Y here to enable the Altera FPGA driver
+ Default Y here to enable the Altera FPGA driver
This provides basic infrastructure to support Altera FPGA devices.
Enable Altera FPGA specific functions which includes bitstream
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 777706f..84e7605 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
obj-$(CONFIG_FPGA_XILINX) += xilinx.o
obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
-obj-y += altera.o
+obj-y += altera.o socfpga.o
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
-obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
endif
diff --git a/include/altera.h b/include/altera.h
index 48d3eb7..a627b37 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -109,7 +109,7 @@ typedef struct {
Altera_post_fn post;
} altera_board_specific_func;
-#ifdef CONFIG_FPGA_SOCFPGA
+#ifdef CONFIG_FPGA_ALTERA
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index da7e4ad..1b79c03 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -107,9 +107,6 @@
*/
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
#define CONFIG_FPGA_COUNT 1
#endif
#endif
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-05 10:26 ` [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method tien.fong.chee at intel.com
@ 2017-05-05 11:11 ` Marek Vasut
2017-05-08 3:02 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-05 11:11 UTC (permalink / raw)
To: u-boot
On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Convert Macro #define configuration to Kconfig method. All FPGA devices
> enable configuration based on CONFIG_FPGA_ALTERA.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> drivers/fpga/Kconfig | 5 ++++-
> drivers/fpga/Makefile | 3 +--
> include/altera.h | 2 +-
> include/configs/socfpga_common.h | 3 ---
> 4 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index a760944..fc4ea0d 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -2,12 +2,15 @@ menu "FPGA support"
>
> config FPGA
> bool
> + help
> + Enable FPGA driver build.
Separate patch please , also this is not driver, but framework . There's
not just drivers here IMO.
> config FPGA_ALTERA
> bool "Enable Altera FPGA drivers"
> + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
Should be selected by arch code, drop this.
> select FPGA
> help
> - Say Y here to enable the Altera FPGA driver
> + Default Y here to enable the Altera FPGA driver
Keep as is, it's up to user to decide.
> This provides basic infrastructure to support Altera FPGA devices.
> Enable Altera FPGA specific functions which includes bitstream
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 777706f..84e7605 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
> obj-$(CONFIG_FPGA_XILINX) += xilinx.o
> obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
> ifdef CONFIG_FPGA_ALTERA
> -obj-y += altera.o
> +obj-y += altera.o socfpga.o
Now all the ancient systems which had the ancient Altera FPGAs will
build-in the socfpga stuff too . That cannot work.
> obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> -obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> endif
> diff --git a/include/altera.h b/include/altera.h
> index 48d3eb7..a627b37 100644
> --- a/include/altera.h
> +++ b/include/altera.h
> @@ -109,7 +109,7 @@ typedef struct {
> Altera_post_fn post;
> } altera_board_specific_func;
>
> -#ifdef CONFIG_FPGA_SOCFPGA
> +#ifdef CONFIG_FPGA_ALTERA
> int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
> #endif
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index da7e4ad..1b79c03 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -107,9 +107,6 @@
> */
> #ifdef CONFIG_TARGET_SOCFPGA_GEN5
> #ifdef CONFIG_CMD_FPGA
> -#define CONFIG_FPGA
> -#define CONFIG_FPGA_ALTERA
> -#define CONFIG_FPGA_SOCFPGA
> #define CONFIG_FPGA_COUNT 1
> #endif
> #endif
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-05 11:11 ` Marek Vasut
@ 2017-05-08 3:02 ` Chee, Tien Fong
2017-05-08 9:57 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-08 3:02 UTC (permalink / raw)
To: u-boot
On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Convert Macro #define configuration to Kconfig method. All FPGA
> > devices
> > enable configuration based on CONFIG_FPGA_ALTERA.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > drivers/fpga/Kconfig | 5 ++++-
> > drivers/fpga/Makefile | 3 +--
> > include/altera.h | 2 +-
> > include/configs/socfpga_common.h | 3 ---
> > 4 files changed, 6 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index a760944..fc4ea0d 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -2,12 +2,15 @@ menu "FPGA support"
> >
> > config FPGA
> > bool
> > + help
> > + Enable FPGA driver build.
> Separate patch please , also this is not driver, but framework .
> There's
> not just drivers here IMO.
>
ohh...okay, so you prefer i revert the changes, or better explanation
in separate patch? if for later,what is your suggestion? Thanks.
> >
> > config FPGA_ALTERA
> > bool "Enable Altera FPGA drivers"
> > + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
> Should be selected by arch code, drop this.
>
just for clarity, are you means defconfig == "selected by arch code"?
> >
> > select FPGA
> > help
> > - Say Y here to enable the Altera FPGA driver
> > + Default Y here to enable the Altera FPGA driver
> Keep as is, it's up to user to decide.
>
I found that all users enable it, so that is why i set this as default,
otherwise i have to add this into their defconfig one by one. Users who
don't want enable it, they can set "N" in their defconfig. What do you
think?
> >
> > This provides basic infrastructure to support Altera
> > FPGA devices.
> > Enable Altera FPGA specific functions which includes
> > bitstream
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 777706f..84e7605 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
> > obj-$(CONFIG_FPGA_XILINX) += xilinx.o
> > obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
> > ifdef CONFIG_FPGA_ALTERA
> > -obj-y += altera.o
> > +obj-y += altera.o socfpga.o
> Now all the ancient systems which had the ancient Altera FPGAs will
> build-in the socfpga stuff too . That cannot work.
>
Okay, i will revert the changes.
> >
> > obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> > obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> > obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> > obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > -obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> > endif
> > diff --git a/include/altera.h b/include/altera.h
> > index 48d3eb7..a627b37 100644
> > --- a/include/altera.h
> > +++ b/include/altera.h
> > @@ -109,7 +109,7 @@ typedef struct {
> > Altera_post_fn post;
> > } altera_board_specific_func;
> >
> > -#ifdef CONFIG_FPGA_SOCFPGA
> > +#ifdef CONFIG_FPGA_ALTERA
> > int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> > rbf_size);
> > #endif
> >
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index da7e4ad..1b79c03 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -107,9 +107,6 @@
> > */
> > #ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > #ifdef CONFIG_CMD_FPGA
> > -#define CONFIG_FPGA
> > -#define CONFIG_FPGA_ALTERA
> > -#define CONFIG_FPGA_SOCFPGA
> > #define CONFIG_FPGA_COUNT 1
> > #endif
> > #endif
> >
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-08 3:02 ` Chee, Tien Fong
@ 2017-05-08 9:57 ` Marek Vasut
2017-05-09 5:02 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-08 9:57 UTC (permalink / raw)
To: u-boot
On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
> On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Convert Macro #define configuration to Kconfig method. All FPGA
>>> devices
>>> enable configuration based on CONFIG_FPGA_ALTERA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>> drivers/fpga/Kconfig | 5 ++++-
>>> drivers/fpga/Makefile | 3 +--
>>> include/altera.h | 2 +-
>>> include/configs/socfpga_common.h | 3 ---
>>> 4 files changed, 6 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>>> index a760944..fc4ea0d 100644
>>> --- a/drivers/fpga/Kconfig
>>> +++ b/drivers/fpga/Kconfig
>>> @@ -2,12 +2,15 @@ menu "FPGA support"
>>>
>>> config FPGA
>>> bool
>>> + help
>>> + Enable FPGA driver build.
>> Separate patch please , also this is not driver, but framework .
>> There's
>> not just drivers here IMO.
>>
> ohh...okay, so you prefer i revert the changes, or better explanation
> in separate patch? if for later,what is your suggestion? Thanks.
Turning this whole FPGA subsystem into Kconfig should be a separate
patch. There's a script for that too and you need to convert and build
test all the boards which define CONFIG_FPGA .
>>> config FPGA_ALTERA
>>> bool "Enable Altera FPGA drivers"
>>> + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
>> Should be selected by arch code, drop this.
>>
> just for clarity, are you means defconfig == "selected by arch code"?
I mean arch/arm/mach-socfpga/Kconfig
>>>
>>> select FPGA
>>> help
>>> - Say Y here to enable the Altera FPGA driver
>>> + Default Y here to enable the Altera FPGA driver
>> Keep as is, it's up to user to decide.
>>
> I found that all users enable it, so that is why i set this as default,
You set it as default in arch/arm/mach-socfpga/Kconfig , no need to
modify the text.
> otherwise i have to add this into their defconfig one by one. Users who
> don't want enable it, they can set "N" in their defconfig. What do you
> think?
>>>
>>> This provides basic infrastructure to support Altera
>>> FPGA devices.
>>> Enable Altera FPGA specific functions which includes
>>> bitstream
>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>>> index 777706f..84e7605 100644
>>> --- a/drivers/fpga/Makefile
>>> +++ b/drivers/fpga/Makefile
>>> @@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
>>> obj-$(CONFIG_FPGA_XILINX) += xilinx.o
>>> obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
>>> ifdef CONFIG_FPGA_ALTERA
>>> -obj-y += altera.o
>>> +obj-y += altera.o socfpga.o
>> Now all the ancient systems which had the ancient Altera FPGAs will
>> build-in the socfpga stuff too . That cannot work.
>>
> Okay, i will revert the changes.
>>>
>>> obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
>>> obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
>>> obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
>>> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
>>> -obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
>>> endif
>>> diff --git a/include/altera.h b/include/altera.h
>>> index 48d3eb7..a627b37 100644
>>> --- a/include/altera.h
>>> +++ b/include/altera.h
>>> @@ -109,7 +109,7 @@ typedef struct {
>>> Altera_post_fn post;
>>> } altera_board_specific_func;
>>>
>>> -#ifdef CONFIG_FPGA_SOCFPGA
>>> +#ifdef CONFIG_FPGA_ALTERA
>>> int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
>>> rbf_size);
>>> #endif
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index da7e4ad..1b79c03 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -107,9 +107,6 @@
>>> */
>>> #ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> #ifdef CONFIG_CMD_FPGA
>>> -#define CONFIG_FPGA
>>> -#define CONFIG_FPGA_ALTERA
>>> -#define CONFIG_FPGA_SOCFPGA
>>> #define CONFIG_FPGA_COUNT 1
>>> #endif
>>> #endif
>>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-08 9:57 ` Marek Vasut
@ 2017-05-09 5:02 ` Chee, Tien Fong
2017-05-09 7:58 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-09 5:02 UTC (permalink / raw)
To: u-boot
On Isn, 2017-05-08 at 11:57 +0200, Marek Vasut wrote:
> On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
> >
> > On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> > >
> > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Convert Macro #define configuration to Kconfig method. All FPGA
> > > > devices
> > > > enable configuration based on CONFIG_FPGA_ALTERA.
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > > drivers/fpga/Kconfig | 5 ++++-
> > > > drivers/fpga/Makefile | 3 +--
> > > > include/altera.h | 2 +-
> > > > include/configs/socfpga_common.h | 3 ---
> > > > 4 files changed, 6 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > index a760944..fc4ea0d 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -2,12 +2,15 @@ menu "FPGA support"
> > > >
> > > > config FPGA
> > > > bool
> > > > + help
> > > > + Enable FPGA driver build.
> > > Separate patch please , also this is not driver, but framework .
> > > There's
> > > not just drivers here IMO.
> > >
> > ohh...okay, so you prefer i revert the changes, or better
> > explanation
> > in separate patch? if for later,what is your suggestion? Thanks.
> Turning this whole FPGA subsystem into Kconfig should be a separat
> patch. There's a script for that too and you need to convert and
> build
> test all the boards which define CONFIG_FPGA .
>
Okay, this patch is specific for turning whole FPGA sybsytem into
Kconfig. I will use moveconfig.py for this. thanks.
> >
> > >
> > > >
> > > > config FPGA_ALTERA
> > > > bool "Enable Altera FPGA drivers"
> > > > + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
> > > Should be selected by arch code, drop this.
> > >
> > just for clarity, are you means defconfig == "selected by arch
> > code"?
> I mean arch/arm/mach-socfpga/Kconfig
>
With moveconfig.py, i think this change is not required.
> >
> > >
> > > >
> > > >
> > > > select FPGA
> > > > help
> > > > - Say Y here to enable the Altera FPGA driver
> > > > + Default Y here to enable the Altera FPGA driver
> > > Keep as is, it's up to user to decide.
> > >
> > I found that all users enable it, so that is why i set this as
> > default,
> You set it as default in arch/arm/mach-socfpga/Kconfig , no need to
> modify the text.
>
> >
> > otherwise i have to add this into their defconfig one by one. Users
> > who
> > don't want enable it, they can set "N" in their defconfig. What do
> > you
> > think?
> > >
> > > >
> > > >
> > > > This provides basic infrastructure to support Altera
> > > > FPGA devices.
> > > > Enable Altera FPGA specific functions which includes
> > > > bitstream
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > index 777706f..84e7605 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
> > > > obj-$(CONFIG_FPGA_XILINX) += xilinx.o
> > > > obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
> > > > ifdef CONFIG_FPGA_ALTERA
> > > > -obj-y += altera.o
> > > > +obj-y += altera.o socfpga.o
> > > Now all the ancient systems which had the ancient Altera FPGAs
> > > will
> > > build-in the socfpga stuff too . That cannot work.
> > >
> > Okay, i will revert the changes.
> > >
> > > >
> > > >
> > > > obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> > > > obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> > > > obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> > > > obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > > > -obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> > > > endif
> > > > diff --git a/include/altera.h b/include/altera.h
> > > > index 48d3eb7..a627b37 100644
> > > > --- a/include/altera.h
> > > > +++ b/include/altera.h
> > > > @@ -109,7 +109,7 @@ typedef struct {
> > > > Altera_post_fn post;
> > > > } altera_board_specific_func;
> > > >
> > > > -#ifdef CONFIG_FPGA_SOCFPGA
> > > > +#ifdef CONFIG_FPGA_ALTERA
> > > > int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > size_t
> > > > rbf_size);
> > > > #endif
> > > >
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index da7e4ad..1b79c03 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -107,9 +107,6 @@
> > > > */
> > > > #ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > > > #ifdef CONFIG_CMD_FPGA
> > > > -#define CONFIG_FPGA
> > > > -#define CONFIG_FPGA_ALTERA
> > > > -#define CONFIG_FPGA_SOCFPGA
> > > > #define CONFIG_FPGA_COUNT 1
> > > > #endif
> > > > #endif
> > > >
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-09 5:02 ` Chee, Tien Fong
@ 2017-05-09 7:58 ` Marek Vasut
2017-05-10 8:28 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-09 7:58 UTC (permalink / raw)
To: u-boot
On 05/09/2017 07:02 AM, Chee, Tien Fong wrote:
> On Isn, 2017-05-08 at 11:57 +0200, Marek Vasut wrote:
>> On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
>>>>
>>>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> Convert Macro #define configuration to Kconfig method. All FPGA
>>>>> devices
>>>>> enable configuration based on CONFIG_FPGA_ALTERA.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>> ---
>>>>> drivers/fpga/Kconfig | 5 ++++-
>>>>> drivers/fpga/Makefile | 3 +--
>>>>> include/altera.h | 2 +-
>>>>> include/configs/socfpga_common.h | 3 ---
>>>>> 4 files changed, 6 insertions(+), 7 deletions(-)
>>>>>
>>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>>>>> index a760944..fc4ea0d 100644
>>>>> --- a/drivers/fpga/Kconfig
>>>>> +++ b/drivers/fpga/Kconfig
>>>>> @@ -2,12 +2,15 @@ menu "FPGA support"
>>>>>
>>>>> config FPGA
>>>>> bool
>>>>> + help
>>>>> + Enable FPGA driver build.
>>>> Separate patch please , also this is not driver, but framework .
>>>> There's
>>>> not just drivers here IMO.
>>>>
>>> ohh...okay, so you prefer i revert the changes, or better
>>> explanation
>>> in separate patch? if for later,what is your suggestion? Thanks.
>> Turning this whole FPGA subsystem into Kconfig should be a separat
>> patch. There's a script for that too and you need to convert and
>> build
>> test all the boards which define CONFIG_FPGA .
>>
> Okay, this patch is specific for turning whole FPGA sybsytem into
> Kconfig. I will use moveconfig.py for this. thanks.
>>>
>>>>
>>>>>
>>>>> config FPGA_ALTERA
>>>>> bool "Enable Altera FPGA drivers"
>>>>> + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
>>>> Should be selected by arch code, drop this.
>>>>
>>> just for clarity, are you means defconfig == "selected by arch
>>> code"?
>> I mean arch/arm/mach-socfpga/Kconfig
>>
> With moveconfig.py, i think this change is not required.
So, who will enable FPGA_ALTERA ?
[...]
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-09 7:58 ` Marek Vasut
@ 2017-05-10 8:28 ` Chee, Tien Fong
2017-05-11 4:09 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-10 8:28 UTC (permalink / raw)
To: u-boot
On Sel, 2017-05-09 at 09:58 +0200, Marek Vasut wrote:
> On 05/09/2017 07:02 AM, Chee, Tien Fong wrote:
> >
> > On Isn, 2017-05-08 at 11:57 +0200, Marek Vasut wrote:
> > >
> > > On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > Convert Macro #define configuration to Kconfig method. All
> > > > > > FPGA
> > > > > > devices
> > > > > > enable configuration based on CONFIG_FPGA_ALTERA.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > ---
> > > > > > drivers/fpga/Kconfig | 5 ++++-
> > > > > > drivers/fpga/Makefile | 3 +--
> > > > > > include/altera.h | 2 +-
> > > > > > include/configs/socfpga_common.h | 3 ---
> > > > > > 4 files changed, 6 insertions(+), 7 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > index a760944..fc4ea0d 100644
> > > > > > --- a/drivers/fpga/Kconfig
> > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > @@ -2,12 +2,15 @@ menu "FPGA support"
> > > > > >
> > > > > > config FPGA
> > > > > > bool
> > > > > > + help
> > > > > > + Enable FPGA driver build.
> > > > > Separate patch please , also this is not driver, but
> > > > > framework .
> > > > > There's
> > > > > not just drivers here IMO.
> > > > >
> > > > ohh...okay, so you prefer i revert the changes, or better
> > > > explanation
> > > > in separate patch? if for later,what is your suggestion?
> > > > Thanks.
> > > Turning this whole FPGA subsystem into Kconfig should be a
> > > separat
> > > patch. There's a script for that too and you need to convert and
> > > build
> > > test all the boards which define CONFIG_FPGA .
> > >
> > Okay, this patch is specific for turning whole FPGA sybsytem into
> > Kconfig. I will use moveconfig.py for this. thanks.
> > >
> > > >
> > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > > config FPGA_ALTERA
> > > > > > bool "Enable Altera FPGA drivers"
> > > > > > + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
> > > > > Should be selected by arch code, drop this.
> > > > >
> > > > just for clarity, are you means defconfig == "selected by arch
> > > > code"?
> > > I mean arch/arm/mach-socfpga/Kconfig
> > >
> > With moveconfig.py, i think this change is not required.
> So, who will enable FPGA_ALTERA ?
>
Below boards will enable the FPGA_ALTERA, their header file include
socfpga_common.h, and CONFIG_CMD_FPGA set to y by default. i believe
moveconfig.py will set this FPGA_ALTERA into their defconfig
respectively.
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_IS1
bool "IS1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
bool "samtec VIN|ING FPGA (Cyclone V)"
select BOARD_LATE_INIT
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
> [...]
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-10 8:28 ` Chee, Tien Fong
@ 2017-05-11 4:09 ` Chee, Tien Fong
2017-05-11 11:47 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-11 4:09 UTC (permalink / raw)
To: u-boot
On Rab, 2017-05-10 at 16:28 +0800, Chee, Tien Fong wrote:
> >
> On Sel, 2017-05-09 at 09:58 +0200, Marek Vasut wrote:
> >
> > On 05/09/2017 07:02 AM, Chee, Tien Fong wrote:
> > >
> > >
> > > On Isn, 2017-05-08 at 11:57 +0200, Marek Vasut wrote:
> > > >
> > > >
> > > > On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
> > > > >
> > > > >
> > > > >
> > > > > On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > >
> > > > > > > Convert Macro #define configuration to Kconfig method.
> > > > > > > All
> > > > > > > FPGA
> > > > > > > devices
> > > > > > > enable configuration based on CONFIG_FPGA_ALTERA.
> > > > > > >
> > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > ---
> > > > > > > drivers/fpga/Kconfig | 5 ++++-
> > > > > > > drivers/fpga/Makefile | 3 +--
> > > > > > > include/altera.h | 2 +-
> > > > > > > include/configs/socfpga_common.h | 3 ---
> > > > > > > 4 files changed, 6 insertions(+), 7 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > index a760944..fc4ea0d 100644
> > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > @@ -2,12 +2,15 @@ menu "FPGA support"
> > > > > > >
> > > > > > > config FPGA
> > > > > > > bool
> > > > > > > + help
> > > > > > > + Enable FPGA driver build.
> > > > > > Separate patch please , also this is not driver, but
> > > > > > framework .
> > > > > > There's
> > > > > > not just drivers here IMO.
> > > > > >
> > > > > ohh...okay, so you prefer i revert the changes, or better
> > > > > explanation
> > > > > in separate patch? if for later,what is your suggestion?
> > > > > Thanks.
> > > > Turning this whole FPGA subsystem into Kconfig should be a
> > > > separat
> > > > patch. There's a script for that too and you need to convert
> > > > and
> > > > build
> > > > test all the boards which define CONFIG_FPGA .
> > > >
> > > Okay, this patch is specific for turning whole FPGA sybsytem into
> > > Kconfig. I will use moveconfig.py for this. thanks.
> > > >
> > > >
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > config FPGA_ALTERA
> > > > > > > bool "Enable Altera FPGA drivers"
> > > > > > > + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
> > > > > > Should be selected by arch code, drop this.
> > > > > >
> > > > > just for clarity, are you means defconfig == "selected by
> > > > > arch
> > > > > code"?
> > > > I mean arch/arm/mach-socfpga/Kconfig
> > > >
> > > With moveconfig.py, i think this change is not required.
> > So, who will enable FPGA_ALTERA ?
> >
> Below boards will enable the FPGA_ALTERA, their header file include
> socfpga_common.h, and CONFIG_CMD_FPGA set to y by default. i believe
> moveconfig.py will set this FPGA_ALTERA into their defconfig
> respectively.
> config TARGET_SOCFPGA_ARRIA10_SOCDK
> bool "Altera SOCFPGA SoCDK (Arria 10)"
> select TARGET_SOCFPGA_ARRIA10
>
> config TARGET_SOCFPGA_ARRIA5_SOCDK
> bool "Altera SOCFPGA SoCDK (Arria V)"
> select TARGET_SOCFPGA_ARRIA5
>
> config TARGET_SOCFPGA_CYCLONE5_SOCDK
> bool "Altera SOCFPGA SoCDK (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_ARIES_MCVEVK
> bool "Aries MCVEVK (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_EBV_SOCRATES
> bool "EBV SoCrates (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_IS1
> bool "IS1 (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> bool "samtec VIN|ING FPGA (Cyclone V)"
> select BOARD_LATE_INIT
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_SR1500
> bool "SR1500 (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_TERASIC_DE0_NANO
> bool "Terasic DE0-Nano-Atlas (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_TERASIC_DE10_NANO
> bool "Terasic DE10-Nano (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_TERASIC_DE1_SOC
> bool "Terasic DE1-SoC (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> config TARGET_SOCFPGA_TERASIC_SOCKIT
> bool "Terasic SoCkit (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
convert to Kconfig take time to run, more than 1k++ defconfg need to be
processed, so i plan to take out from this patch set and submiting
separately after this patchset. It sounds okay for you, marek :)?
> > [...]
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.
2017-05-11 4:09 ` Chee, Tien Fong
@ 2017-05-11 11:47 ` Marek Vasut
0 siblings, 0 replies; 28+ messages in thread
From: Marek Vasut @ 2017-05-11 11:47 UTC (permalink / raw)
To: u-boot
On 05/11/2017 06:09 AM, Chee, Tien Fong wrote:
> On Rab, 2017-05-10 at 16:28 +0800, Chee, Tien Fong wrote:
>>>
>
>
>> On Sel, 2017-05-09 at 09:58 +0200, Marek Vasut wrote:
>>>
>>> On 05/09/2017 07:02 AM, Chee, Tien Fong wrote:
>>>>
>>>>
>>>> On Isn, 2017-05-08 at 11:57 +0200, Marek Vasut wrote:
>>>>>
>>>>>
>>>>> On 05/08/2017 05:02 AM, Chee, Tien Fong wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>>
>>>>>>>> Convert Macro #define configuration to Kconfig method.
>>>>>>>> All
>>>>>>>> FPGA
>>>>>>>> devices
>>>>>>>> enable configuration based on CONFIG_FPGA_ALTERA.
>>>>>>>>
>>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>> ---
>>>>>>>> drivers/fpga/Kconfig | 5 ++++-
>>>>>>>> drivers/fpga/Makefile | 3 +--
>>>>>>>> include/altera.h | 2 +-
>>>>>>>> include/configs/socfpga_common.h | 3 ---
>>>>>>>> 4 files changed, 6 insertions(+), 7 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>>>>>>>> index a760944..fc4ea0d 100644
>>>>>>>> --- a/drivers/fpga/Kconfig
>>>>>>>> +++ b/drivers/fpga/Kconfig
>>>>>>>> @@ -2,12 +2,15 @@ menu "FPGA support"
>>>>>>>>
>>>>>>>> config FPGA
>>>>>>>> bool
>>>>>>>> + help
>>>>>>>> + Enable FPGA driver build.
>>>>>>> Separate patch please , also this is not driver, but
>>>>>>> framework .
>>>>>>> There's
>>>>>>> not just drivers here IMO.
>>>>>>>
>>>>>> ohh...okay, so you prefer i revert the changes, or better
>>>>>> explanation
>>>>>> in separate patch? if for later,what is your suggestion?
>>>>>> Thanks.
>>>>> Turning this whole FPGA subsystem into Kconfig should be a
>>>>> separat
>>>>> patch. There's a script for that too and you need to convert
>>>>> and
>>>>> build
>>>>> test all the boards which define CONFIG_FPGA .
>>>>>
>>>> Okay, this patch is specific for turning whole FPGA sybsytem into
>>>> Kconfig. I will use moveconfig.py for this. thanks.
>>>>>
>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> config FPGA_ALTERA
>>>>>>>> bool "Enable Altera FPGA drivers"
>>>>>>>> + default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
>>>>>>> Should be selected by arch code, drop this.
>>>>>>>
>>>>>> just for clarity, are you means defconfig == "selected by
>>>>>> arch
>>>>>> code"?
>>>>> I mean arch/arm/mach-socfpga/Kconfig
>>>>>
>>>> With moveconfig.py, i think this change is not required.
>>> So, who will enable FPGA_ALTERA ?
>>>
>> Below boards will enable the FPGA_ALTERA, their header file include
>> socfpga_common.h, and CONFIG_CMD_FPGA set to y by default. i believe
>> moveconfig.py will set this FPGA_ALTERA into their defconfig
>> respectively.
>> config TARGET_SOCFPGA_ARRIA10_SOCDK
>> bool "Altera SOCFPGA SoCDK (Arria 10)"
>> select TARGET_SOCFPGA_ARRIA10
>>
>> config TARGET_SOCFPGA_ARRIA5_SOCDK
>> bool "Altera SOCFPGA SoCDK (Arria V)"
>> select TARGET_SOCFPGA_ARRIA5
>>
>> config TARGET_SOCFPGA_CYCLONE5_SOCDK
>> bool "Altera SOCFPGA SoCDK (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_ARIES_MCVEVK
>> bool "Aries MCVEVK (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_EBV_SOCRATES
>> bool "EBV SoCrates (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_IS1
>> bool "IS1 (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>> bool "samtec VIN|ING FPGA (Cyclone V)"
>> select BOARD_LATE_INIT
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_SR1500
>> bool "SR1500 (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_TERASIC_DE0_NANO
>> bool "Terasic DE0-Nano-Atlas (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_TERASIC_DE10_NANO
>> bool "Terasic DE10-Nano (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_TERASIC_DE1_SOC
>> bool "Terasic DE1-SoC (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
>>
>> config TARGET_SOCFPGA_TERASIC_SOCKIT
>> bool "Terasic SoCkit (Cyclone V)"
>> select TARGET_SOCFPGA_CYCLONE5
> convert to Kconfig take time to run, more than 1k++ defconfg need to be
> processed, so i plan to take out from this patch set and submiting
> separately after this patchset. It sounds okay for you, marek :)?
Yes, it takes time. That's fine.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 11:13 ` Marek Vasut
2017-05-05 10:26 ` [U-Boot] [PATCH 4/7] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
` (3 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move FPGA driver which is Gen5 specific code into Gen5 files.
No functional change.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +-
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +----
.../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
drivers/Makefile | 1 +
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga.c | 267 +-------------------
drivers/fpga/{socfpga.c => socfpga_gen5.c} | 29 +--
7 files changed, 48 insertions(+), 386 deletions(-)
copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (92%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 41b779c..286bfef 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
obj-y += board.o
obj-y += clock_manager.o
-obj-y += fpga_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
@@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
+obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..69d8613 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -10,58 +10,9 @@
#include <altera.h>
-struct socfpga_fpga_manager {
- /* FPGA Manager Module */
- u32 stat; /* 0x00 */
- u32 ctrl;
- u32 dclkcnt;
- u32 dclkstat;
- u32 gpo; /* 0x10 */
- u32 gpi;
- u32 misci; /* 0x18 */
- u32 _pad_0x1c_0x82c[517];
-
- /* Configuration Monitor (MON) Registers */
- u32 gpio_inten; /* 0x830 */
- u32 gpio_intmask;
- u32 gpio_inttype_level;
- u32 gpio_int_polarity;
- u32 gpio_intstatus; /* 0x840 */
- u32 gpio_raw_intstatus;
- u32 _pad_0x848;
- u32 gpio_porta_eoi;
- u32 gpio_ext_porta; /* 0x850 */
- u32 _pad_0x854_0x85c[3];
- u32 gpio_1s_sync; /* 0x860 */
- u32 _pad_0x864_0x868[2];
- u32 gpio_ver_id_code;
- u32 gpio_config_reg2; /* 0x870 */
- u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#endif
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
@@ -74,4 +25,12 @@ int fpgamgr_test_fpga_ready(void);
int fpgamgr_poll_fpga_ready(void);
int fpgamgr_get_mode(void);
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+
+#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 57%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
index a077e22..2de7a11 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
@@ -1,14 +1,38 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef _FPGA_MANAGER_H_
-#define _FPGA_MANAGER_H_
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
-#include <altera.h>
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
/* FPGA Manager Module */
@@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
u32 gpio_config_reg1;
};
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
-
-/* FPGA CD Ratio Value */
-#define CDRATIO_x1 0x0
-#define CDRATIO_x2 0x1
-#define CDRATIO_x4 0x2
-#define CDRATIO_x8 0x3
-
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
-int fpgamgr_get_mode(void);
+#endif /* __ASSEMBLY__ */
-#endif /* _FPGA_MANAGER_H_ */
+#endif /* _FPGA_MANAGER_GEN5_H_ */
diff --git a/drivers/Makefile b/drivers/Makefile
index 4a4b237..b4a2230 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_FPGA) += fpga/
endif
ifdef CONFIG_TPL_BUILD
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 84e7605..649b6d1 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
endif
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..30ebee8 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -14,23 +14,10 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
- clrsetbits_le32(&fpgamgr_regs->ctrl,
- 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
- (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
+int fpgamgr_dclkcnt_set(unsigned long cnt)
{
unsigned long i;
@@ -52,253 +39,3 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt)
return -ETIMEDOUT;
}
-
-/* Start the FPGA programming by initialize the FPGA Manager */
-static int fpgamgr_program_init(void)
-{
- unsigned long msel, i;
-
- /* Get the MSEL value */
- msel = readl(&fpgamgr_regs->stat);
- msel &= FPGAMGRREGS_STAT_MSEL_MASK;
- msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
-
- /*
- * Set the cfg width
- * If MSEL[3] = 1, cfg width = 32 bit
- */
- if (msel & 0x8) {
- setbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- /* MSEL[1:0] = 2, CD Ratio = 8 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x8);
-
- } else { /* MSEL[3] = 0 */
- clrbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 2 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x2);
- /* MSEL[1:0] = 2, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- }
-
- /* To enable FPGA Manager configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
-
- /* To enable FPGA Manager drive over configuration line */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- /* Put FPGA into reset phase */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (1) wait until FPGA enter reset phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
- break;
- }
-
- /* If not in reset state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
- puts("FPGA: Could not reset\n");
- return -1;
- }
-
- /* Release FPGA from reset phase */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (2) wait until FPGA enter configuration phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
- puts("FPGA: Could not configure\n");
- return -2;
- }
-
- /* Clear all interrupts in CB Monitor */
- writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
-
- /* Enable AXI configuration */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
-{
- uint32_t src = (uint32_t)rbf_data;
- uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
-
- /* Number of loops for 32-byte long copying. */
- uint32_t loops32 = rbf_size / 32;
- /* Number of loops for 4-byte long copying + trailing bytes */
- uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
-
- asm volatile(
- "1: ldmia %0!, {r0-r7}\n"
- " stmia %1!, {r0-r7}\n"
- " sub %1, #32\n"
- " subs %2, #1\n"
- " bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
- " str %2, [%1]\n"
- " subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
- : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
- : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
-}
-
-/* Ensure the FPGA entering config done */
-static int fpgamgr_program_poll_cd(void)
-{
- const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
- FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
-
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
-
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
- }
-
- /* Disable AXI configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Ensure the FPGA entering init phase */
-static int fpgamgr_program_poll_initphase(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to enter initialization phase */
- if (fpgamgr_dclkcnt_set(0x4))
- return -5;
-
- /* (4) wait until FPGA enter init phase or user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
- break;
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -6;
-
- return 0;
-}
-
-/* Ensure the FPGA entering user mode */
-static int fpgamgr_program_poll_usermode(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to exit initialization phase */
- if (fpgamgr_dclkcnt_set(0x5000))
- return -7;
-
- /* (5) wait until FPGA enter user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -8;
-
- /* To release FPGA Manager drive over configuration line */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- return 0;
-}
-
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
-int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
-{
- unsigned long status;
-
- if ((uint32_t)rbf_data & 0x3) {
- puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
- return -EINVAL;
- }
-
- /* Prior programming the FPGA, all bridges need to be shut off */
-
- /* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
-
- /* Disable all signals from FPGA to HPS SDRAM */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
- writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
-
- /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
- socfpga_bridges_reset(1);
-
- /* Unmap the bridges from NIC-301 */
- writel(0x1, SOCFPGA_L3REGS_ADDRESS);
-
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init();
- if (status)
- return status;
-
- /* Write the RBF data to FPGA Manager */
- fpgamgr_program_write(rbf_data, rbf_size);
-
- /* Ensure the FPGA entering config done */
- status = fpgamgr_program_poll_cd();
- if (status)
- return status;
-
- /* Ensure the FPGA entering init phase */
- status = fpgamgr_program_poll_initphase();
- if (status)
- return status;
-
- /* Ensure the FPGA entering user mode */
- return fpgamgr_program_poll_usermode();
-}
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
similarity index 92%
copy from drivers/fpga/socfpga.c
copy to drivers/fpga/socfpga_gen5.c
index f1b2f2c..6992d83 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -14,9 +14,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
static struct socfpga_system_manager *sysmgr_regs =
@@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
}
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
-{
- unsigned long i;
-
- /* Clear any existing done status */
- if (readl(&fpgamgr_regs->dclkstat))
- writel(0x1, &fpgamgr_regs->dclkstat);
-
- /* Write the dclkcnt */
- writel(cnt, &fpgamgr_regs->dclkcnt);
-
- /* Wait till the dclkcnt done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (!readl(&fpgamgr_regs->dclkstat))
- continue;
-
- writel(0x1, &fpgamgr_regs->dclkstat);
- return 0;
- }
-
- return -ETIMEDOUT;
-}
-
/* Start the FPGA programming by initialize the FPGA Manager */
static int fpgamgr_program_init(void)
{
@@ -267,7 +241,6 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
}
/* Prior programming the FPGA, all bridges need to be shut off */
-
/* Disable all signals from hps peripheral controller to fpga */
writel(0, &sysmgr_regs->fpgaintfgrp_module);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-05 10:26 ` [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
@ 2017-05-05 11:13 ` Marek Vasut
2017-05-08 4:39 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-05 11:13 UTC (permalink / raw)
To: u-boot
On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Move FPGA driver which is Gen5 specific code into Gen5 files.
> No functional change.
It's a driver, so it should stay in drivers/ . If you need to split it,
split it in drivers/fpga/ and add Kconfig option(s)
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 2 +-
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +----
> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
> drivers/Makefile | 1 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/socfpga.c | 267 +-------------------
> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 29 +--
> 7 files changed, 48 insertions(+), 386 deletions(-)
> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (92%)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 41b779c..286bfef 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -9,7 +9,6 @@
>
> obj-y += board.o
> obj-y += clock_manager.o
> -obj-y += fpga_manager.o
> obj-y += misc.o
> obj-y += reset_manager.o
> obj-y += timer.o
> @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
> obj-y += scan_manager.o
> obj-y += system_manager_gen5.o
> obj-y += wrap_pll_config.o
> +obj-y += fpga_manager.o
> endif
>
> ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> index a077e22..69d8613 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> @@ -10,58 +10,9 @@
>
> #include <altera.h>
>
> -struct socfpga_fpga_manager {
> - /* FPGA Manager Module */
> - u32 stat; /* 0x00 */
> - u32 ctrl;
> - u32 dclkcnt;
> - u32 dclkstat;
> - u32 gpo; /* 0x10 */
> - u32 gpi;
> - u32 misci; /* 0x18 */
> - u32 _pad_0x1c_0x82c[517];
> -
> - /* Configuration Monitor (MON) Registers */
> - u32 gpio_inten; /* 0x830 */
> - u32 gpio_intmask;
> - u32 gpio_inttype_level;
> - u32 gpio_int_polarity;
> - u32 gpio_intstatus; /* 0x840 */
> - u32 gpio_raw_intstatus;
> - u32 _pad_0x848;
> - u32 gpio_porta_eoi;
> - u32 gpio_ext_porta; /* 0x850 */
> - u32 _pad_0x854_0x85c[3];
> - u32 gpio_1s_sync; /* 0x860 */
> - u32 _pad_0x864_0x868[2];
> - u32 gpio_ver_id_code;
> - u32 gpio_config_reg2; /* 0x870 */
> - u32 gpio_config_reg1;
> -};
> -
> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> -
> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> -
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> -
> -/* FPGA Mode */
> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> -#define FPGAMGRREGS_MODE_USERMODE 0x4
> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#include <asm/arch/fpga_manager_gen5.h>
> +#endif
>
> /* FPGA CD Ratio Value */
> #define CDRATIO_x1 0x0
> @@ -74,4 +25,12 @@ int fpgamgr_test_fpga_ready(void);
> int fpgamgr_poll_fpga_ready(void);
> int fpgamgr_get_mode(void);
>
> +#define FPGA_TIMEOUT_CNT 0x1000000
> +
> +#ifndef __ASSEMBLY__
> +
> +/* Common prototypes */
> +int fpgamgr_dclkcnt_set(unsigned long cnt);
> +
> +#endif /* __ASSEMBLY__ */
> #endif /* _FPGA_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> similarity index 57%
> copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
> copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> index a077e22..2de7a11 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> @@ -1,14 +1,38 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> */
>
> -#ifndef _FPGA_MANAGER_H_
> -#define _FPGA_MANAGER_H_
> +#ifndef _FPGA_MANAGER_GEN5_H_
> +#define _FPGA_MANAGER_GEN5_H_
>
> -#include <altera.h>
> +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> +#define FPGAMGRREGS_STAT_MSEL_LSB 3
> +
> +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
> +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
> +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
> +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
> +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
> +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> +
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
> +
> +/* FPGA Mode */
> +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> +#define FPGAMGRREGS_MODE_INITPHASE 0x3
> +#define FPGAMGRREGS_MODE_USERMODE 0x4
> +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> +
> +#ifndef __ASSEMBLY__
>
> struct socfpga_fpga_manager {
> /* FPGA Manager Module */
> @@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
> u32 gpio_config_reg1;
> };
>
> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> -
> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> -
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> -
> -/* FPGA Mode */
> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> -#define FPGAMGRREGS_MODE_USERMODE 0x4
> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> -
> -/* FPGA CD Ratio Value */
> -#define CDRATIO_x1 0x0
> -#define CDRATIO_x2 0x1
> -#define CDRATIO_x4 0x2
> -#define CDRATIO_x8 0x3
> -
> -/* SoCFPGA support functions */
> -int fpgamgr_test_fpga_ready(void);
> -int fpgamgr_poll_fpga_ready(void);
> -int fpgamgr_get_mode(void);
> +#endif /* __ASSEMBLY__ */
>
> -#endif /* _FPGA_MANAGER_H_ */
> +#endif /* _FPGA_MANAGER_GEN5_H_ */
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 4a4b237..b4a2230 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> +obj-$(CONFIG_FPGA) += fpga/
> endif
>
> ifdef CONFIG_TPL_BUILD
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 84e7605..649b6d1 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -19,4 +19,5 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> endif
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> index f1b2f2c..30ebee8 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> @@ -14,23 +14,10 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -/* Timeout count */
> -#define FPGA_TIMEOUT_CNT 0x1000000
> -
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> -/* Set CD ratio */
> -static void fpgamgr_set_cd_ratio(unsigned long ratio)
> -{
> - clrsetbits_le32(&fpgamgr_regs->ctrl,
> - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
> - (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
> -}
>
> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> +int fpgamgr_dclkcnt_set(unsigned long cnt)
> {
> unsigned long i;
>
> @@ -52,253 +39,3 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt)
>
> return -ETIMEDOUT;
> }
> -
> -/* Start the FPGA programming by initialize the FPGA Manager */
> -static int fpgamgr_program_init(void)
> -{
> - unsigned long msel, i;
> -
> - /* Get the MSEL value */
> - msel = readl(&fpgamgr_regs->stat);
> - msel &= FPGAMGRREGS_STAT_MSEL_MASK;
> - msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
> -
> - /*
> - * Set the cfg width
> - * If MSEL[3] = 1, cfg width = 32 bit
> - */
> - if (msel & 0x8) {
> - setbits_le32(&fpgamgr_regs->ctrl,
> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> -
> - /* To determine the CD ratio */
> - /* MSEL[1:0] = 0, CD Ratio = 1 */
> - if ((msel & 0x3) == 0x0)
> - fpgamgr_set_cd_ratio(CDRATIO_x1);
> - /* MSEL[1:0] = 1, CD Ratio = 4 */
> - else if ((msel & 0x3) == 0x1)
> - fpgamgr_set_cd_ratio(CDRATIO_x4);
> - /* MSEL[1:0] = 2, CD Ratio = 8 */
> - else if ((msel & 0x3) == 0x2)
> - fpgamgr_set_cd_ratio(CDRATIO_x8);
> -
> - } else { /* MSEL[3] = 0 */
> - clrbits_le32(&fpgamgr_regs->ctrl,
> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> -
> - /* To determine the CD ratio */
> - /* MSEL[1:0] = 0, CD Ratio = 1 */
> - if ((msel & 0x3) == 0x0)
> - fpgamgr_set_cd_ratio(CDRATIO_x1);
> - /* MSEL[1:0] = 1, CD Ratio = 2 */
> - else if ((msel & 0x3) == 0x1)
> - fpgamgr_set_cd_ratio(CDRATIO_x2);
> - /* MSEL[1:0] = 2, CD Ratio = 4 */
> - else if ((msel & 0x3) == 0x2)
> - fpgamgr_set_cd_ratio(CDRATIO_x4);
> - }
> -
> - /* To enable FPGA Manager configuration */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
> -
> - /* To enable FPGA Manager drive over configuration line */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
> -
> - /* Put FPGA into reset phase */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> -
> - /* (1) wait until FPGA enter reset phase */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
> - break;
> - }
> -
> - /* If not in reset state, return error */
> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
> - puts("FPGA: Could not reset\n");
> - return -1;
> - }
> -
> - /* Release FPGA from reset phase */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> -
> - /* (2) wait until FPGA enter configuration phase */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
> - break;
> - }
> -
> - /* If not in configuration state, return error */
> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
> - puts("FPGA: Could not configure\n");
> - return -2;
> - }
> -
> - /* Clear all interrupts in CB Monitor */
> - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
> -
> - /* Enable AXI configuration */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> -
> - return 0;
> -}
> -
> -/* Write the RBF data to FPGA Manager */
> -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
> -{
> - uint32_t src = (uint32_t)rbf_data;
> - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> -
> - /* Number of loops for 32-byte long copying. */
> - uint32_t loops32 = rbf_size / 32;
> - /* Number of loops for 4-byte long copying + trailing bytes */
> - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> -
> - asm volatile(
> - "1: ldmia %0!, {r0-r7}\n"
> - " stmia %1!, {r0-r7}\n"
> - " sub %1, #32\n"
> - " subs %2, #1\n"
> - " bne 1b\n"
> - " cmp %3, #0\n"
> - " beq 3f\n"
> - "2: ldr %2, [%0], #4\n"
> - " str %2, [%1]\n"
> - " subs %3, #1\n"
> - " bne 2b\n"
> - "3: nop\n"
> - : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
> - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
> -}
> -
> -/* Ensure the FPGA entering config done */
> -static int fpgamgr_program_poll_cd(void)
> -{
> - const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
> - FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
> - unsigned long reg, i;
> -
> - /* (3) wait until full config done */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - reg = readl(&fpgamgr_regs->gpio_ext_porta);
> -
> - /* Config error */
> - if (!(reg & mask)) {
> - printf("FPGA: Configuration error.\n");
> - return -3;
> - }
> -
> - /* Config done without error */
> - if (reg & mask)
> - break;
> - }
> -
> - /* Timeout happened, return error */
> - if (i == FPGA_TIMEOUT_CNT) {
> - printf("FPGA: Timeout waiting for program.\n");
> - return -4;
> - }
> -
> - /* Disable AXI configuration */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> -
> - return 0;
> -}
> -
> -/* Ensure the FPGA entering init phase */
> -static int fpgamgr_program_poll_initphase(void)
> -{
> - unsigned long i;
> -
> - /* Additional clocks for the CB to enter initialization phase */
> - if (fpgamgr_dclkcnt_set(0x4))
> - return -5;
> -
> - /* (4) wait until FPGA enter init phase or user mode */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
> - break;
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
> - break;
> - }
> -
> - /* If not in configuration state, return error */
> - if (i == FPGA_TIMEOUT_CNT)
> - return -6;
> -
> - return 0;
> -}
> -
> -/* Ensure the FPGA entering user mode */
> -static int fpgamgr_program_poll_usermode(void)
> -{
> - unsigned long i;
> -
> - /* Additional clocks for the CB to exit initialization phase */
> - if (fpgamgr_dclkcnt_set(0x5000))
> - return -7;
> -
> - /* (5) wait until FPGA enter user mode */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
> - break;
> - }
> - /* If not in configuration state, return error */
> - if (i == FPGA_TIMEOUT_CNT)
> - return -8;
> -
> - /* To release FPGA Manager drive over configuration line */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
> -
> - return 0;
> -}
> -
> -/*
> - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> -int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> -{
> - unsigned long status;
> -
> - if ((uint32_t)rbf_data & 0x3) {
> - puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
> - return -EINVAL;
> - }
> -
> - /* Prior programming the FPGA, all bridges need to be shut off */
> -
> - /* Disable all signals from hps peripheral controller to fpga */
> - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> -
> - /* Disable all signals from FPGA to HPS SDRAM */
> -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> - writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
> -
> - /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> - socfpga_bridges_reset(1);
> -
> - /* Unmap the bridges from NIC-301 */
> - writel(0x1, SOCFPGA_L3REGS_ADDRESS);
> -
> - /* Initialize the FPGA Manager */
> - status = fpgamgr_program_init();
> - if (status)
> - return status;
> -
> - /* Write the RBF data to FPGA Manager */
> - fpgamgr_program_write(rbf_data, rbf_size);
> -
> - /* Ensure the FPGA entering config done */
> - status = fpgamgr_program_poll_cd();
> - if (status)
> - return status;
> -
> - /* Ensure the FPGA entering init phase */
> - status = fpgamgr_program_poll_initphase();
> - if (status)
> - return status;
> -
> - /* Ensure the FPGA entering user mode */
> - return fpgamgr_program_poll_usermode();
> -}
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
> similarity index 92%
> copy from drivers/fpga/socfpga.c
> copy to drivers/fpga/socfpga_gen5.c
> index f1b2f2c..6992d83 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga_gen5.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> @@ -14,9 +14,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -/* Timeout count */
> -#define FPGA_TIMEOUT_CNT 0x1000000
> -
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> static struct socfpga_system_manager *sysmgr_regs =
> @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
> (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
> }
>
> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> -{
> - unsigned long i;
> -
> - /* Clear any existing done status */
> - if (readl(&fpgamgr_regs->dclkstat))
> - writel(0x1, &fpgamgr_regs->dclkstat);
> -
> - /* Write the dclkcnt */
> - writel(cnt, &fpgamgr_regs->dclkcnt);
> -
> - /* Wait till the dclkcnt done */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (!readl(&fpgamgr_regs->dclkstat))
> - continue;
> -
> - writel(0x1, &fpgamgr_regs->dclkstat);
> - return 0;
> - }
> -
> - return -ETIMEDOUT;
> -}
> -
> /* Start the FPGA programming by initialize the FPGA Manager */
> static int fpgamgr_program_init(void)
> {
> @@ -267,7 +241,6 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> }
>
> /* Prior programming the FPGA, all bridges need to be shut off */
> -
> /* Disable all signals from hps peripheral controller to fpga */
> writel(0, &sysmgr_regs->fpgaintfgrp_module);
>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-05 11:13 ` Marek Vasut
@ 2017-05-08 4:39 ` Chee, Tien Fong
2017-05-08 10:16 ` Marek Vasut
0 siblings, 1 reply; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-08 4:39 UTC (permalink / raw)
To: u-boot
On Jum, 2017-05-05 at 13:13 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Move FPGA driver which is Gen5 specific code into Gen5 files.
> > No functional change.
> It's a driver, so it should stay in drivers/ . If you need to split
> it,
> split it in drivers/fpga/ and add Kconfig option(s)
>
I am confused here, all the FPGA drivers which i split into common and
platform specific are still in the drivers/fpga/. Could you explain
more? Thanks.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > arch/arm/mach-socfpga/Makefile | 2 +-
> > arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +----
> > .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
> > drivers/Makefile | 1 +
> > drivers/fpga/Makefile | 1 +
> > drivers/fpga/socfpga.c | 267 +-------
> > ------------
> > drivers/fpga/{socfpga.c => socfpga_gen5.c} | 29 +--
> > 7 files changed, 48 insertions(+), 386 deletions(-)
> > copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> > fpga_manager_gen5.h} (57%)
> > copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (92%)
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 41b779c..286bfef 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -9,7 +9,6 @@
> >
> > obj-y += board.o
> > obj-y += clock_manager.o
> > -obj-y += fpga_manager.o
> > obj-y += misc.o
> > obj-y += reset_manager.o
> > obj-y += timer.o
> > @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
> > obj-y += scan_manager.o
> > obj-y += system_manager_gen5.o
> > obj-y += wrap_pll_config.o
> > +obj-y += fpga_manager.o
> > endif
> >
> > ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > index a077e22..69d8613 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > * All rights reserved.
> > *
> > * SPDX-License-Identifier: BSD-3-Clause
> > @@ -10,58 +10,9 @@
> >
> > #include <altera.h>
> >
> > -struct socfpga_fpga_manager {
> > - /* FPGA Manager Module */
> > - u32 stat; /* 0x00 */
> > - u32 ctrl;
> > - u32 dclkcnt;
> > - u32 dclkstat;
> > - u32 gpo; /* 0x10 */
> > - u32 gpi;
> > - u32 misci; /* 0x18 */
> > - u32 _pad_0x1c_0x82c[517];
> > -
> > - /* Configuration Monitor (MON) Registers */
> > - u32 gpio_inten; /* 0x830 */
> > - u32 gpio_intmask;
> > - u32 gpio_inttype_level;
> > - u32 gpio_int_polarity;
> > - u32 gpio_intstatus; /* 0x840 */
> > - u32 gpio_raw_intstatus;
> > - u32 _pad_0x848;
> > - u32 gpio_porta_eoi;
> > - u32 gpio_ext_porta; /* 0x850 */
> > - u32 _pad_0x854_0x85c[3];
> > - u32 gpio_1s_sync; /* 0x860 */
> > - u32 _pad_0x864_0x868[2];
> > - u32 gpio_ver_id_code;
> > - u32 gpio_config_reg2; /* 0x870 */
> > - u32 gpio_config_reg1;
> > -};
> > -
> > -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > -
> > -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> > -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> > -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> > -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> > -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> > -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > -
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> > -
> > -/* FPGA Mode */
> > -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > -#define FPGAMGRREGS_MODE_USERMODE 0x4
> > -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#include <asm/arch/fpga_manager_gen5.h>
> > +#endif
> >
> > /* FPGA CD Ratio Value */
> > #define CDRATIO_x1 0x0
> > @@ -74,4 +25,12 @@ int fpgamgr_test_fpga_ready(void);
> > int fpgamgr_poll_fpga_ready(void);
> > int fpgamgr_get_mode(void);
> >
> > +#define FPGA_TIMEOUT_CNT 0x1000000
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +/* Common prototypes */
> > +int fpgamgr_dclkcnt_set(unsigned long cnt);
> > +
> > +#endif /* __ASSEMBLY__ */
> > #endif /* _FPGA_MANAGER_H_ */
> > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > similarity index 57%
> > copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > index a077e22..2de7a11 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > @@ -1,14 +1,38 @@
> > /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > * All rights reserved.
> > *
> > * SPDX-License-Identifier: BSD-3-Clause
> > */
> >
> > -#ifndef _FPGA_MANAGER_H_
> > -#define _FPGA_MANAGER_H_
> > +#ifndef _FPGA_MANAGER_GEN5_H_
> > +#define _FPGA_MANAGER_GEN5_H_
> >
> > -#include <altera.h>
> > +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > +#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > +
> > +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
> > +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
> > +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
> > +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
> > +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
> > +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > +
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
> > +
> > +/* FPGA Mode */
> > +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > +#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > +#define FPGAMGRREGS_MODE_USERMODE 0x4
> > +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > +
> > +#ifndef __ASSEMBLY__
> >
> > struct socfpga_fpga_manager {
> > /* FPGA Manager Module */
> > @@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
> > u32 gpio_config_reg1;
> > };
> >
> > -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > -
> > -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> > -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> > -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> > -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> > -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> > -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > -
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> > -
> > -/* FPGA Mode */
> > -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > -#define FPGAMGRREGS_MODE_USERMODE 0x4
> > -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > -
> > -/* FPGA CD Ratio Value */
> > -#define CDRATIO_x1 0x0
> > -#define CDRATIO_x2 0x1
> > -#define CDRATIO_x4 0x2
> > -#define CDRATIO_x8 0x3
> > -
> > -/* SoCFPGA support functions */
> > -int fpgamgr_test_fpga_ready(void);
> > -int fpgamgr_poll_fpga_ready(void);
> > -int fpgamgr_get_mode(void);
> > +#endif /* __ASSEMBLY__ */
> >
> > -#endif /* _FPGA_MANAGER_H_ */
> > +#endif /* _FPGA_MANAGER_GEN5_H_ */
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index 4a4b237..b4a2230 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> > obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> > obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> > obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> > +obj-$(CONFIG_FPGA) += fpga/
> > endif
> >
> > ifdef CONFIG_TPL_BUILD
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 84e7605..649b6d1 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -19,4 +19,5 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> > obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> > obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> > obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> > endif
> > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > index f1b2f2c..30ebee8 100644
> > --- a/drivers/fpga/socfpga.c
> > +++ b/drivers/fpga/socfpga.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > * All rights reserved.
> > *
> > * SPDX-License-Identifier: BSD-3-Clause
> > @@ -14,23 +14,10 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -/* Timeout count */
> > -#define FPGA_TIMEOUT_CNT 0x1000000
> > -
> > static struct socfpga_fpga_manager *fpgamgr_regs =
> > (struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > -/* Set CD ratio */
> > -static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > -{
> > - clrsetbits_le32(&fpgamgr_regs->ctrl,
> > - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
> > - (ratio & 0x3) <<
> > FPGAMGRREGS_CTRL_CDRATIO_LSB);
> > -}
> >
> > -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> > +int fpgamgr_dclkcnt_set(unsigned long cnt)
> > {
> > unsigned long i;
> >
> > @@ -52,253 +39,3 @@ static int fpgamgr_dclkcnt_set(unsigned long
> > cnt)
> >
> > return -ETIMEDOUT;
> > }
> > -
> > -/* Start the FPGA programming by initialize the FPGA Manager */
> > -static int fpgamgr_program_init(void)
> > -{
> > - unsigned long msel, i;
> > -
> > - /* Get the MSEL value */
> > - msel = readl(&fpgamgr_regs->stat);
> > - msel &= FPGAMGRREGS_STAT_MSEL_MASK;
> > - msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
> > -
> > - /*
> > - * Set the cfg width
> > - * If MSEL[3] = 1, cfg width = 32 bit
> > - */
> > - if (msel & 0x8) {
> > - setbits_le32(&fpgamgr_regs->ctrl,
> > - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> > -
> > - /* To determine the CD ratio */
> > - /* MSEL[1:0] = 0, CD Ratio = 1 */
> > - if ((msel & 0x3) == 0x0)
> > - fpgamgr_set_cd_ratio(CDRATIO_x1);
> > - /* MSEL[1:0] = 1, CD Ratio = 4 */
> > - else if ((msel & 0x3) == 0x1)
> > - fpgamgr_set_cd_ratio(CDRATIO_x4);
> > - /* MSEL[1:0] = 2, CD Ratio = 8 */
> > - else if ((msel & 0x3) == 0x2)
> > - fpgamgr_set_cd_ratio(CDRATIO_x8);
> > -
> > - } else { /* MSEL[3] = 0 */
> > - clrbits_le32(&fpgamgr_regs->ctrl,
> > - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> > -
> > - /* To determine the CD ratio */
> > - /* MSEL[1:0] = 0, CD Ratio = 1 */
> > - if ((msel & 0x3) == 0x0)
> > - fpgamgr_set_cd_ratio(CDRATIO_x1);
> > - /* MSEL[1:0] = 1, CD Ratio = 2 */
> > - else if ((msel & 0x3) == 0x1)
> > - fpgamgr_set_cd_ratio(CDRATIO_x2);
> > - /* MSEL[1:0] = 2, CD Ratio = 4 */
> > - else if ((msel & 0x3) == 0x2)
> > - fpgamgr_set_cd_ratio(CDRATIO_x4);
> > - }
> > -
> > - /* To enable FPGA Manager configuration */
> > - clrbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_NCE_MASK);
> > -
> > - /* To enable FPGA Manager drive over configuration line */
> > - setbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_EN_MASK);
> > -
> > - /* Put FPGA into reset phase */
> > - setbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> > -
> > - /* (1) wait until FPGA enter reset phase */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - if (fpgamgr_get_mode() ==
> > FPGAMGRREGS_MODE_RESETPHASE)
> > - break;
> > - }
> > -
> > - /* If not in reset state, return error */
> > - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
> > - puts("FPGA: Could not reset\n");
> > - return -1;
> > - }
> > -
> > - /* Release FPGA from reset phase */
> > - clrbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> > -
> > - /* (2) wait until FPGA enter configuration phase */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - if (fpgamgr_get_mode() ==
> > FPGAMGRREGS_MODE_CFGPHASE)
> > - break;
> > - }
> > -
> > - /* If not in configuration state, return error */
> > - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
> > - puts("FPGA: Could not configure\n");
> > - return -2;
> > - }
> > -
> > - /* Clear all interrupts in CB Monitor */
> > - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
> > -
> > - /* Enable AXI configuration */
> > - setbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> > -
> > - return 0;
> > -}
> > -
> > -/* Write the RBF data to FPGA Manager */
> > -static void fpgamgr_program_write(const void *rbf_data, unsigned
> > long rbf_size)
> > -{
> > - uint32_t src = (uint32_t)rbf_data;
> > - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> > -
> > - /* Number of loops for 32-byte long copying. */
> > - uint32_t loops32 = rbf_size / 32;
> > - /* Number of loops for 4-byte long copying + trailing
> > bytes */
> > - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> > -
> > - asm volatile(
> > - "1: ldmia %0!, {r0-r7}\n"
> > - " stmia %1!, {r0-r7}\n"
> > - " sub %1, #32\n"
> > - " subs %2, #1\n"
> > - " bne 1b\n"
> > - " cmp %3, #0\n"
> > - " beq 3f\n"
> > - "2: ldr %2, [%0], #4\n
> > "
> > - " str %2, [%1]\n"
> > - " subs %3, #1\n"
> > - " bne 2b\n"
> > - "3: nop\n"
> > - : "+r"(src), "+r"(dst), "+r"(loops32),
> > "+r"(loops4) :
> > - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> > "cc");
> > -}
> > -
> > -/* Ensure the FPGA entering config done */
> > -static int fpgamgr_program_poll_cd(void)
> > -{
> > - const uint32_t mask =
> > FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
> > - FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MA
> > SK;
> > - unsigned long reg, i;
> > -
> > - /* (3) wait until full config done */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - reg = readl(&fpgamgr_regs->gpio_ext_porta);
> > -
> > - /* Config error */
> > - if (!(reg & mask)) {
> > - printf("FPGA: Configuration error.\n");
> > - return -3;
> > - }
> > -
> > - /* Config done without error */
> > - if (reg & mask)
> > - break;
> > - }
> > -
> > - /* Timeout happened, return error */
> > - if (i == FPGA_TIMEOUT_CNT) {
> > - printf("FPGA: Timeout waiting for program.\n");
> > - return -4;
> > - }
> > -
> > - /* Disable AXI configuration */
> > - clrbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> > -
> > - return 0;
> > -}
> > -
> > -/* Ensure the FPGA entering init phase */
> > -static int fpgamgr_program_poll_initphase(void)
> > -{
> > - unsigned long i;
> > -
> > - /* Additional clocks for the CB to enter initialization
> > phase */
> > - if (fpgamgr_dclkcnt_set(0x4))
> > - return -5;
> > -
> > - /* (4) wait until FPGA enter init phase or user mode */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - if (fpgamgr_get_mode() ==
> > FPGAMGRREGS_MODE_INITPHASE)
> > - break;
> > - if (fpgamgr_get_mode() ==
> > FPGAMGRREGS_MODE_USERMODE)
> > - break;
> > - }
> > -
> > - /* If not in configuration state, return error */
> > - if (i == FPGA_TIMEOUT_CNT)
> > - return -6;
> > -
> > - return 0;
> > -}
> > -
> > -/* Ensure the FPGA entering user mode */
> > -static int fpgamgr_program_poll_usermode(void)
> > -{
> > - unsigned long i;
> > -
> > - /* Additional clocks for the CB to exit initialization
> > phase */
> > - if (fpgamgr_dclkcnt_set(0x5000))
> > - return -7;
> > -
> > - /* (5) wait until FPGA enter user mode */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - if (fpgamgr_get_mode() ==
> > FPGAMGRREGS_MODE_USERMODE)
> > - break;
> > - }
> > - /* If not in configuration state, return error */
> > - if (i == FPGA_TIMEOUT_CNT)
> > - return -8;
> > -
> > - /* To release FPGA Manager drive over configuration line
> > */
> > - clrbits_le32(&fpgamgr_regs->ctrl,
> > FPGAMGRREGS_CTRL_EN_MASK);
> > -
> > - return 0;
> > -}
> > -
> > -/*
> > - * FPGA Manager to program the FPGA. This is the interface used by
> > FPGA driver.
> > - * Return 0 for sucess, non-zero for error.
> > - */
> > -int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> > rbf_size)
> > -{
> > - unsigned long status;
> > -
> > - if ((uint32_t)rbf_data & 0x3) {
> > - puts("FPGA: Unaligned data, realign to 32bit
> > boundary.\n");
> > - return -EINVAL;
> > - }
> > -
> > - /* Prior programming the FPGA, all bridges need to be shut
> > off */
> > -
> > - /* Disable all signals from hps peripheral controller to
> > fpga */
> > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > -
> > - /* Disable all signals from FPGA to HPS SDRAM */
> > -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> > - writel(0, SOCFPGA_SDR_ADDRESS +
> > SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
> > -
> > - /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > fpga2hps) */
> > - socfpga_bridges_reset(1);
> > -
> > - /* Unmap the bridges from NIC-301 */
> > - writel(0x1, SOCFPGA_L3REGS_ADDRESS);
> > -
> > - /* Initialize the FPGA Manager */
> > - status = fpgamgr_program_init();
> > - if (status)
> > - return status;
> > -
> > - /* Write the RBF data to FPGA Manager */
> > - fpgamgr_program_write(rbf_data, rbf_size);
> > -
> > - /* Ensure the FPGA entering config done */
> > - status = fpgamgr_program_poll_cd();
> > - if (status)
> > - return status;
> > -
> > - /* Ensure the FPGA entering init phase */
> > - status = fpgamgr_program_poll_initphase();
> > - if (status)
> > - return status;
> > -
> > - /* Ensure the FPGA entering user mode */
> > - return fpgamgr_program_poll_usermode();
> > -}
> > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
> > similarity index 92%
> > copy from drivers/fpga/socfpga.c
> > copy to drivers/fpga/socfpga_gen5.c
> > index f1b2f2c..6992d83 100644
> > --- a/drivers/fpga/socfpga.c
> > +++ b/drivers/fpga/socfpga_gen5.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > * All rights reserved.
> > *
> > * SPDX-License-Identifier: BSD-3-Clause
> > @@ -14,9 +14,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -/* Timeout count */
> > -#define FPGA_TIMEOUT_CNT 0x1000000
> > -
> > static struct socfpga_fpga_manager *fpgamgr_regs =
> > (struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > static struct socfpga_system_manager *sysmgr_regs =
> > @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long
> > ratio)
> > (ratio & 0x3) <<
> > FPGAMGRREGS_CTRL_CDRATIO_LSB);
> > }
> >
> > -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> > -{
> > - unsigned long i;
> > -
> > - /* Clear any existing done status */
> > - if (readl(&fpgamgr_regs->dclkstat))
> > - writel(0x1, &fpgamgr_regs->dclkstat);
> > -
> > - /* Write the dclkcnt */
> > - writel(cnt, &fpgamgr_regs->dclkcnt);
> > -
> > - /* Wait till the dclkcnt done */
> > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > - if (!readl(&fpgamgr_regs->dclkstat))
> > - continue;
> > -
> > - writel(0x1, &fpgamgr_regs->dclkstat);
> > - return 0;
> > - }
> > -
> > - return -ETIMEDOUT;
> > -}
> > -
> > /* Start the FPGA programming by initialize the FPGA Manager */
> > static int fpgamgr_program_init(void)
> > {
> > @@ -267,7 +241,6 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> > }
> >
> > /* Prior programming the FPGA, all bridges need to be shut
> > off */
> > -
> > /* Disable all signals from hps peripheral controller to
> > fpga */
> > writel(0, &sysmgr_regs->fpgaintfgrp_module);
> >
> >
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-08 4:39 ` Chee, Tien Fong
@ 2017-05-08 10:16 ` Marek Vasut
2017-05-09 4:00 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-08 10:16 UTC (permalink / raw)
To: u-boot
On 05/08/2017 06:39 AM, Chee, Tien Fong wrote:
> On Jum, 2017-05-05 at 13:13 +0200, Marek Vasut wrote:
>> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Move FPGA driver which is Gen5 specific code into Gen5 files.
>>> No functional change.
>> It's a driver, so it should stay in drivers/ . If you need to split
>> it,
>> split it in drivers/fpga/ and add Kconfig option(s)
>>
> I am confused here, all the FPGA drivers which i split into common and
> platform specific are still in the drivers/fpga/. Could you explain
> more? Thanks.
The driver code should be in drivers/fpga/ , so unless there's a good
reason, don't move any of it into arch/arm/
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>> arch/arm/mach-socfpga/Makefile | 2 +-
>>> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +----
>>> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
>>> drivers/Makefile | 1 +
>>> drivers/fpga/Makefile | 1 +
>>> drivers/fpga/socfpga.c | 267 +-------
>>> ------------
>>> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 29 +--
>>> 7 files changed, 48 insertions(+), 386 deletions(-)
>>> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
>>> fpga_manager_gen5.h} (57%)
>>> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (92%)
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
>>> socfpga/Makefile
>>> index 41b779c..286bfef 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -9,7 +9,6 @@
>>>
>>> obj-y += board.o
>>> obj-y += clock_manager.o
>>> -obj-y += fpga_manager.o
>>> obj-y += misc.o
>>> obj-y += reset_manager.o
>>> obj-y += timer.o
>>> @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
>>> obj-y += scan_manager.o
>>> obj-y += system_manager_gen5.o
>>> obj-y += wrap_pll_config.o
>>> +obj-y += fpga_manager.o
>>> endif
>>>
>>> ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> index a077e22..69d8613 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
>>> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
>>> * All rights reserved.
>>> *
>>> * SPDX-License-Identifier: BSD-3-Clause
>>> @@ -10,58 +10,9 @@
>>>
>>> #include <altera.h>
>>>
>>> -struct socfpga_fpga_manager {
>>> - /* FPGA Manager Module */
>>> - u32 stat; /* 0x00 */
>>> - u32 ctrl;
>>> - u32 dclkcnt;
>>> - u32 dclkstat;
>>> - u32 gpo; /* 0x10 */
>>> - u32 gpi;
>>> - u32 misci; /* 0x18 */
>>> - u32 _pad_0x1c_0x82c[517];
>>> -
>>> - /* Configuration Monitor (MON) Registers */
>>> - u32 gpio_inten; /* 0x830 */
>>> - u32 gpio_intmask;
>>> - u32 gpio_inttype_level;
>>> - u32 gpio_int_polarity;
>>> - u32 gpio_intstatus; /* 0x840 */
>>> - u32 gpio_raw_intstatus;
>>> - u32 _pad_0x848;
>>> - u32 gpio_porta_eoi;
>>> - u32 gpio_ext_porta; /* 0x850 */
>>> - u32 _pad_0x854_0x85c[3];
>>> - u32 gpio_1s_sync; /* 0x860 */
>>> - u32 _pad_0x864_0x868[2];
>>> - u32 gpio_ver_id_code;
>>> - u32 gpio_config_reg2; /* 0x870 */
>>> - u32 gpio_config_reg1;
>>> -};
>>> -
>>> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
>>> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
>>> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
>>> -
>>> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
>>> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
>>> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
>>> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
>>> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
>>> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
>>> -
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
>>> -
>>> -/* FPGA Mode */
>>> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
>>> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
>>> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
>>> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
>>> -#define FPGAMGRREGS_MODE_USERMODE 0x4
>>> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> +#include <asm/arch/fpga_manager_gen5.h>
>>> +#endif
>>>
>>> /* FPGA CD Ratio Value */
>>> #define CDRATIO_x1 0x0
>>> @@ -74,4 +25,12 @@ int fpgamgr_test_fpga_ready(void);
>>> int fpgamgr_poll_fpga_ready(void);
>>> int fpgamgr_get_mode(void);
>>>
>>> +#define FPGA_TIMEOUT_CNT 0x1000000
>>> +
>>> +#ifndef __ASSEMBLY__
>>> +
>>> +/* Common prototypes */
>>> +int fpgamgr_dclkcnt_set(unsigned long cnt);
>>> +
>>> +#endif /* __ASSEMBLY__ */
>>> #endif /* _FPGA_MANAGER_H_ */
>>> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
>>> similarity index 57%
>>> copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
>>> index a077e22..2de7a11 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
>>> @@ -1,14 +1,38 @@
>>> /*
>>> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
>>> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
>>> * All rights reserved.
>>> *
>>> * SPDX-License-Identifier: BSD-3-Clause
>>> */
>>>
>>> -#ifndef _FPGA_MANAGER_H_
>>> -#define _FPGA_MANAGER_H_
>>> +#ifndef _FPGA_MANAGER_GEN5_H_
>>> +#define _FPGA_MANAGER_GEN5_H_
>>>
>>> -#include <altera.h>
>>> +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
>>> +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
>>> +#define FPGAMGRREGS_STAT_MSEL_LSB 3
>>> +
>>> +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
>>> +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
>>> +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
>>> +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
>>> +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
>>> +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
>>> +
>>> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
>>> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
>>> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
>>> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
>>> +
>>> +/* FPGA Mode */
>>> +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
>>> +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
>>> +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
>>> +#define FPGAMGRREGS_MODE_INITPHASE 0x3
>>> +#define FPGAMGRREGS_MODE_USERMODE 0x4
>>> +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
>>> +
>>> +#ifndef __ASSEMBLY__
>>>
>>> struct socfpga_fpga_manager {
>>> /* FPGA Manager Module */
>>> @@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
>>> u32 gpio_config_reg1;
>>> };
>>>
>>> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
>>> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
>>> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
>>> -
>>> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
>>> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
>>> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
>>> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
>>> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
>>> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
>>> -
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
>>> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
>>> -
>>> -/* FPGA Mode */
>>> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
>>> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
>>> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
>>> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
>>> -#define FPGAMGRREGS_MODE_USERMODE 0x4
>>> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
>>> -
>>> -/* FPGA CD Ratio Value */
>>> -#define CDRATIO_x1 0x0
>>> -#define CDRATIO_x2 0x1
>>> -#define CDRATIO_x4 0x2
>>> -#define CDRATIO_x8 0x3
>>> -
>>> -/* SoCFPGA support functions */
>>> -int fpgamgr_test_fpga_ready(void);
>>> -int fpgamgr_poll_fpga_ready(void);
>>> -int fpgamgr_get_mode(void);
>>> +#endif /* __ASSEMBLY__ */
>>>
>>> -#endif /* _FPGA_MANAGER_H_ */
>>> +#endif /* _FPGA_MANAGER_GEN5_H_ */
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index 4a4b237..b4a2230 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile
>>> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
>>> obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
>>> obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
>>> obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
>>> +obj-$(CONFIG_FPGA) += fpga/
>>> endif
>>>
>>> ifdef CONFIG_TPL_BUILD
>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>>> index 84e7605..649b6d1 100644
>>> --- a/drivers/fpga/Makefile
>>> +++ b/drivers/fpga/Makefile
>>> @@ -19,4 +19,5 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
>>> obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
>>> obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
>>> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
>>> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
>>> endif
>>> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
>>> index f1b2f2c..30ebee8 100644
>>> --- a/drivers/fpga/socfpga.c
>>> +++ b/drivers/fpga/socfpga.c
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
>>> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
>>> * All rights reserved.
>>> *
>>> * SPDX-License-Identifier: BSD-3-Clause
>>> @@ -14,23 +14,10 @@
>>>
>>> DECLARE_GLOBAL_DATA_PTR;
>>>
>>> -/* Timeout count */
>>> -#define FPGA_TIMEOUT_CNT 0x1000000
>>> -
>>> static struct socfpga_fpga_manager *fpgamgr_regs =
>>> (struct socfpga_fpga_manager
>>> *)SOCFPGA_FPGAMGRREGS_ADDRESS;
>>> -static struct socfpga_system_manager *sysmgr_regs =
>>> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>> -
>>> -/* Set CD ratio */
>>> -static void fpgamgr_set_cd_ratio(unsigned long ratio)
>>> -{
>>> - clrsetbits_le32(&fpgamgr_regs->ctrl,
>>> - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
>>> - (ratio & 0x3) <<
>>> FPGAMGRREGS_CTRL_CDRATIO_LSB);
>>> -}
>>>
>>> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
>>> +int fpgamgr_dclkcnt_set(unsigned long cnt)
>>> {
>>> unsigned long i;
>>>
>>> @@ -52,253 +39,3 @@ static int fpgamgr_dclkcnt_set(unsigned long
>>> cnt)
>>>
>>> return -ETIMEDOUT;
>>> }
>>> -
>>> -/* Start the FPGA programming by initialize the FPGA Manager */
>>> -static int fpgamgr_program_init(void)
>>> -{
>>> - unsigned long msel, i;
>>> -
>>> - /* Get the MSEL value */
>>> - msel = readl(&fpgamgr_regs->stat);
>>> - msel &= FPGAMGRREGS_STAT_MSEL_MASK;
>>> - msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
>>> -
>>> - /*
>>> - * Set the cfg width
>>> - * If MSEL[3] = 1, cfg width = 32 bit
>>> - */
>>> - if (msel & 0x8) {
>>> - setbits_le32(&fpgamgr_regs->ctrl,
>>> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
>>> -
>>> - /* To determine the CD ratio */
>>> - /* MSEL[1:0] = 0, CD Ratio = 1 */
>>> - if ((msel & 0x3) == 0x0)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x1);
>>> - /* MSEL[1:0] = 1, CD Ratio = 4 */
>>> - else if ((msel & 0x3) == 0x1)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x4);
>>> - /* MSEL[1:0] = 2, CD Ratio = 8 */
>>> - else if ((msel & 0x3) == 0x2)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x8);
>>> -
>>> - } else { /* MSEL[3] = 0 */
>>> - clrbits_le32(&fpgamgr_regs->ctrl,
>>> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
>>> -
>>> - /* To determine the CD ratio */
>>> - /* MSEL[1:0] = 0, CD Ratio = 1 */
>>> - if ((msel & 0x3) == 0x0)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x1);
>>> - /* MSEL[1:0] = 1, CD Ratio = 2 */
>>> - else if ((msel & 0x3) == 0x1)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x2);
>>> - /* MSEL[1:0] = 2, CD Ratio = 4 */
>>> - else if ((msel & 0x3) == 0x2)
>>> - fpgamgr_set_cd_ratio(CDRATIO_x4);
>>> - }
>>> -
>>> - /* To enable FPGA Manager configuration */
>>> - clrbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_NCE_MASK);
>>> -
>>> - /* To enable FPGA Manager drive over configuration line */
>>> - setbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_EN_MASK);
>>> -
>>> - /* Put FPGA into reset phase */
>>> - setbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
>>> -
>>> - /* (1) wait until FPGA enter reset phase */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - if (fpgamgr_get_mode() ==
>>> FPGAMGRREGS_MODE_RESETPHASE)
>>> - break;
>>> - }
>>> -
>>> - /* If not in reset state, return error */
>>> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
>>> - puts("FPGA: Could not reset\n");
>>> - return -1;
>>> - }
>>> -
>>> - /* Release FPGA from reset phase */
>>> - clrbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
>>> -
>>> - /* (2) wait until FPGA enter configuration phase */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - if (fpgamgr_get_mode() ==
>>> FPGAMGRREGS_MODE_CFGPHASE)
>>> - break;
>>> - }
>>> -
>>> - /* If not in configuration state, return error */
>>> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
>>> - puts("FPGA: Could not configure\n");
>>> - return -2;
>>> - }
>>> -
>>> - /* Clear all interrupts in CB Monitor */
>>> - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
>>> -
>>> - /* Enable AXI configuration */
>>> - setbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_AXICFGEN_MASK);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -/* Write the RBF data to FPGA Manager */
>>> -static void fpgamgr_program_write(const void *rbf_data, unsigned
>>> long rbf_size)
>>> -{
>>> - uint32_t src = (uint32_t)rbf_data;
>>> - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
>>> -
>>> - /* Number of loops for 32-byte long copying. */
>>> - uint32_t loops32 = rbf_size / 32;
>>> - /* Number of loops for 4-byte long copying + trailing
>>> bytes */
>>> - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
>>> -
>>> - asm volatile(
>>> - "1: ldmia %0!, {r0-r7}\n"
>>> - " stmia %1!, {r0-r7}\n"
>>> - " sub %1, #32\n"
>>> - " subs %2, #1\n"
>>> - " bne 1b\n"
>>> - " cmp %3, #0\n"
>>> - " beq 3f\n"
>>> - "2: ldr %2, [%0], #4\n
>>> "
>>> - " str %2, [%1]\n"
>>> - " subs %3, #1\n"
>>> - " bne 2b\n"
>>> - "3: nop\n"
>>> - : "+r"(src), "+r"(dst), "+r"(loops32),
>>> "+r"(loops4) :
>>> - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
>>> "cc");
>>> -}
>>> -
>>> -/* Ensure the FPGA entering config done */
>>> -static int fpgamgr_program_poll_cd(void)
>>> -{
>>> - const uint32_t mask =
>>> FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
>>> - FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MA
>>> SK;
>>> - unsigned long reg, i;
>>> -
>>> - /* (3) wait until full config done */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - reg = readl(&fpgamgr_regs->gpio_ext_porta);
>>> -
>>> - /* Config error */
>>> - if (!(reg & mask)) {
>>> - printf("FPGA: Configuration error.\n");
>>> - return -3;
>>> - }
>>> -
>>> - /* Config done without error */
>>> - if (reg & mask)
>>> - break;
>>> - }
>>> -
>>> - /* Timeout happened, return error */
>>> - if (i == FPGA_TIMEOUT_CNT) {
>>> - printf("FPGA: Timeout waiting for program.\n");
>>> - return -4;
>>> - }
>>> -
>>> - /* Disable AXI configuration */
>>> - clrbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_AXICFGEN_MASK);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -/* Ensure the FPGA entering init phase */
>>> -static int fpgamgr_program_poll_initphase(void)
>>> -{
>>> - unsigned long i;
>>> -
>>> - /* Additional clocks for the CB to enter initialization
>>> phase */
>>> - if (fpgamgr_dclkcnt_set(0x4))
>>> - return -5;
>>> -
>>> - /* (4) wait until FPGA enter init phase or user mode */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - if (fpgamgr_get_mode() ==
>>> FPGAMGRREGS_MODE_INITPHASE)
>>> - break;
>>> - if (fpgamgr_get_mode() ==
>>> FPGAMGRREGS_MODE_USERMODE)
>>> - break;
>>> - }
>>> -
>>> - /* If not in configuration state, return error */
>>> - if (i == FPGA_TIMEOUT_CNT)
>>> - return -6;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -/* Ensure the FPGA entering user mode */
>>> -static int fpgamgr_program_poll_usermode(void)
>>> -{
>>> - unsigned long i;
>>> -
>>> - /* Additional clocks for the CB to exit initialization
>>> phase */
>>> - if (fpgamgr_dclkcnt_set(0x5000))
>>> - return -7;
>>> -
>>> - /* (5) wait until FPGA enter user mode */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - if (fpgamgr_get_mode() ==
>>> FPGAMGRREGS_MODE_USERMODE)
>>> - break;
>>> - }
>>> - /* If not in configuration state, return error */
>>> - if (i == FPGA_TIMEOUT_CNT)
>>> - return -8;
>>> -
>>> - /* To release FPGA Manager drive over configuration line
>>> */
>>> - clrbits_le32(&fpgamgr_regs->ctrl,
>>> FPGAMGRREGS_CTRL_EN_MASK);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -/*
>>> - * FPGA Manager to program the FPGA. This is the interface used by
>>> FPGA driver.
>>> - * Return 0 for sucess, non-zero for error.
>>> - */
>>> -int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
>>> rbf_size)
>>> -{
>>> - unsigned long status;
>>> -
>>> - if ((uint32_t)rbf_data & 0x3) {
>>> - puts("FPGA: Unaligned data, realign to 32bit
>>> boundary.\n");
>>> - return -EINVAL;
>>> - }
>>> -
>>> - /* Prior programming the FPGA, all bridges need to be shut
>>> off */
>>> -
>>> - /* Disable all signals from hps peripheral controller to
>>> fpga */
>>> - writel(0, &sysmgr_regs->fpgaintfgrp_module);
>>> -
>>> - /* Disable all signals from FPGA to HPS SDRAM */
>>> -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
>>> - writel(0, SOCFPGA_SDR_ADDRESS +
>>> SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
>>> -
>>> - /* Disable all axi bridge (hps2fpga, lwhps2fpga &
>>> fpga2hps) */
>>> - socfpga_bridges_reset(1);
>>> -
>>> - /* Unmap the bridges from NIC-301 */
>>> - writel(0x1, SOCFPGA_L3REGS_ADDRESS);
>>> -
>>> - /* Initialize the FPGA Manager */
>>> - status = fpgamgr_program_init();
>>> - if (status)
>>> - return status;
>>> -
>>> - /* Write the RBF data to FPGA Manager */
>>> - fpgamgr_program_write(rbf_data, rbf_size);
>>> -
>>> - /* Ensure the FPGA entering config done */
>>> - status = fpgamgr_program_poll_cd();
>>> - if (status)
>>> - return status;
>>> -
>>> - /* Ensure the FPGA entering init phase */
>>> - status = fpgamgr_program_poll_initphase();
>>> - if (status)
>>> - return status;
>>> -
>>> - /* Ensure the FPGA entering user mode */
>>> - return fpgamgr_program_poll_usermode();
>>> -}
>>> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
>>> similarity index 92%
>>> copy from drivers/fpga/socfpga.c
>>> copy to drivers/fpga/socfpga_gen5.c
>>> index f1b2f2c..6992d83 100644
>>> --- a/drivers/fpga/socfpga.c
>>> +++ b/drivers/fpga/socfpga_gen5.c
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
>>> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
>>> * All rights reserved.
>>> *
>>> * SPDX-License-Identifier: BSD-3-Clause
>>> @@ -14,9 +14,6 @@
>>>
>>> DECLARE_GLOBAL_DATA_PTR;
>>>
>>> -/* Timeout count */
>>> -#define FPGA_TIMEOUT_CNT 0x1000000
>>> -
>>> static struct socfpga_fpga_manager *fpgamgr_regs =
>>> (struct socfpga_fpga_manager
>>> *)SOCFPGA_FPGAMGRREGS_ADDRESS;
>>> static struct socfpga_system_manager *sysmgr_regs =
>>> @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long
>>> ratio)
>>> (ratio & 0x3) <<
>>> FPGAMGRREGS_CTRL_CDRATIO_LSB);
>>> }
>>>
>>> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
>>> -{
>>> - unsigned long i;
>>> -
>>> - /* Clear any existing done status */
>>> - if (readl(&fpgamgr_regs->dclkstat))
>>> - writel(0x1, &fpgamgr_regs->dclkstat);
>>> -
>>> - /* Write the dclkcnt */
>>> - writel(cnt, &fpgamgr_regs->dclkcnt);
>>> -
>>> - /* Wait till the dclkcnt done */
>>> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
>>> - if (!readl(&fpgamgr_regs->dclkstat))
>>> - continue;
>>> -
>>> - writel(0x1, &fpgamgr_regs->dclkstat);
>>> - return 0;
>>> - }
>>> -
>>> - return -ETIMEDOUT;
>>> -}
>>> -
>>> /* Start the FPGA programming by initialize the FPGA Manager */
>>> static int fpgamgr_program_init(void)
>>> {
>>> @@ -267,7 +241,6 @@ int socfpga_load(Altera_desc *desc, const void
>>> *rbf_data, size_t rbf_size)
>>> }
>>>
>>> /* Prior programming the FPGA, all bridges need to be shut
>>> off */
>>> -
>>> /* Disable all signals from hps peripheral controller to
>>> fpga */
>>> writel(0, &sysmgr_regs->fpgaintfgrp_module);
>>>
>>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-08 10:16 ` Marek Vasut
@ 2017-05-09 4:00 ` Chee, Tien Fong
0 siblings, 0 replies; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-09 4:00 UTC (permalink / raw)
To: u-boot
On Isn, 2017-05-08 at 12:16 +0200, Marek Vasut wrote:
> On 05/08/2017 06:39 AM, Chee, Tien Fong wrote:
> >
> > On Jum, 2017-05-05 at 13:13 +0200, Marek Vasut wrote:
> > >
> > > On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Move FPGA driver which is Gen5 specific code into Gen5 files.
> > > > No functional change.
> > > It's a driver, so it should stay in drivers/ . If you need to
> > > split
> > > it,
> > > split it in drivers/fpga/ and add Kconfig option(s)
> > >
> > I am confused here, all the FPGA drivers which i split into common
> > and
> > platform specific are still in the drivers/fpga/. Could you explain
> > more? Thanks.
> The driver code should be in drivers/fpga/ , so unless there's a good
> reason, don't move any of it into arch/arm/
>
Yeah, i agree with you. Hence, the patch 3, patch 4 and patch 5 are for
moving all fpga drivers into drivers/fpga/, and header files into
include/intel_socfpga/ .
> >
> > >
> > > >
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > > arch/arm/mach-socfpga/Makefile | 2 +-
> > > > arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +---
> > > > -
> > > > .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++-
> > > > --
> > > > drivers/Makefile | 1 +
> > > > drivers/fpga/Makefile | 1 +
> > > > drivers/fpga/socfpga.c | 267 +---
> > > > ----
> > > > ------------
> > > > drivers/fpga/{socfpga.c => socfpga_gen5.c} | 29 +--
> > > > 7 files changed, 48 insertions(+), 386 deletions(-)
> > > > copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> > > > fpga_manager_gen5.h} (57%)
> > > > copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (92%)
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > socfpga/Makefile
> > > > index 41b779c..286bfef 100644
> > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > @@ -9,7 +9,6 @@
> > > >
> > > > obj-y += board.o
> > > > obj-y += clock_manager.o
> > > > -obj-y += fpga_manager.o
> > > > obj-y += misc.o
> > > > obj-y += reset_manager.o
> > > > obj-y += timer.o
> > > > @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
> > > > obj-y += scan_manager.o
> > > > obj-y += system_manager_gen5.o
> > > > obj-y += wrap_pll_config.o
> > > > +obj-y += fpga_manager.o
> > > > endif
> > > >
> > > > ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > index a077e22..69d8613 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > @@ -1,5 +1,5 @@
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > > > * All rights reserved.
> > > > *
> > > > * SPDX-License-Identifier: BSD-3-Clause
> > > > @@ -10,58 +10,9 @@
> > > >
> > > > #include <altera.h>
> > > >
> > > > -struct socfpga_fpga_manager {
> > > > - /* FPGA Manager Module */
> > > > - u32 stat; /* 0x00 */
> > > > - u32 ctrl;
> > > > - u32 dclkcnt;
> > > > - u32 dclkstat;
> > > > - u32 gpo; /* 0x10 */
> > > > - u32 gpi;
> > > > - u32 misci; /* 0x18 */
> > > > - u32 _pad_0x1c_0x82c[517];
> > > > -
> > > > - /* Configuration Monitor (MON) Registers */
> > > > - u32 gpio_inten; /* 0x830 */
> > > > - u32 gpio_intmask;
> > > > - u32 gpio_inttype_level;
> > > > - u32 gpio_int_polarity;
> > > > - u32 gpio_intstatus; /* 0x840 */
> > > > - u32 gpio_raw_intstatus;
> > > > - u32 _pad_0x848;
> > > > - u32 gpio_porta_eoi;
> > > > - u32 gpio_ext_porta; /* 0x850 */
> > > > - u32 _pad_0x854_0x85c[3];
> > > > - u32 gpio_1s_sync; /* 0x860 */
> > > > - u32 _pad_0x864_0x868[2];
> > > > - u32 gpio_ver_id_code;
> > > > - u32 gpio_config_reg2; /* 0x870 */
> > > > - u32 gpio_config_reg1;
> > > > -};
> > > > -
> > > > -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > > > -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > > > -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > > > -
> > > > -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> > > > -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> > > > -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> > > > -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> > > > -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> > > > -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > > > -
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> > > > -
> > > > -/* FPGA Mode */
> > > > -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > > > -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > > > -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > > > -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > > > -#define FPGAMGRREGS_MODE_USERMODE 0x4
> > > > -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > +#include <asm/arch/fpga_manager_gen5.h>
> > > > +#endif
> > > >
> > > > /* FPGA CD Ratio Value */
> > > > #define CDRATIO_x1 0x0
> > > > @@ -74,4 +25,12 @@ int fpgamgr_test_fpga_ready(void);
> > > > int fpgamgr_poll_fpga_ready(void);
> > > > int fpgamgr_get_mode(void);
> > > >
> > > > +#define FPGA_TIMEOUT_CNT 0x1000000
> > > > +
> > > > +#ifndef __ASSEMBLY__
> > > > +
> > > > +/* Common prototypes */
> > > > +int fpgamgr_dclkcnt_set(unsigned long cnt);
> > > > +
> > > > +#endif /* __ASSEMBLY__ */
> > > > #endif /* _FPGA_MANAGER_H_ */
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > > > similarity index 57%
> > > > copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > > > index a077e22..2de7a11 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> > > > @@ -1,14 +1,38 @@
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > > > * All rights reserved.
> > > > *
> > > > * SPDX-License-Identifier: BSD-3-Clause
> > > > */
> > > >
> > > > -#ifndef _FPGA_MANAGER_H_
> > > > -#define _FPGA_MANAGER_H_
> > > > +#ifndef _FPGA_MANAGER_GEN5_H_
> > > > +#define _FPGA_MANAGER_GEN5_H_
> > > >
> > > > -#include <altera.h>
> > > > +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > > > +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > > > +#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > > > +
> > > > +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
> > > > +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
> > > > +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
> > > > +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
> > > > +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
> > > > +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > > > +
> > > > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
> > > > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
> > > > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
> > > > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
> > > > +
> > > > +/* FPGA Mode */
> > > > +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > > > +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > > > +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > > > +#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > > > +#define FPGAMGRREGS_MODE_USERMODE 0x4
> > > > +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > > > +
> > > > +#ifndef __ASSEMBLY__
> > > >
> > > > struct socfpga_fpga_manager {
> > > > /* FPGA Manager Module */
> > > > @@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
> > > > u32 gpio_config_reg1;
> > > > };
> > > >
> > > > -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > > > -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > > > -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > > > -
> > > > -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> > > > -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> > > > -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> > > > -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> > > > -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> > > > -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > > > -
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> > > > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> > > > -
> > > > -/* FPGA Mode */
> > > > -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > > > -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > > > -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > > > -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > > > -#define FPGAMGRREGS_MODE_USERMODE 0x4
> > > > -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > > > -
> > > > -/* FPGA CD Ratio Value */
> > > > -#define CDRATIO_x1 0x0
> > > > -#define CDRATIO_x2 0x1
> > > > -#define CDRATIO_x4 0x2
> > > > -#define CDRATIO_x8 0x3
> > > > -
> > > > -/* SoCFPGA support functions */
> > > > -int fpgamgr_test_fpga_ready(void);
> > > > -int fpgamgr_poll_fpga_ready(void);
> > > > -int fpgamgr_get_mode(void);
> > > > +#endif /* __ASSEMBLY__ */
> > > >
> > > > -#endif /* _FPGA_MANAGER_H_ */
> > > > +#endif /* _FPGA_MANAGER_GEN5_H_ */
> > > > diff --git a/drivers/Makefile b/drivers/Makefile
> > > > index 4a4b237..b4a2230 100644
> > > > --- a/drivers/Makefile
> > > > +++ b/drivers/Makefile
> > > > @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> > > > obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> > > > obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> > > > obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> > > > +obj-$(CONFIG_FPGA) += fpga/
> > > > endif
> > > >
> > > > ifdef CONFIG_TPL_BUILD
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > index 84e7605..649b6d1 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -19,4 +19,5 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> > > > obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> > > > obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> > > > obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > > > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> > > > endif
> > > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > > > index f1b2f2c..30ebee8 100644
> > > > --- a/drivers/fpga/socfpga.c
> > > > +++ b/drivers/fpga/socfpga.c
> > > > @@ -1,5 +1,5 @@
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > > > * All rights reserved.
> > > > *
> > > > * SPDX-License-Identifier: BSD-3-Clause
> > > > @@ -14,23 +14,10 @@
> > > >
> > > > DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > -/* Timeout count */
> > > > -#define FPGA_TIMEOUT_CNT 0x1000000
> > > > -
> > > > static struct socfpga_fpga_manager *fpgamgr_regs =
> > > > (struct socfpga_fpga_manager
> > > > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > - (struct socfpga_system_manager
> > > > *)SOCFPGA_SYSMGR_ADDRESS;
> > > > -
> > > > -/* Set CD ratio */
> > > > -static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > > > -{
> > > > - clrsetbits_le32(&fpgamgr_regs->ctrl,
> > > > - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
> > > > - (ratio & 0x3) <<
> > > > FPGAMGRREGS_CTRL_CDRATIO_LSB);
> > > > -}
> > > >
> > > > -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> > > > +int fpgamgr_dclkcnt_set(unsigned long cnt)
> > > > {
> > > > unsigned long i;
> > > >
> > > > @@ -52,253 +39,3 @@ static int fpgamgr_dclkcnt_set(unsigned
> > > > long
> > > > cnt)
> > > >
> > > > return -ETIMEDOUT;
> > > > }
> > > > -
> > > > -/* Start the FPGA programming by initialize the FPGA Manager
> > > > */
> > > > -static int fpgamgr_program_init(void)
> > > > -{
> > > > - unsigned long msel, i;
> > > > -
> > > > - /* Get the MSEL value */
> > > > - msel = readl(&fpgamgr_regs->stat);
> > > > - msel &= FPGAMGRREGS_STAT_MSEL_MASK;
> > > > - msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
> > > > -
> > > > - /*
> > > > - * Set the cfg width
> > > > - * If MSEL[3] = 1, cfg width = 32 bit
> > > > - */
> > > > - if (msel & 0x8) {
> > > > - setbits_le32(&fpgamgr_regs->ctrl,
> > > > - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> > > > -
> > > > - /* To determine the CD ratio */
> > > > - /* MSEL[1:0] = 0, CD Ratio = 1 */
> > > > - if ((msel & 0x3) == 0x0)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x1);
> > > > - /* MSEL[1:0] = 1, CD Ratio = 4 */
> > > > - else if ((msel & 0x3) == 0x1)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x4);
> > > > - /* MSEL[1:0] = 2, CD Ratio = 8 */
> > > > - else if ((msel & 0x3) == 0x2)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x8);
> > > > -
> > > > - } else { /* MSEL[3] = 0 */
> > > > - clrbits_le32(&fpgamgr_regs->ctrl,
> > > > - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> > > > -
> > > > - /* To determine the CD ratio */
> > > > - /* MSEL[1:0] = 0, CD Ratio = 1 */
> > > > - if ((msel & 0x3) == 0x0)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x1);
> > > > - /* MSEL[1:0] = 1, CD Ratio = 2 */
> > > > - else if ((msel & 0x3) == 0x1)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x2);
> > > > - /* MSEL[1:0] = 2, CD Ratio = 4 */
> > > > - else if ((msel & 0x3) == 0x2)
> > > > - fpgamgr_set_cd_ratio(CDRATIO_x4);
> > > > - }
> > > > -
> > > > - /* To enable FPGA Manager configuration */
> > > > - clrbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_NCE_MASK);
> > > > -
> > > > - /* To enable FPGA Manager drive over configuration
> > > > line */
> > > > - setbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_EN_MASK);
> > > > -
> > > > - /* Put FPGA into reset phase */
> > > > - setbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> > > > -
> > > > - /* (1) wait until FPGA enter reset phase */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - if (fpgamgr_get_mode() ==
> > > > FPGAMGRREGS_MODE_RESETPHASE)
> > > > - break;
> > > > - }
> > > > -
> > > > - /* If not in reset state, return error */
> > > > - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE)
> > > > {
> > > > - puts("FPGA: Could not reset\n");
> > > > - return -1;
> > > > - }
> > > > -
> > > > - /* Release FPGA from reset phase */
> > > > - clrbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> > > > -
> > > > - /* (2) wait until FPGA enter configuration phase */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - if (fpgamgr_get_mode() ==
> > > > FPGAMGRREGS_MODE_CFGPHASE)
> > > > - break;
> > > > - }
> > > > -
> > > > - /* If not in configuration state, return error */
> > > > - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
> > > > - puts("FPGA: Could not configure\n");
> > > > - return -2;
> > > > - }
> > > > -
> > > > - /* Clear all interrupts in CB Monitor */
> > > > - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
> > > > -
> > > > - /* Enable AXI configuration */
> > > > - setbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -/* Write the RBF data to FPGA Manager */
> > > > -static void fpgamgr_program_write(const void *rbf_data,
> > > > unsigned
> > > > long rbf_size)
> > > > -{
> > > > - uint32_t src = (uint32_t)rbf_data;
> > > > - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> > > > -
> > > > - /* Number of loops for 32-byte long copying. */
> > > > - uint32_t loops32 = rbf_size / 32;
> > > > - /* Number of loops for 4-byte long copying + trailing
> > > > bytes */
> > > > - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> > > > -
> > > > - asm volatile(
> > > > - "1: ldmia %0!, {r0-r7}\n"
> > > > - " stmia %1!, {r0-r7}\n"
> > > > - " sub %1, #32\n"
> > > > - " subs %2, #1\n"
> > > > - " bne 1b\n"
> > > > - " cmp %3, #0\n"
> > > > - " beq 3f\n"
> > > > - "2: ldr %2, [%0],
> > > > #4\n
> > > > "
> > > > - " str %2, [%1]\n"
> > > > - " subs %3, #1\n"
> > > > - " bne 2b\n"
> > > > - "3: nop\n"
> > > > - : "+r"(src), "+r"(dst), "+r"(loops32),
> > > > "+r"(loops4) :
> > > > - : "r0", "r1", "r2", "r3", "r4", "r5", "r6",
> > > > "r7",
> > > > "cc");
> > > > -}
> > > > -
> > > > -/* Ensure the FPGA entering config done */
> > > > -static int fpgamgr_program_poll_cd(void)
> > > > -{
> > > > - const uint32_t mask =
> > > > FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
> > > > - FPGAMGRREGS_MON_GPIO_EXT_PORTA_C
> > > > D_MA
> > > > SK;
> > > > - unsigned long reg, i;
> > > > -
> > > > - /* (3) wait until full config done */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - reg = readl(&fpgamgr_regs->gpio_ext_porta);
> > > > -
> > > > - /* Config error */
> > > > - if (!(reg & mask)) {
> > > > - printf("FPGA: Configuration
> > > > error.\n");
> > > > - return -3;
> > > > - }
> > > > -
> > > > - /* Config done without error */
> > > > - if (reg & mask)
> > > > - break;
> > > > - }
> > > > -
> > > > - /* Timeout happened, return error */
> > > > - if (i == FPGA_TIMEOUT_CNT) {
> > > > - printf("FPGA: Timeout waiting for
> > > > program.\n");
> > > > - return -4;
> > > > - }
> > > > -
> > > > - /* Disable AXI configuration */
> > > > - clrbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -/* Ensure the FPGA entering init phase */
> > > > -static int fpgamgr_program_poll_initphase(void)
> > > > -{
> > > > - unsigned long i;
> > > > -
> > > > - /* Additional clocks for the CB to enter
> > > > initialization
> > > > phase */
> > > > - if (fpgamgr_dclkcnt_set(0x4))
> > > > - return -5;
> > > > -
> > > > - /* (4) wait until FPGA enter init phase or user mode
> > > > */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - if (fpgamgr_get_mode() ==
> > > > FPGAMGRREGS_MODE_INITPHASE)
> > > > - break;
> > > > - if (fpgamgr_get_mode() ==
> > > > FPGAMGRREGS_MODE_USERMODE)
> > > > - break;
> > > > - }
> > > > -
> > > > - /* If not in configuration state, return error */
> > > > - if (i == FPGA_TIMEOUT_CNT)
> > > > - return -6;
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -/* Ensure the FPGA entering user mode */
> > > > -static int fpgamgr_program_poll_usermode(void)
> > > > -{
> > > > - unsigned long i;
> > > > -
> > > > - /* Additional clocks for the CB to exit initialization
> > > > phase */
> > > > - if (fpgamgr_dclkcnt_set(0x5000))
> > > > - return -7;
> > > > -
> > > > - /* (5) wait until FPGA enter user mode */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - if (fpgamgr_get_mode() ==
> > > > FPGAMGRREGS_MODE_USERMODE)
> > > > - break;
> > > > - }
> > > > - /* If not in configuration state, return error */
> > > > - if (i == FPGA_TIMEOUT_CNT)
> > > > - return -8;
> > > > -
> > > > - /* To release FPGA Manager drive over configuration
> > > > line
> > > > */
> > > > - clrbits_le32(&fpgamgr_regs->ctrl,
> > > > FPGAMGRREGS_CTRL_EN_MASK);
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -/*
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > -int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > size_t
> > > > rbf_size)
> > > > -{
> > > > - unsigned long status;
> > > > -
> > > > - if ((uint32_t)rbf_data & 0x3) {
> > > > - puts("FPGA: Unaligned data, realign to 32bit
> > > > boundary.\n");
> > > > - return -EINVAL;
> > > > - }
> > > > -
> > > > - /* Prior programming the FPGA, all bridges need to be
> > > > shut
> > > > off */
> > > > -
> > > > - /* Disable all signals from hps peripheral controller
> > > > to
> > > > fpga */
> > > > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > > > -
> > > > - /* Disable all signals from FPGA to HPS SDRAM */
> > > > -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> > > > - writel(0, SOCFPGA_SDR_ADDRESS +
> > > > SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
> > > > -
> > > > - /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > > fpga2hps) */
> > > > - socfpga_bridges_reset(1);
> > > > -
> > > > - /* Unmap the bridges from NIC-301 */
> > > > - writel(0x1, SOCFPGA_L3REGS_ADDRESS);
> > > > -
> > > > - /* Initialize the FPGA Manager */
> > > > - status = fpgamgr_program_init();
> > > > - if (status)
> > > > - return status;
> > > > -
> > > > - /* Write the RBF data to FPGA Manager */
> > > > - fpgamgr_program_write(rbf_data, rbf_size);
> > > > -
> > > > - /* Ensure the FPGA entering config done */
> > > > - status = fpgamgr_program_poll_cd();
> > > > - if (status)
> > > > - return status;
> > > > -
> > > > - /* Ensure the FPGA entering init phase */
> > > > - status = fpgamgr_program_poll_initphase();
> > > > - if (status)
> > > > - return status;
> > > > -
> > > > - /* Ensure the FPGA entering user mode */
> > > > - return fpgamgr_program_poll_usermode();
> > > > -}
> > > > diff --git a/drivers/fpga/socfpga.c
> > > > b/drivers/fpga/socfpga_gen5.c
> > > > similarity index 92%
> > > > copy from drivers/fpga/socfpga.c
> > > > copy to drivers/fpga/socfpga_gen5.c
> > > > index f1b2f2c..6992d83 100644
> > > > --- a/drivers/fpga/socfpga.c
> > > > +++ b/drivers/fpga/socfpga_gen5.c
> > > > @@ -1,5 +1,5 @@
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > > > * All rights reserved.
> > > > *
> > > > * SPDX-License-Identifier: BSD-3-Clause
> > > > @@ -14,9 +14,6 @@
> > > >
> > > > DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > -/* Timeout count */
> > > > -#define FPGA_TIMEOUT_CNT 0x1000000
> > > > -
> > > > static struct socfpga_fpga_manager *fpgamgr_regs =
> > > > (struct socfpga_fpga_manager
> > > > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > static struct socfpga_system_manager *sysmgr_regs =
> > > > @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned
> > > > long
> > > > ratio)
> > > > (ratio & 0x3) <<
> > > > FPGAMGRREGS_CTRL_CDRATIO_LSB);
> > > > }
> > > >
> > > > -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> > > > -{
> > > > - unsigned long i;
> > > > -
> > > > - /* Clear any existing done status */
> > > > - if (readl(&fpgamgr_regs->dclkstat))
> > > > - writel(0x1, &fpgamgr_regs->dclkstat);
> > > > -
> > > > - /* Write the dclkcnt */
> > > > - writel(cnt, &fpgamgr_regs->dclkcnt);
> > > > -
> > > > - /* Wait till the dclkcnt done */
> > > > - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > > > - if (!readl(&fpgamgr_regs->dclkstat))
> > > > - continue;
> > > > -
> > > > - writel(0x1, &fpgamgr_regs->dclkstat);
> > > > - return 0;
> > > > - }
> > > > -
> > > > - return -ETIMEDOUT;
> > > > -}
> > > > -
> > > > /* Start the FPGA programming by initialize the FPGA Manager
> > > > */
> > > > static int fpgamgr_program_init(void)
> > > > {
> > > > @@ -267,7 +241,6 @@ int socfpga_load(Altera_desc *desc, const
> > > > void
> > > > *rbf_data, size_t rbf_size)
> > > > }
> > > >
> > > > /* Prior programming the FPGA, all bridges need to be
> > > > shut
> > > > off */
> > > > -
> > > > /* Disable all signals from hps peripheral controller
> > > > to
> > > > fpga */
> > > > writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > > >
> > > >
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 4/7] arm: socfpga: Move FPGA manager driver to FPGA driver
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (2 preceding siblings ...)
2017-05-05 10:26 ` [U-Boot] [PATCH 3/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 5/7] arm: socfpga: Move the FPGA driver header from arch to include directory tien.fong.chee at intel.com
` (2 subsequent siblings)
6 siblings, 0 replies; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move FPGA manager driver which is Gen5 specific code into FPGA driver.
No functional change.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 -
arch/arm/mach-socfpga/fpga_manager.c | 78 ----------------------------------
drivers/fpga/socfpga_gen5.c | 54 +++++++++++++++++++++++
3 files changed, 54 insertions(+), 79 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..824cd8e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -20,7 +20,6 @@ obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
-obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
deleted file mode 100644
index f909573..0000000
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- * All rights reserved.
- *
- * This file contains only support functions used also by the SoCFPGA
- * platform code, the real meat is located in drivers/fpga/socfpga.c .
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/fpga_manager.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
-static struct socfpga_fpga_manager *fpgamgr_regs =
- (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-
-/* Check whether FPGA Init_Done signal is high */
-static int is_fpgamgr_initdone_high(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->gpio_ext_porta);
- return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
-}
-
-/* Get the FPGA mode */
-int fpgamgr_get_mode(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->stat);
- return val & FPGAMGRREGS_STAT_MODE_MASK;
-}
-
-/* Check whether FPGA is ready to be accessed */
-int fpgamgr_test_fpga_ready(void)
-{
- /* Check for init done signal */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- /* Check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
- return 0;
-
- return 1;
-}
-
-/* Poll until FPGA is ready to be accessed or timeout occurred */
-int fpgamgr_poll_fpga_ready(void)
-{
- unsigned long i;
-
- /* If FPGA is blank, wait till WD invoke warm reset */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- /* check for init done signal */
- if (!is_fpgamgr_initdone_high())
- continue;
- /* check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- continue;
- return 1;
- }
-
- return 0;
-}
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 6992d83..892a8e4 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -19,6 +19,60 @@ static struct socfpga_fpga_manager *fpgamgr_regs =
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->gpio_ext_porta);
+ return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->stat);
+ return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+ /* Check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ /* Check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ /* check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ return 1;
+ }
+
+ return 0;
+}
+
/* Set CD ratio */
static void fpgamgr_set_cd_ratio(unsigned long ratio)
{
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 5/7] arm: socfpga: Move the FPGA driver header from arch to include directory
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (3 preceding siblings ...)
2017-05-05 10:26 ` [U-Boot] [PATCH 4/7] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver tien.fong.chee at intel.com
2017-05-05 10:26 ` [U-Boot] [PATCH 7/7] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
6 siblings, 0 replies; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move FPGA driver header to include directory which would be shared
between arch platform drivers and FPGA drivers.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +-
arch/arm/mach-socfpga/system_manager_gen5.c | 2 +-
drivers/ddr/altera/sdram.c | 7 ++-
drivers/fpga/socfpga.c | 2 +-
drivers/fpga/socfpga_gen5.c | 2 +-
include/intel_socfpga/fpga_manager.h | 36 +++++++++++++
include/intel_socfpga/fpga_manager_gen5.h | 68 +++++++++++++++++++++++++
8 files changed, 115 insertions(+), 9 deletions(-)
create mode 100644 include/intel_socfpga/fpga_manager.h
create mode 100644 include/intel_socfpga/fpga_manager_gen5.h
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 66f1ec2..bfc375e 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -5,13 +5,13 @@
*/
#include <asm/io.h>
-#include <asm/arch/fpga_manager.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <intel_socfpga/fpga_manager.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index aa88adb..3d76913 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -1,13 +1,12 @@
/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/fpga_manager.h>
+#include <intel_socfpga/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
index 3588a57..a32250b 100644
--- a/arch/arm/mach-socfpga/system_manager_gen5.c
+++ b/arch/arm/mach-socfpga/system_manager_gen5.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
-#include <asm/arch/fpga_manager.h>
+#include <intel_socfpga/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index e74c5b0..22dba3c 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -1,17 +1,20 @@
/*
- * Copyright Altera Corporation (C) 2014-2015
+ * Copyright Altera Corporation (C) 2014-2017
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <errno.h>
#include <div64.h>
#include <watchdog.h>
-#include <asm/arch/fpga_manager.h>
+#include <intel_socfpga/fpga_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+
+
DECLARE_GLOBAL_DATA_PTR;
struct sdram_prot_rule {
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 30ebee8..c37e7cf 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <linux/errno.h>
-#include <asm/arch/fpga_manager.h>
+#include <intel_socfpga/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 892a8e4..3348475 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <linux/errno.h>
-#include <asm/arch/fpga_manager.h>
+#include <intel_socfpga/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
diff --git a/include/intel_socfpga/fpga_manager.h b/include/intel_socfpga/fpga_manager.h
new file mode 100644
index 0000000..8dbf369
--- /dev/null
+++ b/include/intel_socfpga/fpga_manager.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_H_
+#define _FPGA_MANAGER_H_
+
+#include <altera.h>
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <intel_socfpga/fpga_manager_gen5.h>
+#endif
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1 0x0
+#define CDRATIO_x2 0x1
+#define CDRATIO_x4 0x2
+#define CDRATIO_x8 0x3
+
+/* SoCFPGA support functions */
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_poll_fpga_ready(void);
+int fpgamgr_get_mode(void);
+
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _FPGA_MANAGER_H_ */
diff --git a/include/intel_socfpga/fpga_manager_gen5.h b/include/intel_socfpga/fpga_manager_gen5.h
new file mode 100644
index 0000000..2de7a11
--- /dev/null
+++ b/include/intel_socfpga/fpga_manager_gen5.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
+
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ /* FPGA Manager Module */
+ u32 stat; /* 0x00 */
+ u32 ctrl;
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo; /* 0x10 */
+ u32 gpi;
+ u32 misci; /* 0x18 */
+ u32 _pad_0x1c_0x82c[517];
+
+ /* Configuration Monitor (MON) Registers */
+ u32 gpio_inten; /* 0x830 */
+ u32 gpio_intmask;
+ u32 gpio_inttype_level;
+ u32 gpio_int_polarity;
+ u32 gpio_intstatus; /* 0x840 */
+ u32 gpio_raw_intstatus;
+ u32 _pad_0x848;
+ u32 gpio_porta_eoi;
+ u32 gpio_ext_porta; /* 0x850 */
+ u32 _pad_0x854_0x85c[3];
+ u32 gpio_1s_sync; /* 0x860 */
+ u32 _pad_0x864_0x868[2];
+ u32 gpio_ver_id_code;
+ u32 gpio_config_reg2; /* 0x870 */
+ u32 gpio_config_reg1;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_GEN5_H_ */
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (4 preceding siblings ...)
2017-05-05 10:26 ` [U-Boot] [PATCH 5/7] arm: socfpga: Move the FPGA driver header from arch to include directory tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
2017-05-05 11:14 ` Marek Vasut
2017-05-05 10:26 ` [U-Boot] [PATCH 7/7] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
6 siblings, 1 reply; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Adding the Arria10 FPGA manager program assembly driver which can be used
to feed bitstream into FPGA manager for configuring FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/lowlevel_init.S | 48 +++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 824cd8e..8b86dc7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -24,6 +24,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += clock_manager_arria10.o
+obj-y += lowlevel_init.o
obj-y += misc_arria10.o
obj-y += pinmux_arria10.o
obj-y += reset_manager_arria10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
new file mode 100644
index 0000000..79e9d07
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * Write RBF data in burst form to FPGA Manager
+ * [r0] RBF binary source address
+ * [r1] FPGA Manager data address
+ * [r2] RBF data length
+ */
+
+ENTRY(fpgamgr_axi_write)
+ PUSH {r4-r11, lr} /* save registers per AAPCS */
+
+write_burst:
+ cmp r2,#32
+ beq write_burst_cont
+ bls write_word
+write_burst_cont:
+ ldmia r0!, {r4-r11}
+ stmia r1, {r4-r11}
+ subs r2, r2, #32
+ b write_burst
+
+write_word:
+ cmp r2,#4
+ beq write_word_cont
+ bls write_byte
+write_word_cont:
+ ldmia r0!, {r4}
+ stmia r1, {r4}
+ subs r2, r2, #4
+ b write_word
+
+write_byte:
+ cmp r2,#0
+ beq write_end
+ ldr r3, [r0]
+ str r3, [r1]
+write_end:
+ POP {r4-r11, pc}
+ENDPROC(fpgamgr_axi_write)
--
1.7.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver
2017-05-05 10:26 ` [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver tien.fong.chee at intel.com
@ 2017-05-05 11:14 ` Marek Vasut
2017-05-08 4:03 ` Chee, Tien Fong
0 siblings, 1 reply; 28+ messages in thread
From: Marek Vasut @ 2017-05-05 11:14 UTC (permalink / raw)
To: u-boot
On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Adding the Arria10 FPGA manager program assembly driver which can be used
> to feed bitstream into FPGA manager for configuring FPGA.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> arch/arm/mach-socfpga/lowlevel_init.S | 48 +++++++++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 824cd8e..8b86dc7 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -24,6 +24,7 @@ endif
>
> ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> obj-y += clock_manager_arria10.o
> +obj-y += lowlevel_init.o
> obj-y += misc_arria10.o
> obj-y += pinmux_arria10.o
> obj-y += reset_manager_arria10.o
> diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
> new file mode 100644
> index 0000000..79e9d07
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/lowlevel_init.S
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <linux/linkage.h>
> +
> +/*
> + * Write RBF data in burst form to FPGA Manager
> + * [r0] RBF binary source address
> + * [r1] FPGA Manager data address
> + * [r2] RBF data length
> + */
We do the same for Gen5 in C code with a bit of assembly, so do the same.
> +ENTRY(fpgamgr_axi_write)
> + PUSH {r4-r11, lr} /* save registers per AAPCS */
> +
> +write_burst:
> + cmp r2,#32
> + beq write_burst_cont
> + bls write_word
> +write_burst_cont:
> + ldmia r0!, {r4-r11}
> + stmia r1, {r4-r11}
> + subs r2, r2, #32
> + b write_burst
> +
> +write_word:
> + cmp r2,#4
> + beq write_word_cont
> + bls write_byte
> +write_word_cont:
> + ldmia r0!, {r4}
> + stmia r1, {r4}
> + subs r2, r2, #4
> + b write_word
> +
> +write_byte:
> + cmp r2,#0
> + beq write_end
> + ldr r3, [r0]
> + str r3, [r1]
> +write_end:
> + POP {r4-r11, pc}
> +ENDPROC(fpgamgr_axi_write)
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver
2017-05-05 11:14 ` Marek Vasut
@ 2017-05-08 4:03 ` Chee, Tien Fong
0 siblings, 0 replies; 28+ messages in thread
From: Chee, Tien Fong @ 2017-05-08 4:03 UTC (permalink / raw)
To: u-boot
On Jum, 2017-05-05 at 13:14 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Adding the Arria10 FPGA manager program assembly driver which can
> > be used
> > to feed bitstream into FPGA manager for configuring FPGA.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > arch/arm/mach-socfpga/Makefile | 1 +
> > arch/arm/mach-socfpga/lowlevel_init.S | 48
> > +++++++++++++++++++++++++++++++++
> > 2 files changed, 49 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 824cd8e..8b86dc7 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -24,6 +24,7 @@ endif
> >
> > ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> > obj-y += clock_manager_arria10.o
> > +obj-y += lowlevel_init.o
> > obj-y += misc_arria10.o
> > obj-y += pinmux_arria10.o
> > obj-y += reset_manager_arria10.o
> > diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-
> > socfpga/lowlevel_init.S
> > new file mode 100644
> > index 0000000..79e9d07
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/lowlevel_init.S
> > @@ -0,0 +1,48 @@
> > +/*
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include <asm-offsets.h>
> > +#include <config.h>
> > +#include <linux/linkage.h>
> > +
> > +/*
> > + * Write RBF data in burst form to FPGA Manager
> > + * [r0] RBF binary source address
> > + * [r1] FPGA Manager data address
> > + * [r2] RBF data length
> > + */
> We do the same for Gen5 in C code with a bit of assembly, so do the
> same.
>
Okay, i just saw it, thanks for pointing out.
> >
> > +ENTRY(fpgamgr_axi_write)
> > + PUSH {r4-r11, lr} /* save registers per
> > AAPCS */
> > +
> > +write_burst:
> > + cmp r2,#32
> > + beq write_burst_cont
> > + bls write_word
> > +write_burst_cont:
> > + ldmia r0!, {r4-r11}
> > + stmia r1, {r4-r11}
> > + subs r2, r2, #32
> > + b write_burst
> > +
> > +write_word:
> > + cmp r2,#4
> > + beq write_word_cont
> > + bls write_byte
> > +write_word_cont:
> > + ldmia r0!, {r4}
> > + stmia r1, {r4}
> > + subs r2, r2, #4
> > + b write_word
> > +
> > +write_byte:
> > + cmp r2,#0
> > + beq write_end
> > + ldr r3, [r0]
> > + str r3, [r1]
> > +write_end:
> > + POP {r4-r11, pc}
> > +ENDPROC(fpgamgr_axi_write)
> >
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 7/7] arm: socfpga: Add FPGA driver support for Arria 10
2017-05-05 10:26 [U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (5 preceding siblings ...)
2017-05-05 10:26 ` [U-Boot] [PATCH 6/7] arm: socfpga: Add Arria10 FPGA manager program assembly driver tien.fong.chee at intel.com
@ 2017-05-05 10:26 ` tien.fong.chee at intel.com
6 siblings, 0 replies; 28+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-05 10:26 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
drivers/fpga/Kconfig | 2 +-
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga_arria10.c | 490 ++++++++++++++++++++++++++
include/intel_socfpga/fpga_manager.h | 2 +
include/intel_socfpga/fpga_manager_arria10.h | 107 ++++++
5 files changed, 601 insertions(+), 1 deletions(-)
create mode 100644 drivers/fpga/socfpga_arria10.c
create mode 100644 include/intel_socfpga/fpga_manager_arria10.h
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index fc4ea0d..ed519d2 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -7,7 +7,7 @@ config FPGA
config FPGA_ALTERA
bool "Enable Altera FPGA drivers"
- default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
+ default y if (TARGET_SOCFPGA_GEN5 && CMD_FPGA) || TARGET_SOCFPGA_ARRIA10
select FPGA
help
Default Y here to enable the Altera FPGA driver
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 649b6d1..ac23996 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
new file mode 100644
index 0000000..8831183
--- /dev/null
+++ b/drivers/fpga/socfpga_arria10.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <intel_socfpga/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32 1
+#define MIN_BITSTREAM_SIZECHECK 230
+#define ENCRYPTION_OFFSET 69
+#define COMPRESSION_OFFSET 229
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+ (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+ u32 reg;
+
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+ return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+ if (width)
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+ else
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+/* Check whether FPGA Init_Done signal is high */
+int is_fpgamgr_initdone_high(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
+}
+
+int is_fpgamgr_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+ u32 sync_data = 0xffffffff;
+ u32 i = 0;
+ unsigned start = get_timer(0);
+ unsigned long cd_ratio;
+
+ /* Getting existing CDRATIO */
+ cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+ /* Using CDRATIO_X1 for better compatibility */
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+ while (!(is_fpgamgr_early_user_mode())) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ udelay(FPGA_TIMEOUT_MSEC);
+ i++;
+ }
+
+ debug("Additional %i sync word needed\n", i);
+
+ /* restoring original CDRATIO */
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+ unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+ /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
+ * timeout at 1000ms
+ */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ mask,
+ false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+ /* Poll until f2s to specific value, timeout at 1000ms */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+ value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration mode */
+static int fpgamgr_verify_msel(void)
+{
+ unsigned int msel = fpgamgr_get_msel();
+
+ if ((msel != 0) && (msel != 1)) {
+ printf("Fail: read msel=%d\n", msel);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+ u32 rbf_size)
+{
+ unsigned int cd_ratio;
+ bool encrypt, compress;
+
+ /*
+ * According to the bitstream specification,
+ * both encryption and compression status are
+ * in location before offset 230 of the buffer.
+ */
+ if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+ return -EINVAL;
+
+ encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+ encrypt = encrypt != 0;
+
+ compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+ compress = !compress;
+
+ debug("header word %d = %08x\n", 69, rbf_data[69]);
+ debug("header word %d = %08x\n", 229, rbf_data[229]);
+ debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+
+ /*
+ * from the register map description of cdratio in imgcfg_ctrl_02:
+ * Normal Configuration : 32bit Passive Parallel
+ * Partial Reconfiguration : 16bit Passive Parallel
+ */
+
+ /*
+ * cd ratio is dependent on cfg width and whether the bitstream
+ * is encrypted and/or compressed.
+ *
+ * | width | encr. | compr. | cd ratio |
+ * | 16 | 0 | 0 | 1 |
+ * | 16 | 0 | 1 | 4 |
+ * | 16 | 1 | 0 | 2 |
+ * | 16 | 1 | 1 | 4 |
+ * | 32 | 0 | 0 | 1 |
+ * | 32 | 0 | 1 | 8 |
+ * | 32 | 1 | 0 | 4 |
+ * | 32 | 1 | 1 | 8 |
+ */
+ if (!compress && !encrypt) {
+ cd_ratio = CDRATIO_x1;
+ } else {
+ if (compress)
+ cd_ratio = CDRATIO_x4;
+ else
+ cd_ratio = CDRATIO_x2;
+
+ /* if 32 bit, double the cd ratio (so register
+ field setting is incremented) */
+ if (cfg_width == CFGWDTH_32)
+ cd_ratio += 1;
+ }
+
+ fpgamgr_set_cfgwdth(cfg_width);
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+static int fpgamgr_reset(void)
+{
+ unsigned long reg;
+
+ /* S2F_NCONFIG = 0 */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 0 */
+ if (wait_for_f2s_nstatus_pin(0))
+ return -ETIME;
+
+ /* S2F_NCONFIG = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 1 */
+ if (wait_for_f2s_nstatus_pin(1))
+ return -ETIME;
+
+ /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
+ return -EPERM;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
+ return -EPERM;
+
+ return 0;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size)
+{
+ int ret;
+
+ /* Step 1 */
+ if (fpgamgr_verify_msel())
+ return -EPERM;
+
+ /* Step 2 */
+ if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
+ return -EPERM;
+
+ /*
+ * Step 3:
+ * Make sure no other external devices are trying to interfere with
+ * programming:
+ */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /*
+ * Step 4:
+ * Deassert the signal drives from HPS
+ *
+ * S2F_NCE = 1
+ * S2F_PR_REQUEST = 0
+ * EN_CFG_CTRL = 0
+ * EN_CFG_DATA = 0
+ * S2F_NCONFIG = 1
+ * S2F_NSTATUS_OE = 0
+ * S2F_CONDONE_OE = 0
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
+
+ /*
+ * Step 5:
+ * Enable overrides
+ * S2F_NENABLE_CONFIG = 0
+ * S2F_NENABLE_NCONFIG = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /*
+ * Disable driving signals that HPS doesn't need to drive.
+ * S2F_NENABLE_NSTATUS = 1
+ * S2F_NENABLE_CONDONE = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
+
+ /*
+ * Step 6:
+ * Drive chip select S2F_NCE = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /* Step 7 */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /* Step 8 */
+ ret = fpgamgr_reset();
+
+ if (ret)
+ return ret;
+
+ /*
+ * Step 9:
+ * EN_CFG_CTRL and EN_CFG_DATA = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ return 0;
+}
+
+/* Write the RBF data to FPGA Manager */
+void fpgamgr_program_write(const unsigned long *rbf_data,
+ unsigned long rbf_size)
+{
+ /* Write sof/pof data to img_data_w */
+ fpgamgr_axi_write(rbf_data, SOCFPGA_FPGAMGRDATA_ADDRESS, rbf_size);
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
+ return 0;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
+ printf("nstatus == 0 while waiting for condone\n");
+ return -EPERM;
+ }
+ }
+
+ if (i == FPGA_TIMEOUT_CNT)
+ return -ETIME;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long reg;
+ int ret = 0;
+
+ if (fpgamgr_dclkcnt_set(0xf))
+ return -ETIME;
+
+ ret = wait_for_user_mode();
+
+ if (ret < 0) {
+ printf("%s: Failed to enter user mode with ", __func__);
+ printf("error code %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Step 14:
+ * Stop DATA path and Dclk
+ * EN_CFG_CTRL and EN_CFG_DATA = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ /*
+ * Step 15:
+ * Disable overrides
+ * S2F_NENABLE_CONFIG = 1
+ * S2F_NENABLE_NCONFIG = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /* Disable chip select S2F_NCE = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /*
+ * Step 16:
+ * Final check
+ */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) == 0) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) == 0) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0))
+ return -EPERM;
+
+ return 0;
+}
+
+int fpgamgr_program_fini(void)
+{
+ /* Ensure the FPGA entering config done */
+ int status = fpgamgr_program_poll_cd();
+
+ if (status) {
+ printf("FPGA: Poll CD failed with error code %d\n", status);
+ return -EPERM;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ printf("FPGA: Poll usermode failed with error code %d\n",
+ status);
+ return -EPERM;
+ }
+
+ printf("Full Configuration Succeeded.\n");
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ return fpgamgr_program_fini();
+}
diff --git a/include/intel_socfpga/fpga_manager.h b/include/intel_socfpga/fpga_manager.h
index 8dbf369..a4bfda6 100644
--- a/include/intel_socfpga/fpga_manager.h
+++ b/include/intel_socfpga/fpga_manager.h
@@ -12,6 +12,8 @@
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <intel_socfpga/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <intel_socfpga/fpga_manager_arria10.h>
#endif
/* FPGA CD Ratio Value */
diff --git a/include/intel_socfpga/fpga_manager_arria10.h b/include/intel_socfpga/fpga_manager_arria10.h
new file mode 100644
index 0000000..3fb4aed
--- /dev/null
+++ b/include/intel_socfpga/fpga_manager_arria10.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+
+/* Timeout counter */
+#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ u32 _pad_0x0_0x7[2];
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo;
+ u32 gpi;
+ u32 misci;
+ u32 _pad_0x1c_0x2f[5];
+ u32 emr_data0;
+ u32 emr_data1;
+ u32 emr_data2;
+ u32 emr_data3;
+ u32 emr_data4;
+ u32 emr_data5;
+ u32 emr_valid;
+ u32 emr_en;
+ u32 jtag_config;
+ u32 jtag_status;
+ u32 jtag_kick;
+ u32 _pad_0x5c_0x5f;
+ u32 jtag_data_w;
+ u32 jtag_data_r;
+ u32 _pad_0x68_0x6f[2];
+ u32 imgcfg_ctrl_00;
+ u32 imgcfg_ctrl_01;
+ u32 imgcfg_ctrl_02;
+ u32 _pad_0x7c_0x7f;
+ u32 imgcfg_stat;
+ u32 intr_masked_status;
+ u32 intr_mask;
+ u32 intr_polarity;
+ u32 dma_config;
+ u32 imgcfg_fifo_status;
+};
+
+/* Functions */
+void fpgamgr_axi_write(const unsigned long *rbf_data,
+ const unsigned long fpgamgr_data_addr, unsigned long rbf_size);
+int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size);
+int fpgamgr_program_fini(void);
+int is_fpgamgr_user_mode(void);
+void fpgamgr_program_write(const unsigned long *rbf_data,
+ unsigned long rbf_size);
+int fpgamgr_wait_early_user_mode(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
--
1.7.7.4
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