[PATCH v1 0/4] Enable guest linux i915 full ppgtt functionality

[PATCH v1 0/4] Enable guest linux i915 full ppgtt functionality

[Tina Zhang]

This patchset fixs guest i915 full ppgtt block issue in device model and
enables the full ppgtt functionality to guest i915 driver when device model
with the fixed patch can support this capability.

Tina Zhang (4):
  drm/i915/gvt: reorder the shadow ppgtt update process by adding entry
    first
  drm/i915: introduce vgt_caps to pvinfo
  drm/i915/gvt: provide full ppgtt capability for guest i915 driver
  drm/i915: enable guest full ppgtt when device model supports

 drivers/gpu/drm/i915/gvt/gtt.c      | 45 +++++++++++++++++++++++--------------
 drivers/gpu/drm/i915/gvt/vgpu.c     |  1 +
 drivers/gpu/drm/i915/i915_drv.h     |  1 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/i915_pvinfo.h  |  7 +++++-
 drivers/gpu/drm/i915/i915_vgpu.c    |  6 +++++
 drivers/gpu/drm/i915/i915_vgpu.h    |  1 +
 7 files changed, 45 insertions(+), 20 deletions(-)

-- 
2.7.4

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[PATCH v1 1/4] drm/i915/gvt: reorder the shadow ppgtt update process by adding entry first

[Tina Zhang]

Guest i915 driver may update the ppgtt table just before this workload
is going to be submitted to the hardware by device model. This case
wasn't handled well by device model before, due to the small time
window between removing old ppgtt entry and adding the new one. Errors
occur when the workload is executed by hardware during that small time
window. This patch is to remove this time window by adding the new ppgtt
entry first and then remove the old one.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 45 ++++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index c6f0077..8caad86 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -975,29 +975,26 @@ static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
 }
 
 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt,
-		unsigned long index)
+		struct intel_gvt_gtt_entry *se, unsigned long index)
 {
 	struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
 	struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
 	struct intel_vgpu *vgpu = spt->vgpu;
 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
-	struct intel_gvt_gtt_entry e;
 	int ret;
 
-	ppgtt_get_shadow_entry(spt, &e, index);
-
-	trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64,
+	trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, se->val64,
 			 index);
 
-	if (!ops->test_present(&e))
+	if (!ops->test_present(se))
 		return 0;
 
-	if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn)
+	if (ops->get_pfn(se) == vgpu->gtt.scratch_pt[sp->type].page_mfn)
 		return 0;
 
-	if (gtt_type_is_pt(get_next_pt_type(e.type))) {
+	if (gtt_type_is_pt(get_next_pt_type(se->type))) {
 		struct intel_vgpu_ppgtt_spt *s =
-			ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e));
+			ppgtt_find_shadow_page(vgpu, ops->get_pfn(se));
 		if (!s) {
 			gvt_vgpu_err("fail to find guest page\n");
 			ret = -ENXIO;
@@ -1007,12 +1004,10 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt,
 		if (ret)
 			goto fail;
 	}
-	ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn);
-	ppgtt_set_shadow_entry(spt, &e, index);
 	return 0;
 fail:
 	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
-			spt, e.val64, e.type);
+			spt, se->val64, se->type);
 	return ret;
 }
 
@@ -1232,22 +1227,37 @@ static int ppgtt_handle_guest_write_page_table(
 {
 	struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
 	struct intel_vgpu *vgpu = spt->vgpu;
+	int type = spt->shadow_page.type;
 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+	struct intel_gvt_gtt_entry se;
 
 	int ret;
 	int new_present;
 
 	new_present = ops->test_present(we);
 
-	ret = ppgtt_handle_guest_entry_removal(gpt, index);
-	if (ret)
-		goto fail;
+	/*
+	 * Adding the new entry first and then removing the old one, that can
+	 * guarantee the ppgtt table is validated during the window between
+	 * adding and removal.
+	 */
+	ppgtt_get_shadow_entry(spt, &se, index);
 
 	if (new_present) {
 		ret = ppgtt_handle_guest_entry_add(gpt, we, index);
 		if (ret)
 			goto fail;
 	}
+
+	ret = ppgtt_handle_guest_entry_removal(gpt, &se, index);
+	if (ret)
+		goto fail;
+
+	if (!new_present) {
+		ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
+		ppgtt_set_shadow_entry(spt, &se, index);
+	}
+
 	return 0;
 fail:
 	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
@@ -1319,7 +1329,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
 	struct intel_vgpu *vgpu = spt->vgpu;
 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
-	struct intel_gvt_gtt_entry we;
+	struct intel_gvt_gtt_entry we, se;
 	unsigned long index;
 	int ret;
 
@@ -1335,7 +1345,8 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
 			return ret;
 	} else {
 		if (!test_bit(index, spt->post_shadow_bitmap)) {
-			ret = ppgtt_handle_guest_entry_removal(gpt, index);
+			ppgtt_get_shadow_entry(spt, &se, index);
+			ret = ppgtt_handle_guest_entry_removal(gpt, &se, index);
 			if (ret)
 				return ret;
 		}
-- 
2.7.4

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[PATCH v1 2/4] drm/i915: introduce vgt_caps to pvinfo

[Tina Zhang]

vgt_caps is used for guest i915 driver to get the vgpu capabilities
from the device model.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index c0cb297..a879478 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -58,7 +58,8 @@ struct vgt_if {
 	uint16_t version_major;
 	uint16_t version_minor;
 	u32 vgt_id;		/* ID of vGT instance */
-	u32 rsv1[12];		/* pad to offset 0x40 */
+	uint32_t  vgt_caps;     /* VGT capabilities */
+	u32 rsv1[11];		/* pad to offset 0x40 */
 	/*
 	 *  Data structure to describe the balooning info of resources.
 	 *  Each VM can only have one portion of continuous area for now.
-- 
2.7.4

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Re: [PATCH v1 2/4] drm/i915: introduce vgt_caps to pvinfo

[Joonas Lahtinen]

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote:
> vgt_caps is used for guest i915 driver to get the vgpu capabilities
> from the device model.
> 
> Signed-off-by: Tina Zhang <tina.zhang@intel.com>

<SNIP>

> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -58,7 +58,8 @@ struct vgt_if {
>  	uint16_t version_major;
>  	uint16_t version_minor;
>  	u32 vgt_id;		/* ID of vGT instance */
> -	u32 rsv1[12];		/* pad to offset 0x40 */
> +	uint32_t  vgt_caps;     /* VGT capabilities */

This should really be u32 too.

Regards, Joonas

> +	u32 rsv1[11];		/* pad to offset 0x40 */
>  	/*
>  	 *  Data structure to describe the balooning info of resources.
>  	 *  Each VM can only have one portion of continuous area for now.
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[PATCH v1 3/4] drm/i915/gvt: provide full ppgtt capability for guest i915 driver

[Tina Zhang]

This patch is to provide full ppgtt capability for guest i915 driver.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/vgpu.c    | 1 +
 drivers/gpu/drm/i915/i915_pvinfo.h | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 6e3cbd8..23578c1 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -43,6 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
 	vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
+	vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index a879478..bbe554c 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -53,6 +53,10 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+enum vgt_caps_type {
+	VGT_CAPS_FULL_PPGTT = (1 << 2),
+};
+
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
 	uint16_t version_major;
-- 
2.7.4

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Re: [PATCH v1 3/4] drm/i915/gvt: provide full ppgtt capability for guest i915 driver

[Joonas Lahtinen]

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote:
> This patch is to provide full ppgtt capability for guest i915 driver.
> 
> Signed-off-by: Tina Zhang <tina.zhang@intel.com>

<SNIP>

> @@ -53,6 +53,10 @@ enum vgt_g2v_type {
>  	VGT_G2V_MAX,
>  };
>  
> +enum vgt_caps_type {
> +	VGT_CAPS_FULL_PPGTT = (1 << 2),
> +};

Please separate this change to the previous patch to keep it separate
from the gvt/ folder changes. Also use #define and BIT(2) notation.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[PATCH v1 4/4] drm/i915: enable guest full ppgtt when device model supports

[Tina Zhang]

Add full ppgtt capability check in guest i915 driver and enable the full
ppgtt in guest only when device mode supports.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     | 1 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 drivers/gpu/drm/i915/i915_vgpu.c    | 6 ++++++
 drivers/gpu/drm/i915/i915_vgpu.h    | 1 +
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 357b6c6..212147b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1909,6 +1909,7 @@ struct i915_workarounds {
 
 struct i915_virtual_gpu {
 	bool active;
+	uint32_t  caps;
 };
 
 /* used in computing the new watermarks state */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8bab4ae..15aa081 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -141,8 +141,8 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
 	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
 
-	if (intel_vgpu_active(dev_priv)) {
-		/* emulation is too hard */
+	if (intel_vgpu_active(dev_priv) &&
+	    (!intel_vgpu_has_full_ppgtt(dev_priv))) {
 		has_full_ppgtt = false;
 		has_full_48bit_ppgtt = false;
 	}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 4ab8a97..9b92c73 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -77,10 +77,16 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 		return;
 	}
 
+	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
 	dev_priv->vgpu.active = true;
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
+bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
+{
+	return (dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT) ? true : false;
+}
+
 struct _balloon_info_ {
 	/*
 	 * There are up to 2 regions per mappable/unmappable graphic
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 3c3b2d2..4fc20aa 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -29,5 +29,6 @@
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
 
 #endif /* _I915_VGPU_H_ */
-- 
2.7.4

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Re: [PATCH v1 4/4] drm/i915: enable guest full ppgtt when device model supports

[Joonas Lahtinen]

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote:
> Add full ppgtt capability check in guest i915 driver and enable the full
> ppgtt in guest only when device mode supports.
> 
> Signed-off-by: Tina Zhang <tina.zhang@intel.com>

<SNIP>

> @@ -1909,6 +1909,7 @@ struct i915_workarounds {
>  
>  struct i915_virtual_gpu {
>  	bool active;
> +	uint32_t  caps;

u32, and no extra spaces.

> @@ -141,8 +141,8 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
>  	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
>  
> -	if (intel_vgpu_active(dev_priv)) {
> -		/* emulation is too hard */
> +	if (intel_vgpu_active(dev_priv) &&
> +	    (!intel_vgpu_has_full_ppgtt(dev_priv))) {
>  		has_full_ppgtt = false;
>  		has_full_48bit_ppgtt = false;

	has_full_ppgtt = dev_priv->info.has_full_ppgtt;

	if (intel_vpgu_active(dev_priv))
		has_full_ppgtt = intel_vgpu_has_full_ppgtt(dev_priv);

 	has_full_48bit_ppgtt = has_full_ppgtt &&
			       dev_priv->info.has_full_48bit_ppgtt;

	Would make for cleanest code.

>  	}
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 4ab8a97..9b92c73 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -77,10 +77,16 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>  		return;
>  	}
>  
> +	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));

Newline.

>  	dev_priv->vgpu.active = true;
>  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
>  }
>  
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
> +{
> +	return (dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT) ? true : false;
> +}

The ternary operator is not needed.

> +
>  struct _balloon_info_ {
>  	/*
>  	 * There are up to 2 regions per mappable/unmappable graphic
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 3c3b2d2..4fc20aa 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -29,5 +29,6 @@
>  void i915_check_vgpu(struct drm_i915_private *dev_priv);

Add the new function here and add a newline to separate.

Regards, Joonas

>  int intel_vgt_balloon(struct drm_i915_private *dev_priv);
>  void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
>  
>  #endif /* _I915_VGPU_H_ */
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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✓ Fi.CI.BAT: success for Enable guest linux i915 full ppgtt functionality

[Patchwork]

== Series Details ==

Series: Enable guest linux i915 full ppgtt functionality
URL   : https://patchwork.freedesktop.org/series/24271/
State : success

== Summary ==

Series 24271v1 Enable guest linux i915 full ppgtt functionality
https://patchwork.freedesktop.org/api/1.0/series/24271/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                dmesg-warn -> PASS       (fi-kbl-7560u) fdo#100125
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                pass       -> FAIL       (fi-snb-2600) fdo#100215

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:423s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:431s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:588s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:514s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time:568s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:493s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:488s
fi-elk-e7500     total:278  pass:229  dwarn:0   dfail:0   fail:0   skip:49  time:423s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:420s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:400s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:423s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:496s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:463s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:449s
fi-kbl-7560u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:557s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:443s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time:563s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:447s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:504s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:436s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:545s
fi-snb-2600      total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  time:403s

4149c7b22164d81960dae0987f497725117b68e6 drm-tip: 2017y-05m-10d-18h-09m-15s UTC integration manifest
dfd36e2 drm/i915: enable guest full ppgtt when device model supports
f37994f drm/i915/gvt: provide full ppgtt capability for guest i915 driver
d599a0c drm/i915: introduce vgt_caps to pvinfo
be4e5e3 drm/i915/gvt: reorder the shadow ppgtt update process by adding entry first

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4666/
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