* [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver
@ 2017-05-15 10:52 tien.fong.chee at intel.com
2017-05-15 10:52 ` [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-15 10:52 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This is the 3rd version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Marek in [v2].This series is
working on top of u-boot-socfpga-next branch
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/next.
[v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.html
v2 -> v3 changes:
-----------------
- Changed the commit messages on patch 1.
- Changed to size_t for size, moved timeout #define into c files, reverted deleted
line, and fixing copyright extending issue on patch 2.
- No change on patch 3.
- Reverted all fpga header files back to arch/arm/mach-socfpga/.
- Changed unsigned int to u32, size_t for size, and fixing indentation on patch 4.
Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.html
Tien Fong Chee (4):
arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
arm: socfpga: Restructure FPGA driver in the preparation to support
A10.
arm: socfpga: Move FPGA manager driver to FPGA driver
arm: socfpga: Add FPGA driver support for Arria 10
arch/arm/mach-socfpga/Makefile | 1 -
arch/arm/mach-socfpga/fpga_manager.c | 78 ----
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +--
.../include/mach/fpga_manager_arria10.h | 100 +++++
.../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++-
.../include/mach/reset_manager_arria10.h | 2 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 4 +-
drivers/Makefile | 1 +
drivers/fpga/Makefile | 2 +
drivers/fpga/socfpga.c | 241 +---------
drivers/fpga/socfpga_arria10.c | 487 +++++++++++++++++++++
drivers/fpga/{socfpga.c => socfpga_gen5.c} | 98 +++--
include/configs/socfpga_common.h | 3 +-
13 files changed, 693 insertions(+), 463 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
create mode 100644 drivers/fpga/socfpga_arria10.c
copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)
--
1.8.2.3
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
@ 2017-05-15 10:52 ` tien.fong.chee at intel.com
2017-05-17 14:41 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-15 10:52 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deasserte_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 7922db8..b6d7f4f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index d8c858c..66f1ec2 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
/* For SoCFPGA-VT, this is NOP. */
return 0;
}
#else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
int ret;
--
1.8.2.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-15 10:52 ` [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
@ 2017-05-15 10:52 ` tien.fong.chee at intel.com
2017-05-17 8:21 ` Ley Foon Tan
2017-05-17 18:37 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
` (2 subsequent siblings)
4 siblings, 2 replies; 14+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-15 10:52 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA drivi er intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/ .
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +-
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 68 +-----
.../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
drivers/Makefile | 1 +
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga.c | 241 +--------------------
drivers/fpga/{socfpga.c => socfpga_gen5.c} | 54 +----
7 files changed, 50 insertions(+), 386 deletions(-)
copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 41b779c..286bfef 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
obj-y += board.o
obj-y += clock_manager.o
-obj-y += fpga_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
@@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
+obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..b046c2c 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -10,58 +10,9 @@
#include <altera.h>
-struct socfpga_fpga_manager {
- /* FPGA Manager Module */
- u32 stat; /* 0x00 */
- u32 ctrl;
- u32 dclkcnt;
- u32 dclkstat;
- u32 gpo; /* 0x10 */
- u32 gpi;
- u32 misci; /* 0x18 */
- u32 _pad_0x1c_0x82c[517];
-
- /* Configuration Monitor (MON) Registers */
- u32 gpio_inten; /* 0x830 */
- u32 gpio_intmask;
- u32 gpio_inttype_level;
- u32 gpio_int_polarity;
- u32 gpio_intstatus; /* 0x840 */
- u32 gpio_raw_intstatus;
- u32 _pad_0x848;
- u32 gpio_porta_eoi;
- u32 gpio_ext_porta; /* 0x850 */
- u32 _pad_0x854_0x85c[3];
- u32 gpio_1s_sync; /* 0x860 */
- u32 _pad_0x864_0x868[2];
- u32 gpio_ver_id_code;
- u32 gpio_config_reg2; /* 0x870 */
- u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#endif
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
@@ -69,9 +20,14 @@ struct socfpga_fpga_manager {
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 57%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
index a077e22..2de7a11 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
@@ -1,14 +1,38 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef _FPGA_MANAGER_H_
-#define _FPGA_MANAGER_H_
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
-#include <altera.h>
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
/* FPGA Manager Module */
@@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
u32 gpio_config_reg1;
};
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
-
-/* FPGA CD Ratio Value */
-#define CDRATIO_x1 0x0
-#define CDRATIO_x2 0x1
-#define CDRATIO_x4 0x2
-#define CDRATIO_x8 0x3
-
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
-int fpgamgr_get_mode(void);
+#endif /* __ASSEMBLY__ */
-#endif /* _FPGA_MANAGER_H_ */
+#endif /* _FPGA_MANAGER_GEN5_H_ */
diff --git a/drivers/Makefile b/drivers/Makefile
index 4a4b237..b4a2230 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_FPGA) += fpga/
endif
ifdef CONFIG_TPL_BUILD
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 777706f..b65e5ba 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
endif
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..5200de7 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -14,23 +14,12 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
+#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
- clrsetbits_le32(&fpgamgr_regs->ctrl,
- 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
- (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}
-
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
+int fpgamgr_dclkcnt_set(unsigned long cnt)
{
unsigned long i;
@@ -53,98 +42,8 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt)
return -ETIMEDOUT;
}
-/* Start the FPGA programming by initialize the FPGA Manager */
-static int fpgamgr_program_init(void)
-{
- unsigned long msel, i;
-
- /* Get the MSEL value */
- msel = readl(&fpgamgr_regs->stat);
- msel &= FPGAMGRREGS_STAT_MSEL_MASK;
- msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
-
- /*
- * Set the cfg width
- * If MSEL[3] = 1, cfg width = 32 bit
- */
- if (msel & 0x8) {
- setbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- /* MSEL[1:0] = 2, CD Ratio = 8 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x8);
-
- } else { /* MSEL[3] = 0 */
- clrbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 2 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x2);
- /* MSEL[1:0] = 2, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- }
-
- /* To enable FPGA Manager configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
-
- /* To enable FPGA Manager drive over configuration line */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- /* Put FPGA into reset phase */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (1) wait until FPGA enter reset phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
- break;
- }
-
- /* If not in reset state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
- puts("FPGA: Could not reset\n");
- return -1;
- }
-
- /* Release FPGA from reset phase */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (2) wait until FPGA enter configuration phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
- puts("FPGA: Could not configure\n");
- return -2;
- }
-
- /* Clear all interrupts in CB Monitor */
- writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
-
- /* Enable AXI configuration */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
{
uint32_t src = (uint32_t)rbf_data;
uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
@@ -169,136 +68,4 @@ static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
"3: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
-}
-
-/* Ensure the FPGA entering config done */
-static int fpgamgr_program_poll_cd(void)
-{
- const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
- FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
-
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
-
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
- }
-
- /* Disable AXI configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Ensure the FPGA entering init phase */
-static int fpgamgr_program_poll_initphase(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to enter initialization phase */
- if (fpgamgr_dclkcnt_set(0x4))
- return -5;
-
- /* (4) wait until FPGA enter init phase or user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
- break;
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -6;
-
- return 0;
-}
-
-/* Ensure the FPGA entering user mode */
-static int fpgamgr_program_poll_usermode(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to exit initialization phase */
- if (fpgamgr_dclkcnt_set(0x5000))
- return -7;
-
- /* (5) wait until FPGA enter user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -8;
-
- /* To release FPGA Manager drive over configuration line */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- return 0;
-}
-
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
-int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
-{
- unsigned long status;
-
- if ((uint32_t)rbf_data & 0x3) {
- puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
- return -EINVAL;
- }
-
- /* Prior programming the FPGA, all bridges need to be shut off */
-
- /* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
-
- /* Disable all signals from FPGA to HPS SDRAM */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
- writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
-
- /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
- socfpga_bridges_reset(1);
-
- /* Unmap the bridges from NIC-301 */
- writel(0x1, SOCFPGA_L3REGS_ADDRESS);
-
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init();
- if (status)
- return status;
-
- /* Write the RBF data to FPGA Manager */
- fpgamgr_program_write(rbf_data, rbf_size);
-
- /* Ensure the FPGA entering config done */
- status = fpgamgr_program_poll_cd();
- if (status)
- return status;
-
- /* Ensure the FPGA entering init phase */
- status = fpgamgr_program_poll_initphase();
- if (status)
- return status;
-
- /* Ensure the FPGA entering user mode */
- return fpgamgr_program_poll_usermode();
-}
+}
\ No newline at end of file
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
similarity index 83%
copy from drivers/fpga/socfpga.c
copy to drivers/fpga/socfpga_gen5.c
index f1b2f2c..3dfb030 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -14,8 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
+#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
@@ -30,29 +29,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
}
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
-{
- unsigned long i;
-
- /* Clear any existing done status */
- if (readl(&fpgamgr_regs->dclkstat))
- writel(0x1, &fpgamgr_regs->dclkstat);
-
- /* Write the dclkcnt */
- writel(cnt, &fpgamgr_regs->dclkcnt);
-
- /* Wait till the dclkcnt done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (!readl(&fpgamgr_regs->dclkstat))
- continue;
-
- writel(0x1, &fpgamgr_regs->dclkstat);
- return 0;
- }
-
- return -ETIMEDOUT;
-}
-
/* Start the FPGA programming by initialize the FPGA Manager */
static int fpgamgr_program_init(void)
{
@@ -143,34 +119,6 @@ static int fpgamgr_program_init(void)
return 0;
}
-/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
-{
- uint32_t src = (uint32_t)rbf_data;
- uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
-
- /* Number of loops for 32-byte long copying. */
- uint32_t loops32 = rbf_size / 32;
- /* Number of loops for 4-byte long copying + trailing bytes */
- uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
-
- asm volatile(
- "1: ldmia %0!, {r0-r7}\n"
- " stmia %1!, {r0-r7}\n"
- " sub %1, #32\n"
- " subs %2, #1\n"
- " bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
- " str %2, [%1]\n"
- " subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
- : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
- : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
-}
-
/* Ensure the FPGA entering config done */
static int fpgamgr_program_poll_cd(void)
{
--
1.8.2.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-15 10:52 ` [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-05-15 10:52 ` [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
@ 2017-05-15 10:52 ` tien.fong.chee at intel.com
2017-05-17 18:45 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
2017-05-17 5:12 ` [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
4 siblings, 1 reply; 14+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-15 10:52 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move FPGA manager driver which is Gen5 specific code from arch/arm/
into FPGA driver at driver/fpga/. No functional change.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 -
arch/arm/mach-socfpga/fpga_manager.c | 78 ------------------------------------
drivers/fpga/socfpga_gen5.c | 54 +++++++++++++++++++++++++
3 files changed, 54 insertions(+), 79 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..824cd8e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -20,7 +20,6 @@ obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
-obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
deleted file mode 100644
index f909573..0000000
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- * All rights reserved.
- *
- * This file contains only support functions used also by the SoCFPGA
- * platform code, the real meat is located in drivers/fpga/socfpga.c .
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/fpga_manager.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
-static struct socfpga_fpga_manager *fpgamgr_regs =
- (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-
-/* Check whether FPGA Init_Done signal is high */
-static int is_fpgamgr_initdone_high(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->gpio_ext_porta);
- return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
-}
-
-/* Get the FPGA mode */
-int fpgamgr_get_mode(void)
-{
- unsigned long val;
-
- val = readl(&fpgamgr_regs->stat);
- return val & FPGAMGRREGS_STAT_MODE_MASK;
-}
-
-/* Check whether FPGA is ready to be accessed */
-int fpgamgr_test_fpga_ready(void)
-{
- /* Check for init done signal */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- /* Check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- return 0;
-
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
- return 0;
-
- return 1;
-}
-
-/* Poll until FPGA is ready to be accessed or timeout occurred */
-int fpgamgr_poll_fpga_ready(void)
-{
- unsigned long i;
-
- /* If FPGA is blank, wait till WD invoke warm reset */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- /* check for init done signal */
- if (!is_fpgamgr_initdone_high())
- continue;
- /* check again to avoid false glitches */
- if (!is_fpgamgr_initdone_high())
- continue;
- return 1;
- }
-
- return 0;
-}
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 3dfb030..d8f222a 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -21,6 +21,60 @@ static struct socfpga_fpga_manager *fpgamgr_regs =
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->gpio_ext_porta);
+ return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->stat);
+ return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+ /* Check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ /* Check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ /* check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ return 1;
+ }
+
+ return 0;
+}
+
/* Set CD ratio */
static void fpgamgr_set_cd_ratio(unsigned long ratio)
{
--
1.8.2.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (2 preceding siblings ...)
2017-05-15 10:52 ` [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
@ 2017-05-15 10:52 ` tien.fong.chee at intel.com
2017-05-17 8:49 ` Ley Foon Tan
2017-05-17 19:03 ` Dinh Nguyen
2017-05-17 5:12 ` [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
4 siblings, 2 replies; 14+ messages in thread
From: tien.fong.chee at intel.com @ 2017-05-15 10:52 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
.../include/mach/fpga_manager_arria10.h | 100 +++++
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga_arria10.c | 487 +++++++++++++++++++++
include/configs/socfpga_common.h | 3 +-
5 files changed, 592 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
create mode 100644 drivers/fpga/socfpga_arria10.c
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index b046c2c..a21c716 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -12,6 +12,8 @@
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
#endif
/* FPGA CD Ratio Value */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 0000000..18d9580
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ u32 _pad_0x0_0x7[2];
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo;
+ u32 gpi;
+ u32 misci;
+ u32 _pad_0x1c_0x2f[5];
+ u32 emr_data0;
+ u32 emr_data1;
+ u32 emr_data2;
+ u32 emr_data3;
+ u32 emr_data4;
+ u32 emr_data5;
+ u32 emr_valid;
+ u32 emr_en;
+ u32 jtag_config;
+ u32 jtag_status;
+ u32 jtag_kick;
+ u32 _pad_0x5c_0x5f;
+ u32 jtag_data_w;
+ u32 jtag_data_r;
+ u32 _pad_0x68_0x6f[2];
+ u32 imgcfg_ctrl_00;
+ u32 imgcfg_ctrl_01;
+ u32 imgcfg_ctrl_02;
+ u32 _pad_0x7c_0x7f;
+ u32 imgcfg_stat;
+ u32 intr_masked_status;
+ u32 intr_mask;
+ u32 intr_polarity;
+ u32 dma_config;
+ u32 imgcfg_fifo_status;
+};
+
+/* Functions */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
+int fpgamgr_program_fini(void);
+int is_fpgamgr_user_mode(void);
+int fpgamgr_wait_early_user_mode(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index b65e5ba..08c9ff8 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
new file mode 100644
index 0000000..262e962
--- /dev/null
+++ b/drivers/fpga/socfpga_arria10.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32 1
+#define MIN_BITSTREAM_SIZECHECK 230
+#define ENCRYPTION_OFFSET 69
+#define COMPRESSION_OFFSET 229
+#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+ (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+ u32 reg;
+
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+ return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+ if (width)
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+ else
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+/* Check whether FPGA Init_Done signal is high */
+int is_fpgamgr_initdone_high(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
+}
+
+int is_fpgamgr_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+ u32 sync_data = 0xffffffff;
+ u32 i = 0;
+ unsigned start = get_timer(0);
+ unsigned long cd_ratio;
+
+ /* Getting existing CDRATIO */
+ cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+ /* Using CDRATIO_X1 for better compatibility */
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+ while (!(is_fpgamgr_early_user_mode())) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ udelay(FPGA_TIMEOUT_MSEC);
+ i++;
+ }
+
+ debug("Additional %i sync word needed\n", i);
+
+ /* restoring original CDRATIO */
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+ unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+ /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
+ * timeout at 1000ms
+ */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ mask,
+ false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+ /* Poll until f2s to specific value, timeout at 1000ms */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+ value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration mode */
+static int fpgamgr_verify_msel(void)
+{
+ u32 msel = fpgamgr_get_msel();
+
+ if ((msel != 0) && (msel != 1)) {
+ printf("Fail: read msel=%d\n", msel);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+ size_t rbf_size)
+{
+ unsigned int cd_ratio;
+ bool encrypt, compress;
+
+ /*
+ * According to the bitstream specification,
+ * both encryption and compression status are
+ * in location before offset 230 of the buffer.
+ */
+ if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+ return -EINVAL;
+
+ encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+ encrypt = encrypt != 0;
+
+ compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+ compress = !compress;
+
+ debug("header word %d = %08x\n", 69, rbf_data[69]);
+ debug("header word %d = %08x\n", 229, rbf_data[229]);
+ debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+
+ /*
+ * from the register map description of cdratio in imgcfg_ctrl_02:
+ * Normal Configuration : 32bit Passive Parallel
+ * Partial Reconfiguration : 16bit Passive Parallel
+ */
+
+ /*
+ * cd ratio is dependent on cfg width and whether the bitstream
+ * is encrypted and/or compressed.
+ *
+ * | width | encr. | compr. | cd ratio |
+ * | 16 | 0 | 0 | 1 |
+ * | 16 | 0 | 1 | 4 |
+ * | 16 | 1 | 0 | 2 |
+ * | 16 | 1 | 1 | 4 |
+ * | 32 | 0 | 0 | 1 |
+ * | 32 | 0 | 1 | 8 |
+ * | 32 | 1 | 0 | 4 |
+ * | 32 | 1 | 1 | 8 |
+ */
+ if (!compress && !encrypt) {
+ cd_ratio = CDRATIO_x1;
+ } else {
+ if (compress)
+ cd_ratio = CDRATIO_x4;
+ else
+ cd_ratio = CDRATIO_x2;
+
+ /* if 32 bit, double the cd ratio (so register
+ field setting is incremented) */
+ if (cfg_width == CFGWDTH_32)
+ cd_ratio += 1;
+ }
+
+ fpgamgr_set_cfgwdth(cfg_width);
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+static int fpgamgr_reset(void)
+{
+ unsigned long reg;
+
+ /* S2F_NCONFIG = 0 */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 0 */
+ if (wait_for_f2s_nstatus_pin(0))
+ return -ETIME;
+
+ /* S2F_NCONFIG = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 1 */
+ if (wait_for_f2s_nstatus_pin(1))
+ return -ETIME;
+
+ /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
+ return -EPERM;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
+ return -EPERM;
+
+ return 0;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ /* Step 1 */
+ if (fpgamgr_verify_msel())
+ return -EPERM;
+
+ /* Step 2 */
+ if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
+ return -EPERM;
+
+ /*
+ * Step 3:
+ * Make sure no other external devices are trying to interfere with
+ * programming:
+ */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /*
+ * Step 4:
+ * Deassert the signal drives from HPS
+ *
+ * S2F_NCE = 1
+ * S2F_PR_REQUEST = 0
+ * EN_CFG_CTRL = 0
+ * EN_CFG_DATA = 0
+ * S2F_NCONFIG = 1
+ * S2F_NSTATUS_OE = 0
+ * S2F_CONDONE_OE = 0
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
+
+ /*
+ * Step 5:
+ * Enable overrides
+ * S2F_NENABLE_CONFIG = 0
+ * S2F_NENABLE_NCONFIG = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /*
+ * Disable driving signals that HPS doesn't need to drive.
+ * S2F_NENABLE_NSTATUS = 1
+ * S2F_NENABLE_CONDONE = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
+
+ /*
+ * Step 6:
+ * Drive chip select S2F_NCE = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /* Step 7 */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /* Step 8 */
+ ret = fpgamgr_reset();
+
+ if (ret)
+ return ret;
+
+ /*
+ * Step 9:
+ * EN_CFG_CTRL and EN_CFG_DATA = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
+ return 0;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
+ printf("nstatus == 0 while waiting for condone\n");
+ return -EPERM;
+ }
+ }
+
+ if (i == FPGA_TIMEOUT_CNT)
+ return -ETIME;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long reg;
+ int ret = 0;
+
+ if (fpgamgr_dclkcnt_set(0xf))
+ return -ETIME;
+
+ ret = wait_for_user_mode();
+
+ if (ret < 0) {
+ printf("%s: Failed to enter user mode with ", __func__);
+ printf("error code %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Step 14:
+ * Stop DATA path and Dclk
+ * EN_CFG_CTRL and EN_CFG_DATA = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ /*
+ * Step 15:
+ * Disable overrides
+ * S2F_NENABLE_CONFIG = 1
+ * S2F_NENABLE_NCONFIG = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /* Disable chip select S2F_NCE = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /*
+ * Step 16:
+ * Final check
+ */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
+ return -EPERM;
+
+ return 0;
+}
+
+int fpgamgr_program_fini(void)
+{
+ /* Ensure the FPGA entering config done */
+ int status = fpgamgr_program_poll_cd();
+
+ if (status) {
+ printf("FPGA: Poll CD failed with error code %d\n", status);
+ return -EPERM;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ printf("FPGA: Poll usermode failed with error code %d\n",
+ status);
+ return -EPERM;
+ }
+
+ printf("Full Configuration Succeeded.\n");
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ return fpgamgr_program_fini();
+}
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index da7e4ad..992097d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -105,7 +105,8 @@
/*
* FPGA Driver
*/
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || \
+ defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
--
1.8.2.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
` (3 preceding siblings ...)
2017-05-15 10:52 ` [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
@ 2017-05-17 5:12 ` Chee, Tien Fong
2017-05-17 7:24 ` Marek Vasut
4 siblings, 1 reply; 14+ messages in thread
From: Chee, Tien Fong @ 2017-05-17 5:12 UTC (permalink / raw)
To: u-boot
On Isn, 2017-05-15 at 18:52 +0800, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This is the 3rd version of patchset to adds support for Intel Arria
> 10 SoC FPGA
> driver. This version mainly resolved comments from Marek in [v2].This
> series is
> working on top of u-boot-socfpga-next branch
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/hea
> ds/next.
>
> [v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.htm
> l
>
> v2 -> v3 changes:
> -----------------
> - Changed the commit messages on patch 1.
> - Changed to size_t for size, moved timeout #define into c files,
> reverted deleted
> line, and fixing copyright extending issue on patch 2.
> - No change on patch 3.
> - Reverted all fpga header files back to arch/arm/mach-socfpga/.
> - Changed unsigned int to u32, size_t for size, and fixing
> indentation on patch 4.
>
> Patchset history
> ----------------
> [v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.htm
> l
>
> Tien Fong Chee (4):
> arm: socfpga: Remove unused passing parameter of
> socfpga_bridges_reset
> arm: socfpga: Restructure FPGA driver in the preparation to support
> A10.
> arm: socfpga: Move FPGA manager driver to FPGA driver
> arm: socfpga: Add FPGA driver support for Arria 10
>
> arch/arm/mach-socfpga/Makefile | 1 -
> arch/arm/mach-socfpga/fpga_manager.c | 78 ----
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +--
> .../include/mach/fpga_manager_arria10.h | 100 +++++
> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++-
> .../include/mach/reset_manager_arria10.h | 2 +-
> arch/arm/mach-socfpga/reset_manager_arria10.c | 4 +-
> drivers/Makefile | 1 +
> drivers/fpga/Makefile | 2 +
> drivers/fpga/socfpga.c | 241 +---------
> drivers/fpga/socfpga_arria10.c | 487
> +++++++++++++++++++++
> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 98 +++--
> include/configs/socfpga_common.h | 3 +-
> 13 files changed, 693 insertions(+), 463 deletions(-)
> delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> fpga_manager_gen5.h} (57%)
> create mode 100644 drivers/fpga/socfpga_arria10.c
> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)
>
Hi Marek, this whole patchset looks okay?
Thanks.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver
2017-05-17 5:12 ` [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
@ 2017-05-17 7:24 ` Marek Vasut
0 siblings, 0 replies; 14+ messages in thread
From: Marek Vasut @ 2017-05-17 7:24 UTC (permalink / raw)
To: u-boot
On 05/17/2017 07:12 AM, Chee, Tien Fong wrote:
> On Isn, 2017-05-15 at 18:52 +0800, tien.fong.chee at intel.com wrote:
>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>
>> This is the 3rd version of patchset to adds support for Intel Arria
>> 10 SoC FPGA
>> driver. This version mainly resolved comments from Marek in [v2].This
>> series is
>> working on top of u-boot-socfpga-next branch
>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/hea
>> ds/next.
>>
>> [v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.htm
>> l
>>
>> v2 -> v3 changes:
>> -----------------
>> - Changed the commit messages on patch 1.
>> - Changed to size_t for size, moved timeout #define into c files,
>> reverted deleted
>> line, and fixing copyright extending issue on patch 2.
>> - No change on patch 3.
>> - Reverted all fpga header files back to arch/arm/mach-socfpga/.
>> - Changed unsigned int to u32, size_t for size, and fixing
>> indentation on patch 4.
>>
>> Patchset history
>> ----------------
>> [v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.htm
>> l
>>
>> Tien Fong Chee (4):
>> arm: socfpga: Remove unused passing parameter of
>> socfpga_bridges_reset
>> arm: socfpga: Restructure FPGA driver in the preparation to support
>> A10.
>> arm: socfpga: Move FPGA manager driver to FPGA driver
>> arm: socfpga: Add FPGA driver support for Arria 10
>>
>> arch/arm/mach-socfpga/Makefile | 1 -
>> arch/arm/mach-socfpga/fpga_manager.c | 78 ----
>> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +--
>> .../include/mach/fpga_manager_arria10.h | 100 +++++
>> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++-
>> .../include/mach/reset_manager_arria10.h | 2 +-
>> arch/arm/mach-socfpga/reset_manager_arria10.c | 4 +-
>> drivers/Makefile | 1 +
>> drivers/fpga/Makefile | 2 +
>> drivers/fpga/socfpga.c | 241 +---------
>> drivers/fpga/socfpga_arria10.c | 487
>> +++++++++++++++++++++
>> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 98 +++--
>> include/configs/socfpga_common.h | 3 +-
>> 13 files changed, 693 insertions(+), 463 deletions(-)
>> delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
>> create mode 100644 arch/arm/mach-
>> socfpga/include/mach/fpga_manager_arria10.h
>> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
>> fpga_manager_gen5.h} (57%)
>> create mode 100644 drivers/fpga/socfpga_arria10.c
>> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)
>>
> Hi Marek, this whole patchset looks okay?
I'd like A-B/R-B from Dinh/Ley first.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-15 10:52 ` [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
@ 2017-05-17 8:21 ` Ley Foon Tan
2017-05-17 18:37 ` Dinh Nguyen
1 sibling, 0 replies; 14+ messages in thread
From: Ley Foon Tan @ 2017-05-17 8:21 UTC (permalink / raw)
To: u-boot
On Mon, May 15, 2017 at 6:52 PM, <tien.fong.chee@intel.com> wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Move FPGA driver which is Gen5 specific code into Gen5 driver file
> and keeping common FPGA drivi er intact. All the changes are still keeping
Typo "drivi er".
> in driver/fpga/ and no functional change. Subsequent patch would move
> FPGA manager driver from arch/arm into driver/fpga/ .
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 2 +-
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 68 +-----
> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
> drivers/Makefile | 1 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/socfpga.c | 241 +--------------------
> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 54 +----
> 7 files changed, 50 insertions(+), 386 deletions(-)
> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 41b779c..286bfef 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -9,7 +9,6 @@
>
> obj-y += board.o
> obj-y += clock_manager.o
> -obj-y += fpga_manager.o
> obj-y += misc.o
> obj-y += reset_manager.o
> obj-y += timer.o
> @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
> obj-y += scan_manager.o
> obj-y += system_manager_gen5.o
> obj-y += wrap_pll_config.o
> +obj-y += fpga_manager.o
> endif
>
> ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> index a077e22..b046c2c 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> @@ -10,58 +10,9 @@
>
> #include <altera.h>
>
> -struct socfpga_fpga_manager {
> - /* FPGA Manager Module */
> - u32 stat; /* 0x00 */
> - u32 ctrl;
> - u32 dclkcnt;
> - u32 dclkstat;
> - u32 gpo; /* 0x10 */
> - u32 gpi;
> - u32 misci; /* 0x18 */
> - u32 _pad_0x1c_0x82c[517];
> -
> - /* Configuration Monitor (MON) Registers */
> - u32 gpio_inten; /* 0x830 */
> - u32 gpio_intmask;
> - u32 gpio_inttype_level;
> - u32 gpio_int_polarity;
> - u32 gpio_intstatus; /* 0x840 */
> - u32 gpio_raw_intstatus;
> - u32 _pad_0x848;
> - u32 gpio_porta_eoi;
> - u32 gpio_ext_porta; /* 0x850 */
> - u32 _pad_0x854_0x85c[3];
> - u32 gpio_1s_sync; /* 0x860 */
> - u32 _pad_0x864_0x868[2];
> - u32 gpio_ver_id_code;
> - u32 gpio_config_reg2; /* 0x870 */
> - u32 gpio_config_reg1;
> -};
> -
> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> -
> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> -
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> -
> -/* FPGA Mode */
> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> -#define FPGAMGRREGS_MODE_USERMODE 0x4
> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#include <asm/arch/fpga_manager_gen5.h>
> +#endif
>
> /* FPGA CD Ratio Value */
> #define CDRATIO_x1 0x0
> @@ -69,9 +20,14 @@ struct socfpga_fpga_manager {
> #define CDRATIO_x4 0x2
> #define CDRATIO_x8 0x3
>
> -/* SoCFPGA support functions */
> -int fpgamgr_test_fpga_ready(void);
> -int fpgamgr_poll_fpga_ready(void);
> +#ifndef __ASSEMBLY__
> +
> +/* Common prototypes */
> int fpgamgr_get_mode(void);
> +int fpgamgr_poll_fpga_ready(void);
> +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
> +int fpgamgr_test_fpga_ready(void);
> +int fpgamgr_dclkcnt_set(unsigned long cnt);
>
> +#endif /* __ASSEMBLY__ */
> #endif /* _FPGA_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> similarity index 57%
> copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
> copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> index a077e22..2de7a11 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
> @@ -1,14 +1,38 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> * All rights reserved.
> *
> * SPDX-License-Identifier: BSD-3-Clause
> */
>
> -#ifndef _FPGA_MANAGER_H_
> -#define _FPGA_MANAGER_H_
> +#ifndef _FPGA_MANAGER_GEN5_H_
> +#define _FPGA_MANAGER_GEN5_H_
>
> -#include <altera.h>
> +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> +#define FPGAMGRREGS_STAT_MSEL_LSB 3
> +
> +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
> +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
> +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
> +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
> +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
> +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> +
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
> +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
> +
> +/* FPGA Mode */
> +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> +#define FPGAMGRREGS_MODE_INITPHASE 0x3
> +#define FPGAMGRREGS_MODE_USERMODE 0x4
> +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> +
> +#ifndef __ASSEMBLY__
>
> struct socfpga_fpga_manager {
> /* FPGA Manager Module */
> @@ -39,39 +63,6 @@ struct socfpga_fpga_manager {
> u32 gpio_config_reg1;
> };
>
> -#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> -#define FPGAMGRREGS_STAT_MSEL_LSB 3
> -
> -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
> -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
> -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
> -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
> -#define FPGAMGRREGS_CTRL_EN_MASK 0x1
> -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> -
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
> -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
> -
> -/* FPGA Mode */
> -#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> -#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> -#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> -#define FPGAMGRREGS_MODE_INITPHASE 0x3
> -#define FPGAMGRREGS_MODE_USERMODE 0x4
> -#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> -
> -/* FPGA CD Ratio Value */
> -#define CDRATIO_x1 0x0
> -#define CDRATIO_x2 0x1
> -#define CDRATIO_x4 0x2
> -#define CDRATIO_x8 0x3
> -
> -/* SoCFPGA support functions */
> -int fpgamgr_test_fpga_ready(void);
> -int fpgamgr_poll_fpga_ready(void);
> -int fpgamgr_get_mode(void);
> +#endif /* __ASSEMBLY__ */
>
> -#endif /* _FPGA_MANAGER_H_ */
> +#endif /* _FPGA_MANAGER_GEN5_H_ */
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 4a4b237..b4a2230 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> +obj-$(CONFIG_FPGA) += fpga/
> endif
>
> ifdef CONFIG_TPL_BUILD
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 777706f..b65e5ba 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> endif
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> index f1b2f2c..5200de7 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga.c
> @@ -14,23 +14,12 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -/* Timeout count */
> -#define FPGA_TIMEOUT_CNT 0x1000000
> +#define FPGA_TIMEOUT_CNT 0x1000000
>
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> -/* Set CD ratio */
> -static void fpgamgr_set_cd_ratio(unsigned long ratio)
> -{
> - clrsetbits_le32(&fpgamgr_regs->ctrl,
> - 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
> - (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
> -}
> -
> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> +int fpgamgr_dclkcnt_set(unsigned long cnt)
> {
> unsigned long i;
>
> @@ -53,98 +42,8 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt)
> return -ETIMEDOUT;
> }
>
> -/* Start the FPGA programming by initialize the FPGA Manager */
> -static int fpgamgr_program_init(void)
> -{
> - unsigned long msel, i;
> -
> - /* Get the MSEL value */
> - msel = readl(&fpgamgr_regs->stat);
> - msel &= FPGAMGRREGS_STAT_MSEL_MASK;
> - msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
> -
> - /*
> - * Set the cfg width
> - * If MSEL[3] = 1, cfg width = 32 bit
> - */
> - if (msel & 0x8) {
> - setbits_le32(&fpgamgr_regs->ctrl,
> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> -
> - /* To determine the CD ratio */
> - /* MSEL[1:0] = 0, CD Ratio = 1 */
> - if ((msel & 0x3) == 0x0)
> - fpgamgr_set_cd_ratio(CDRATIO_x1);
> - /* MSEL[1:0] = 1, CD Ratio = 4 */
> - else if ((msel & 0x3) == 0x1)
> - fpgamgr_set_cd_ratio(CDRATIO_x4);
> - /* MSEL[1:0] = 2, CD Ratio = 8 */
> - else if ((msel & 0x3) == 0x2)
> - fpgamgr_set_cd_ratio(CDRATIO_x8);
> -
> - } else { /* MSEL[3] = 0 */
> - clrbits_le32(&fpgamgr_regs->ctrl,
> - FPGAMGRREGS_CTRL_CFGWDTH_MASK);
> -
> - /* To determine the CD ratio */
> - /* MSEL[1:0] = 0, CD Ratio = 1 */
> - if ((msel & 0x3) == 0x0)
> - fpgamgr_set_cd_ratio(CDRATIO_x1);
> - /* MSEL[1:0] = 1, CD Ratio = 2 */
> - else if ((msel & 0x3) == 0x1)
> - fpgamgr_set_cd_ratio(CDRATIO_x2);
> - /* MSEL[1:0] = 2, CD Ratio = 4 */
> - else if ((msel & 0x3) == 0x2)
> - fpgamgr_set_cd_ratio(CDRATIO_x4);
> - }
> -
> - /* To enable FPGA Manager configuration */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
> -
> - /* To enable FPGA Manager drive over configuration line */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
> -
> - /* Put FPGA into reset phase */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> -
> - /* (1) wait until FPGA enter reset phase */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
> - break;
> - }
> -
> - /* If not in reset state, return error */
> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
> - puts("FPGA: Could not reset\n");
> - return -1;
> - }
> -
> - /* Release FPGA from reset phase */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
> -
> - /* (2) wait until FPGA enter configuration phase */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
> - break;
> - }
> -
> - /* If not in configuration state, return error */
> - if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
> - puts("FPGA: Could not configure\n");
> - return -2;
> - }
> -
> - /* Clear all interrupts in CB Monitor */
> - writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
> -
> - /* Enable AXI configuration */
> - setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> -
> - return 0;
> -}
> -
> /* Write the RBF data to FPGA Manager */
> -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
> +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
> {
> uint32_t src = (uint32_t)rbf_data;
> uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> @@ -169,136 +68,4 @@ static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
> "3: nop\n"
> : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
> : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
> -}
> -
> -/* Ensure the FPGA entering config done */
> -static int fpgamgr_program_poll_cd(void)
> -{
> - const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
> - FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
> - unsigned long reg, i;
> -
> - /* (3) wait until full config done */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - reg = readl(&fpgamgr_regs->gpio_ext_porta);
> -
> - /* Config error */
> - if (!(reg & mask)) {
> - printf("FPGA: Configuration error.\n");
> - return -3;
> - }
> -
> - /* Config done without error */
> - if (reg & mask)
> - break;
> - }
> -
> - /* Timeout happened, return error */
> - if (i == FPGA_TIMEOUT_CNT) {
> - printf("FPGA: Timeout waiting for program.\n");
> - return -4;
> - }
> -
> - /* Disable AXI configuration */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
> -
> - return 0;
> -}
> -
> -/* Ensure the FPGA entering init phase */
> -static int fpgamgr_program_poll_initphase(void)
> -{
> - unsigned long i;
> -
> - /* Additional clocks for the CB to enter initialization phase */
> - if (fpgamgr_dclkcnt_set(0x4))
> - return -5;
> -
> - /* (4) wait until FPGA enter init phase or user mode */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
> - break;
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
> - break;
> - }
> -
> - /* If not in configuration state, return error */
> - if (i == FPGA_TIMEOUT_CNT)
> - return -6;
> -
> - return 0;
> -}
> -
> -/* Ensure the FPGA entering user mode */
> -static int fpgamgr_program_poll_usermode(void)
> -{
> - unsigned long i;
> -
> - /* Additional clocks for the CB to exit initialization phase */
> - if (fpgamgr_dclkcnt_set(0x5000))
> - return -7;
> -
> - /* (5) wait until FPGA enter user mode */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
> - break;
> - }
> - /* If not in configuration state, return error */
> - if (i == FPGA_TIMEOUT_CNT)
> - return -8;
> -
> - /* To release FPGA Manager drive over configuration line */
> - clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
> -
> - return 0;
> -}
> -
> -/*
> - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> -int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> -{
> - unsigned long status;
> -
> - if ((uint32_t)rbf_data & 0x3) {
> - puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
> - return -EINVAL;
> - }
> -
> - /* Prior programming the FPGA, all bridges need to be shut off */
> -
> - /* Disable all signals from hps peripheral controller to fpga */
> - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> -
> - /* Disable all signals from FPGA to HPS SDRAM */
> -#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> - writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
> -
> - /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> - socfpga_bridges_reset(1);
> -
> - /* Unmap the bridges from NIC-301 */
> - writel(0x1, SOCFPGA_L3REGS_ADDRESS);
> -
> - /* Initialize the FPGA Manager */
> - status = fpgamgr_program_init();
> - if (status)
> - return status;
> -
> - /* Write the RBF data to FPGA Manager */
> - fpgamgr_program_write(rbf_data, rbf_size);
> -
> - /* Ensure the FPGA entering config done */
> - status = fpgamgr_program_poll_cd();
> - if (status)
> - return status;
> -
> - /* Ensure the FPGA entering init phase */
> - status = fpgamgr_program_poll_initphase();
> - if (status)
> - return status;
> -
> - /* Ensure the FPGA entering user mode */
> - return fpgamgr_program_poll_usermode();
> -}
> +}
> \ No newline at end of file
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
> similarity index 83%
> copy from drivers/fpga/socfpga.c
> copy to drivers/fpga/socfpga_gen5.c
> index f1b2f2c..3dfb030 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga_gen5.c
> @@ -14,8 +14,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -/* Timeout count */
> -#define FPGA_TIMEOUT_CNT 0x1000000
> +#define FPGA_TIMEOUT_CNT 0x1000000
>
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> @@ -30,29 +29,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
> (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
> }
>
> -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> -{
> - unsigned long i;
> -
> - /* Clear any existing done status */
> - if (readl(&fpgamgr_regs->dclkstat))
> - writel(0x1, &fpgamgr_regs->dclkstat);
> -
> - /* Write the dclkcnt */
> - writel(cnt, &fpgamgr_regs->dclkcnt);
> -
> - /* Wait till the dclkcnt done */
> - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> - if (!readl(&fpgamgr_regs->dclkstat))
> - continue;
> -
> - writel(0x1, &fpgamgr_regs->dclkstat);
> - return 0;
> - }
> -
> - return -ETIMEDOUT;
> -}
> -
> /* Start the FPGA programming by initialize the FPGA Manager */
> static int fpgamgr_program_init(void)
> {
> @@ -143,34 +119,6 @@ static int fpgamgr_program_init(void)
> return 0;
> }
>
> -/* Write the RBF data to FPGA Manager */
> -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
> -{
> - uint32_t src = (uint32_t)rbf_data;
> - uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> -
> - /* Number of loops for 32-byte long copying. */
> - uint32_t loops32 = rbf_size / 32;
> - /* Number of loops for 4-byte long copying + trailing bytes */
> - uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> -
> - asm volatile(
> - "1: ldmia %0!, {r0-r7}\n"
> - " stmia %1!, {r0-r7}\n"
> - " sub %1, #32\n"
> - " subs %2, #1\n"
> - " bne 1b\n"
> - " cmp %3, #0\n"
> - " beq 3f\n"
> - "2: ldr %2, [%0], #4\n"
> - " str %2, [%1]\n"
> - " subs %3, #1\n"
> - " bne 2b\n"
> - "3: nop\n"
> - : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
> - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
> -}
> -
> /* Ensure the FPGA entering config done */
> static int fpgamgr_program_poll_cd(void)
> {
> --
> 1.8.2.3
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10
2017-05-15 10:52 ` [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
@ 2017-05-17 8:49 ` Ley Foon Tan
2017-05-17 19:03 ` Dinh Nguyen
1 sibling, 0 replies; 14+ messages in thread
From: Ley Foon Tan @ 2017-05-17 8:49 UTC (permalink / raw)
To: u-boot
On Mon, May 15, 2017 at 6:52 PM, <tien.fong.chee@intel.com> wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Add FPGA driver support for Arria 10.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
> .../include/mach/fpga_manager_arria10.h | 100 +++++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/socfpga_arria10.c | 487 +++++++++++++++++++++
> include/configs/socfpga_common.h | 3 +-
> 5 files changed, 592 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> create mode 100644 drivers/fpga/socfpga_arria10.c
>
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> index b046c2c..a21c716 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> @@ -12,6 +12,8 @@
>
> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> #include <asm/arch/fpga_manager_gen5.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include <asm/arch/fpga_manager_arria10.h>
> #endif
>
> /* FPGA CD Ratio Value */
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> new file mode 100644
> index 0000000..18d9580
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + * All rights reserved.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef _FPGA_MANAGER_ARRIA10_H_
> +#define _FPGA_MANAGER_ARRIA10_H_
> +
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
> +
> +#ifndef __ASSEMBLY__
> +
> +struct socfpga_fpga_manager {
> + u32 _pad_0x0_0x7[2];
> + u32 dclkcnt;
> + u32 dclkstat;
> + u32 gpo;
> + u32 gpi;
> + u32 misci;
> + u32 _pad_0x1c_0x2f[5];
> + u32 emr_data0;
> + u32 emr_data1;
> + u32 emr_data2;
> + u32 emr_data3;
> + u32 emr_data4;
> + u32 emr_data5;
> + u32 emr_valid;
> + u32 emr_en;
> + u32 jtag_config;
> + u32 jtag_status;
> + u32 jtag_kick;
> + u32 _pad_0x5c_0x5f;
> + u32 jtag_data_w;
> + u32 jtag_data_r;
> + u32 _pad_0x68_0x6f[2];
> + u32 imgcfg_ctrl_00;
> + u32 imgcfg_ctrl_01;
> + u32 imgcfg_ctrl_02;
> + u32 _pad_0x7c_0x7f;
> + u32 imgcfg_stat;
> + u32 intr_masked_status;
> + u32 intr_mask;
> + u32 intr_polarity;
> + u32 dma_config;
> + u32 imgcfg_fifo_status;
> +};
> +
> +/* Functions */
> +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> +int fpgamgr_program_fini(void);
> +int is_fpgamgr_user_mode(void);
> +int fpgamgr_wait_early_user_mode(void);
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _FPGA_MANAGER_ARRIA10_H_ */
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index b65e5ba..08c9ff8 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
> endif
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> new file mode 100644
> index 0000000..262e962
> --- /dev/null
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -0,0 +1,487 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <asm/io.h>
> +#include <asm/arch/fpga_manager.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/misc.h>
> +#include <altera.h>
> +#include <common.h>
> +#include <errno.h>
> +#include <wait_bit.h>
> +#include <watchdog.h>
> +
> +#define CFGWDTH_32 1
> +#define MIN_BITSTREAM_SIZECHECK 230
> +#define ENCRYPTION_OFFSET 69
> +#define COMPRESSION_OFFSET 229
> +#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> +#define FPGA_TIMEOUT_CNT 0x1000000
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_fpga_manager *fpga_manager_base =
> + (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> +
> +static const struct socfpga_system_manager *system_manager_base =
> + (void *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +static void fpgamgr_set_cd_ratio(unsigned long ratio);
> +
> +static uint32_t fpgamgr_get_msel(void)
> +{
> + u32 reg;
> +
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
> +
> + return reg;
> +}
> +
> +static void fpgamgr_set_cfgwdth(int width)
> +{
> + if (width)
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> + else
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> +}
> +
> +/* Check whether FPGA Init_Done signal is high */
> +int is_fpgamgr_initdone_high(void)
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
> +}
> +
> +int is_fpgamgr_user_mode(void)
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
> +}
> +
> +static int wait_for_user_mode(void)
> +{
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
> + 1, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +static int is_fpgamgr_early_user_mode(void)
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
> +}
> +
> +int fpgamgr_wait_early_user_mode(void)
> +{
> + u32 sync_data = 0xffffffff;
> + u32 i = 0;
> + unsigned start = get_timer(0);
unsigned --> unsigned long
> + unsigned long cd_ratio;
> +
> + /* Getting existing CDRATIO */
> + cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
> +
> + /* Using CDRATIO_X1 for better compatibility */
> + fpgamgr_set_cd_ratio(CDRATIO_x1);
> +
> + while (!(is_fpgamgr_early_user_mode())) {
> + if (get_timer(start) > FPGA_TIMEOUT_MSEC)
> + return -ETIMEDOUT;
> + fpgamgr_program_write((const long unsigned int *)&sync_data,
> + sizeof(sync_data));
> + udelay(FPGA_TIMEOUT_MSEC);
> + i++;
> + }
> +
> + debug("Additional %i sync word needed\n", i);
> +
> + /* restoring original CDRATIO */
> + fpgamgr_set_cd_ratio(cd_ratio);
> +
> + return 0;
> +}
> +
> +/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
> +static int wait_for_nconfig_pin_and_nstatus_pin(void)
> +{
> + unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
> +
> + /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
> + * timeout at 1000ms
> + */
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + mask,
> + false, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +static int wait_for_f2s_nstatus_pin(unsigned long value)
> +{
> + /* Poll until f2s to specific value, timeout at 1000ms */
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
> + value, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +/* set CD ratio */
> +static void fpgamgr_set_cd_ratio(unsigned long ratio)
> +{
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> +
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> +}
> +
> +/* get the MSEL value, verify we are set for FPP configuration mode */
> +static int fpgamgr_verify_msel(void)
> +{
> + u32 msel = fpgamgr_get_msel();
> +
> + if ((msel != 0) && (msel != 1)) {
> + printf("Fail: read msel=%d\n", msel);
> + return -EPERM;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Write cdratio and cdwidth based on whether the bitstream is compressed
> + * and/or encoded
> + */
> +static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
> + size_t rbf_size)
> +{
> + unsigned int cd_ratio;
> + bool encrypt, compress;
> +
> + /*
> + * According to the bitstream specification,
> + * both encryption and compression status are
> + * in location before offset 230 of the buffer.
> + */
> + if (rbf_size < MIN_BITSTREAM_SIZECHECK)
> + return -EINVAL;
> +
> + encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
> + encrypt = encrypt != 0;
> +
> + compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
> + compress = !compress;
> +
> + debug("header word %d = %08x\n", 69, rbf_data[69]);
> + debug("header word %d = %08x\n", 229, rbf_data[229]);
> + debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
> +
> + /*
> + * from the register map description of cdratio in imgcfg_ctrl_02:
> + * Normal Configuration : 32bit Passive Parallel
> + * Partial Reconfiguration : 16bit Passive Parallel
> + */
> +
> + /*
> + * cd ratio is dependent on cfg width and whether the bitstream
> + * is encrypted and/or compressed.
> + *
> + * | width | encr. | compr. | cd ratio |
> + * | 16 | 0 | 0 | 1 |
> + * | 16 | 0 | 1 | 4 |
> + * | 16 | 1 | 0 | 2 |
> + * | 16 | 1 | 1 | 4 |
> + * | 32 | 0 | 0 | 1 |
> + * | 32 | 0 | 1 | 8 |
> + * | 32 | 1 | 0 | 4 |
> + * | 32 | 1 | 1 | 8 |
> + */
> + if (!compress && !encrypt) {
> + cd_ratio = CDRATIO_x1;
> + } else {
> + if (compress)
> + cd_ratio = CDRATIO_x4;
> + else
> + cd_ratio = CDRATIO_x2;
> +
> + /* if 32 bit, double the cd ratio (so register
> + field setting is incremented) */
> + if (cfg_width == CFGWDTH_32)
> + cd_ratio += 1;
> + }
> +
> + fpgamgr_set_cfgwdth(cfg_width);
> + fpgamgr_set_cd_ratio(cd_ratio);
> +
> + return 0;
> +}
> +
> +static int fpgamgr_reset(void)
> +{
> + unsigned long reg;
> +
> + /* S2F_NCONFIG = 0 */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + /* Wait for f2s_nstatus == 0 */
> + if (wait_for_f2s_nstatus_pin(0))
> + return -ETIME;
> +
> + /* S2F_NCONFIG = 1 */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + /* Wait for f2s_nstatus == 1 */
> + if (wait_for_f2s_nstatus_pin(1))
> + return -ETIME;
> +
> + /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
> + return -EPERM;
> +
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
> + return -EPERM;
> +
> + return 0;
> +}
> +
> +/* Start the FPGA programming by initialize the FPGA Manager */
> +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
> +{
> + int ret;
> +
> + /* Step 1 */
> + if (fpgamgr_verify_msel())
> + return -EPERM;
> +
> + /* Step 2 */
> + if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
> + return -EPERM;
> +
> + /*
> + * Step 3:
> + * Make sure no other external devices are trying to interfere with
> + * programming:
> + */
> + if (wait_for_nconfig_pin_and_nstatus_pin())
> + return -ETIME;
> +
> + /*
> + * Step 4:
> + * Deassert the signal drives from HPS
> + *
> + * S2F_NCE = 1
> + * S2F_PR_REQUEST = 0
> + * EN_CFG_CTRL = 0
> + * EN_CFG_DATA = 0
> + * S2F_NCONFIG = 1
> + * S2F_NSTATUS_OE = 0
> + * S2F_CONDONE_OE = 0
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
> +
> + /*
> + * Step 5:
> + * Enable overrides
> + * S2F_NENABLE_CONFIG = 0
> + * S2F_NENABLE_NCONFIG = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> +
> + /*
> + * Disable driving signals that HPS doesn't need to drive.
> + * S2F_NENABLE_NSTATUS = 1
> + * S2F_NENABLE_CONDONE = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
> +
> + /*
> + * Step 6:
> + * Drive chip select S2F_NCE = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + /* Step 7 */
> + if (wait_for_nconfig_pin_and_nstatus_pin())
> + return -ETIME;
> +
> + /* Step 8 */
> + ret = fpgamgr_reset();
> +
> + if (ret)
> + return ret;
> +
> + /*
> + * Step 9:
> + * EN_CFG_CTRL and EN_CFG_DATA = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + return 0;
> +}
> +
> +/* Ensure the FPGA entering config done */
> +static int fpgamgr_program_poll_cd(void)
> +{
> + unsigned long reg, i;
> +
> + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
> + return 0;
> +
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
> + printf("nstatus == 0 while waiting for condone\n");
> + return -EPERM;
> + }
> + }
> +
> + if (i == FPGA_TIMEOUT_CNT)
> + return -ETIME;
> +
> + return 0;
> +}
> +
> +/* Ensure the FPGA entering user mode */
> +static int fpgamgr_program_poll_usermode(void)
> +{
> + unsigned long reg;
> + int ret = 0;
> +
> + if (fpgamgr_dclkcnt_set(0xf))
> + return -ETIME;
> +
> + ret = wait_for_user_mode();
Remove extra new line here.
> +
> + if (ret < 0) {
> + printf("%s: Failed to enter user mode with ", __func__);
> + printf("error code %d\n", ret);
> + return ret;
> + }
> +
> + /*
> + * Step 14:
> + * Stop DATA path and Dclk
> + * EN_CFG_CTRL and EN_CFG_DATA = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + /*
> + * Step 15:
> + * Disable overrides
> + * S2F_NENABLE_CONFIG = 1
> + * S2F_NENABLE_NCONFIG = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> +
> + /* Disable chip select S2F_NCE = 1 */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + /*
> + * Step 16:
> + * Final check
> + */
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
> + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
> + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
> + return -EPERM;
> +
> + return 0;
> +}
> +
> +int fpgamgr_program_fini(void)
> +{
> + /* Ensure the FPGA entering config done */
> + int status = fpgamgr_program_poll_cd();
> +
> + if (status) {
> + printf("FPGA: Poll CD failed with error code %d\n", status);
> + return -EPERM;
> + }
> + WATCHDOG_RESET();
> +
> + /* Ensure the FPGA entering user mode */
> + status = fpgamgr_program_poll_usermode();
> + if (status) {
> + printf("FPGA: Poll usermode failed with error code %d\n",
> + status);
> + return -EPERM;
> + }
> +
> + printf("Full Configuration Succeeded.\n");
> +
> + return 0;
> +}
> +
> +/*
> + * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
> + * Return 0 for sucess, non-zero for error.
> + */
> +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> +{
> + unsigned long status;
> +
> + /* disable all signals from hps peripheral controller to fpga */
> + writel(0, &system_manager_base->fpgaintf_en_global);
> +
> + /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> + socfpga_bridges_reset();
> +
> + /* Initialize the FPGA Manager */
> + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> + if (status)
> + return status;
> +
> + /* Write the RBF data to FPGA Manager */
> + fpgamgr_program_write(rbf_data, rbf_size);
> +
> + return fpgamgr_program_fini();
> +}
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index da7e4ad..992097d 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -105,7 +105,8 @@
> /*
> * FPGA Driver
> */
> -#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || \
> + defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
Can remove switch here since both Gen5 and Arria 10 support FPGA now.
This will convert to Kconfig later too.
> #ifdef CONFIG_CMD_FPGA
> #define CONFIG_FPGA
> #define CONFIG_FPGA_ALTERA
> --
> 1.8.2.3
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
2017-05-15 10:52 ` [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
@ 2017-05-17 14:41 ` Dinh Nguyen
0 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2017-05-17 14:41 UTC (permalink / raw)
To: u-boot
minor nit
On 05/15/2017 05:52 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Remove parameter from socfpga_bridges_reset(), and keeping this function
> for single purpose which is just triggering reset on bridges.
> socfpga_reset_deasserte_bridges_handoff() can be called for releasing reset
s/socfpga_reset_deasserte_bridges_handoff/socfpga_reset_deassert_bridges_handoff
with fix above,
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-05-15 10:52 ` [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-05-17 8:21 ` Ley Foon Tan
@ 2017-05-17 18:37 ` Dinh Nguyen
1 sibling, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2017-05-17 18:37 UTC (permalink / raw)
To: u-boot
On 05/15/2017 05:52 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Move FPGA driver which is Gen5 specific code into Gen5 driver file
> and keeping common FPGA drivi er intact. All the changes are still keeping
> in driver/fpga/ and no functional change. Subsequent patch would move
> FPGA manager driver from arch/arm into driver/fpga/ .
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 2 +-
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 68 +-----
> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 +++---
> drivers/Makefile | 1 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/socfpga.c | 241 +--------------------
> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 54 +----
> 7 files changed, 50 insertions(+), 386 deletions(-)
> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)
>
[snip]
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 4a4b237..b4a2230 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> +obj-$(CONFIG_FPGA) += fpga/
You're adding the FPGA driver to SPL with this change. This should be
for Arria10 only right? It should be in a different patch.
Dinh
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver
2017-05-15 10:52 ` [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
@ 2017-05-17 18:45 ` Dinh Nguyen
0 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2017-05-17 18:45 UTC (permalink / raw)
To: u-boot
On 05/15/2017 05:52 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Move FPGA manager driver which is Gen5 specific code from arch/arm/
> into FPGA driver at driver/fpga/. No functional change.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 1 -
> arch/arm/mach-socfpga/fpga_manager.c | 78 ------------------------------------
> drivers/fpga/socfpga_gen5.c | 54 +++++++++++++++++++++++++
> 3 files changed, 54 insertions(+), 79 deletions(-)
> delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10
2017-05-15 10:52 ` [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
2017-05-17 8:49 ` Ley Foon Tan
@ 2017-05-17 19:03 ` Dinh Nguyen
2017-05-18 7:40 ` chee skywind
1 sibling, 1 reply; 14+ messages in thread
From: Dinh Nguyen @ 2017-05-17 19:03 UTC (permalink / raw)
To: u-boot
On 05/15/2017 05:52 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Add FPGA driver support for Arria 10.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
> .../include/mach/fpga_manager_arria10.h | 100 +++++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/socfpga_arria10.c | 487 +++++++++++++++++++++
> include/configs/socfpga_common.h | 3 +-
> 5 files changed, 592 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> create mode 100644 drivers/fpga/socfpga_arria10.c
>
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> index b046c2c..a21c716 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> @@ -12,6 +12,8 @@
>
> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> #include <asm/arch/fpga_manager_gen5.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include <asm/arch/fpga_manager_arria10.h>
> #endif
>
> /* FPGA CD Ratio Value */
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> new file mode 100644
> index 0000000..18d9580
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + * All rights reserved.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef _FPGA_MANAGER_ARRIA10_H_
> +#define _FPGA_MANAGER_ARRIA10_H_
> +
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
> +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
> +
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
> +
> +#ifndef __ASSEMBLY__
> +
> +struct socfpga_fpga_manager {
> + u32 _pad_0x0_0x7[2];
> + u32 dclkcnt;
> + u32 dclkstat;
> + u32 gpo;
> + u32 gpi;
> + u32 misci;
> + u32 _pad_0x1c_0x2f[5];
> + u32 emr_data0;
> + u32 emr_data1;
> + u32 emr_data2;
> + u32 emr_data3;
> + u32 emr_data4;
> + u32 emr_data5;
> + u32 emr_valid;
> + u32 emr_en;
> + u32 jtag_config;
> + u32 jtag_status;
> + u32 jtag_kick;
> + u32 _pad_0x5c_0x5f;
> + u32 jtag_data_w;
> + u32 jtag_data_r;
> + u32 _pad_0x68_0x6f[2];
> + u32 imgcfg_ctrl_00;
> + u32 imgcfg_ctrl_01;
> + u32 imgcfg_ctrl_02;
> + u32 _pad_0x7c_0x7f;
> + u32 imgcfg_stat;
> + u32 intr_masked_status;
> + u32 intr_mask;
> + u32 intr_polarity;
> + u32 dma_config;
> + u32 imgcfg_fifo_status;
> +};
> +
> +/* Functions */
> +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> +int fpgamgr_program_fini(void);
> +int is_fpgamgr_user_mode(void);
> +int fpgamgr_wait_early_user_mode(void);
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _FPGA_MANAGER_ARRIA10_H_ */
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index b65e5ba..08c9ff8 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
> endif
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> new file mode 100644
> index 0000000..262e962
> --- /dev/null
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -0,0 +1,487 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <asm/io.h>
> +#include <asm/arch/fpga_manager.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/misc.h>
> +#include <altera.h>
> +#include <common.h>
> +#include <errno.h>
> +#include <wait_bit.h>
> +#include <watchdog.h>
> +
> +#define CFGWDTH_32 1
> +#define MIN_BITSTREAM_SIZECHECK 230
> +#define ENCRYPTION_OFFSET 69
> +#define COMPRESSION_OFFSET 229
> +#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> +#define FPGA_TIMEOUT_CNT 0x1000000
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_fpga_manager *fpga_manager_base =
> + (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> +
> +static const struct socfpga_system_manager *system_manager_base =
> + (void *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +static void fpgamgr_set_cd_ratio(unsigned long ratio);
> +
> +static uint32_t fpgamgr_get_msel(void)
> +{
> + u32 reg;
> +
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
> +
> + return reg;
> +}
> +
> +static void fpgamgr_set_cfgwdth(int width)
> +{
> + if (width)
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> + else
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> +}
> +
> +/* Check whether FPGA Init_Done signal is high */
> +int is_fpgamgr_initdone_high(void)
static
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
> +}
> +
> +int is_fpgamgr_user_mode(void)
static
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
> +}
> +
> +static int wait_for_user_mode(void)
> +{
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
> + 1, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +static int is_fpgamgr_early_user_mode(void)
> +{
> + return (readl(&fpga_manager_base->imgcfg_stat) &
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
> +}
> +
> +int fpgamgr_wait_early_user_mode(void)
static ?
> +{
> + u32 sync_data = 0xffffffff;
> + u32 i = 0;
> + unsigned start = get_timer(0);
> + unsigned long cd_ratio;
> +
> + /* Getting existing CDRATIO */
> + cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
> +
> + /* Using CDRATIO_X1 for better compatibility */
> + fpgamgr_set_cd_ratio(CDRATIO_x1);
> +
> + while (!(is_fpgamgr_early_user_mode())) {
> + if (get_timer(start) > FPGA_TIMEOUT_MSEC)
> + return -ETIMEDOUT;
> + fpgamgr_program_write((const long unsigned int *)&sync_data,
> + sizeof(sync_data));
> + udelay(FPGA_TIMEOUT_MSEC);
> + i++;
> + }
> +
> + debug("Additional %i sync word needed\n", i);
> +
> + /* restoring original CDRATIO */
> + fpgamgr_set_cd_ratio(cd_ratio);
> +
> + return 0;
> +}
> +
> +/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
> +static int wait_for_nconfig_pin_and_nstatus_pin(void)
> +{
> + unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
> +
> + /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
> + * timeout at 1000ms
> + */
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + mask,
> + false, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +static int wait_for_f2s_nstatus_pin(unsigned long value)
> +{
> + /* Poll until f2s to specific value, timeout at 1000ms */
> + return wait_for_bit(__func__,
> + &fpga_manager_base->imgcfg_stat,
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
> + value, FPGA_TIMEOUT_MSEC, false);
> +}
> +
> +/* set CD ratio */
> +static void fpgamgr_set_cd_ratio(unsigned long ratio)
> +{
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> +
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
> + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> +}
> +
> +/* get the MSEL value, verify we are set for FPP configuration mode */
> +static int fpgamgr_verify_msel(void)
> +{
> + u32 msel = fpgamgr_get_msel();
> +
> + if ((msel != 0) && (msel != 1)) {
> + printf("Fail: read msel=%d\n", msel);
> + return -EPERM;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Write cdratio and cdwidth based on whether the bitstream is compressed
> + * and/or encoded
> + */
> +static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
> + size_t rbf_size)
> +{
> + unsigned int cd_ratio;
> + bool encrypt, compress;
> +
> + /*
> + * According to the bitstream specification,
> + * both encryption and compression status are
> + * in location before offset 230 of the buffer.
> + */
> + if (rbf_size < MIN_BITSTREAM_SIZECHECK)
> + return -EINVAL;
> +
> + encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
> + encrypt = encrypt != 0;
> +
> + compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
> + compress = !compress;
> +
> + debug("header word %d = %08x\n", 69, rbf_data[69]);
> + debug("header word %d = %08x\n", 229, rbf_data[229]);
> + debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
> +
> + /*
> + * from the register map description of cdratio in imgcfg_ctrl_02:
> + * Normal Configuration : 32bit Passive Parallel
> + * Partial Reconfiguration : 16bit Passive Parallel
> + */
> +
> + /*
> + * cd ratio is dependent on cfg width and whether the bitstream
> + * is encrypted and/or compressed.
> + *
> + * | width | encr. | compr. | cd ratio |
> + * | 16 | 0 | 0 | 1 |
> + * | 16 | 0 | 1 | 4 |
> + * | 16 | 1 | 0 | 2 |
> + * | 16 | 1 | 1 | 4 |
> + * | 32 | 0 | 0 | 1 |
> + * | 32 | 0 | 1 | 8 |
> + * | 32 | 1 | 0 | 4 |
> + * | 32 | 1 | 1 | 8 |
> + */
> + if (!compress && !encrypt) {
> + cd_ratio = CDRATIO_x1;
> + } else {
> + if (compress)
> + cd_ratio = CDRATIO_x4;
> + else
> + cd_ratio = CDRATIO_x2;
> +
> + /* if 32 bit, double the cd ratio (so register
> + field setting is incremented) */
> + if (cfg_width == CFGWDTH_32)
> + cd_ratio += 1;
> + }
> +
> + fpgamgr_set_cfgwdth(cfg_width);
> + fpgamgr_set_cd_ratio(cd_ratio);
> +
> + return 0;
> +}
> +
> +static int fpgamgr_reset(void)
> +{
> + unsigned long reg;
> +
> + /* S2F_NCONFIG = 0 */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + /* Wait for f2s_nstatus == 0 */
> + if (wait_for_f2s_nstatus_pin(0))
> + return -ETIME;
> +
> + /* S2F_NCONFIG = 1 */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + /* Wait for f2s_nstatus == 1 */
> + if (wait_for_f2s_nstatus_pin(1))
> + return -ETIME;
> +
> + /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
> + return -EPERM;
> +
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
> + return -EPERM;
> +
> + return 0;
> +}
> +
> +/* Start the FPGA programming by initialize the FPGA Manager */
> +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
> +{
> + int ret;
> +
> + /* Step 1 */
> + if (fpgamgr_verify_msel())
> + return -EPERM;
> +
> + /* Step 2 */
> + if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
> + return -EPERM;
> +
> + /*
> + * Step 3:
> + * Make sure no other external devices are trying to interfere with
> + * programming:
> + */
> + if (wait_for_nconfig_pin_and_nstatus_pin())
> + return -ETIME;
> +
> + /*
> + * Step 4:
> + * Deassert the signal drives from HPS
> + *
> + * S2F_NCE = 1
> + * S2F_PR_REQUEST = 0
> + * EN_CFG_CTRL = 0
> + * EN_CFG_DATA = 0
> + * S2F_NCONFIG = 1
> + * S2F_NSTATUS_OE = 0
> + * S2F_CONDONE_OE = 0
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> +
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
> +
> + /*
> + * Step 5:
> + * Enable overrides
> + * S2F_NENABLE_CONFIG = 0
> + * S2F_NENABLE_NCONFIG = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> +
> + /*
> + * Disable driving signals that HPS doesn't need to drive.
> + * S2F_NENABLE_NSTATUS = 1
> + * S2F_NENABLE_CONDONE = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
> +
> + /*
> + * Step 6:
> + * Drive chip select S2F_NCE = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + /* Step 7 */
> + if (wait_for_nconfig_pin_and_nstatus_pin())
> + return -ETIME;
> +
> + /* Step 8 */
> + ret = fpgamgr_reset();
> +
> + if (ret)
> + return ret;
> +
> + /*
> + * Step 9:
> + * EN_CFG_CTRL and EN_CFG_DATA = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + return 0;
> +}
> +
> +/* Ensure the FPGA entering config done */
> +static int fpgamgr_program_poll_cd(void)
> +{
> + unsigned long reg, i;
> +
> + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
> + return 0;
> +
> + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
> + printf("nstatus == 0 while waiting for condone\n");
> + return -EPERM;
> + }
> + }
> +
> + if (i == FPGA_TIMEOUT_CNT)
> + return -ETIME;
> +
> + return 0;
> +}
> +
> +/* Ensure the FPGA entering user mode */
> +static int fpgamgr_program_poll_usermode(void)
> +{
> + unsigned long reg;
> + int ret = 0;
> +
> + if (fpgamgr_dclkcnt_set(0xf))
> + return -ETIME;
> +
> + ret = wait_for_user_mode();
> +
> + if (ret < 0) {
> + printf("%s: Failed to enter user mode with ", __func__);
> + printf("error code %d\n", ret);
> + return ret;
> + }
> +
> + /*
> + * Step 14:
> + * Stop DATA path and Dclk
> + * EN_CFG_CTRL and EN_CFG_DATA = 0
> + */
> + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> +
> + /*
> + * Step 15:
> + * Disable overrides
> + * S2F_NENABLE_CONFIG = 1
> + * S2F_NENABLE_NCONFIG = 1
> + */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> +
> + /* Disable chip select S2F_NCE = 1 */
> + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> +
> + /*
> + * Step 16:
> + * Final check
> + */
> + reg = readl(&fpga_manager_base->imgcfg_stat);
> + if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
> + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
> + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
> + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
> + return -EPERM;
> +
> + return 0;
> +}
> +
> +int fpgamgr_program_fini(void)
static and how about fpgamgr_program_finish()?
> +{
> + /* Ensure the FPGA entering config done */
> + int status = fpgamgr_program_poll_cd();
> +
> + if (status) {
> + printf("FPGA: Poll CD failed with error code %d\n", status);
> + return -EPERM;
> + }
> + WATCHDOG_RESET();
> +
> + /* Ensure the FPGA entering user mode */
> + status = fpgamgr_program_poll_usermode();
> + if (status) {
> + printf("FPGA: Poll usermode failed with error code %d\n",
> + status);
> + return -EPERM;
> + }
> +
> + printf("Full Configuration Succeeded.\n");
> +
> + return 0;
> +}
> +
> +/*
> + * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
> + * Return 0 for sucess, non-zero for error.
> + */
> +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> +{
> + unsigned long status;
> +
> + /* disable all signals from hps peripheral controller to fpga */
> + writel(0, &system_manager_base->fpgaintf_en_global);
> +
> + /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> + socfpga_bridges_reset();
> +
> + /* Initialize the FPGA Manager */
> + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> + if (status)
> + return status;
> +
> + /* Write the RBF data to FPGA Manager */
> + fpgamgr_program_write(rbf_data, rbf_size);
> +
> + return fpgamgr_program_fini();
> +}
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index da7e4ad..992097d 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -105,7 +105,8 @@
> /*
> * FPGA Driver
> */
> -#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || \
> + defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
I don't think there's a need for the above wrappers at all.
Dinh
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10
2017-05-17 19:03 ` Dinh Nguyen
@ 2017-05-18 7:40 ` chee skywind
0 siblings, 0 replies; 14+ messages in thread
From: chee skywind @ 2017-05-18 7:40 UTC (permalink / raw)
To: u-boot
On Thu, May 18, 2017 at 3:03 AM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
> On 05/15/2017 05:52 AM, tien.fong.chee at intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Add FPGA driver support for Arria 10.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
> > .../include/mach/fpga_manager_arria10.h | 100 +++++
> > drivers/fpga/Makefile | 1 +
> > drivers/fpga/socfpga_arria10.c | 487
> +++++++++++++++++++++
> > include/configs/socfpga_common.h | 3 +-
> > 5 files changed, 592 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/mach-socfpga/include/
> mach/fpga_manager_arria10.h
> > create mode 100644 drivers/fpga/socfpga_arria10.c
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > index b046c2c..a21c716 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > @@ -12,6 +12,8 @@
> >
> > #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > #include <asm/arch/fpga_manager_gen5.h>
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include <asm/arch/fpga_manager_arria10.h>
> > #endif
> >
> > /* FPGA CD Ratio Value */
> > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > new file mode 100644
> > index 0000000..18d9580
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -0,0 +1,100 @@
> > +/*
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + * All rights reserved.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#ifndef _FPGA_MANAGER_ARRIA10_H_
> > +#define _FPGA_MANAGER_ARRIA10_H_
> > +
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK
> BIT(0)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
> BIT(2)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
> BIT(4)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK
> BIT(5)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
> BIT(6)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK
> BIT(7)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK
> BIT(12)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK
> BIT(16)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK
> BIT(17)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK
> BIT(18)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK
> BIT(29)
> > +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
> > +
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK
> BIT(0)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK
> BIT(1)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK
> BIT(2)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
> BIT(8)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
> > +
> > +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
> > +
> > +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
> 0x00030000
> > +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> > +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +struct socfpga_fpga_manager {
> > + u32 _pad_0x0_0x7[2];
> > + u32 dclkcnt;
> > + u32 dclkstat;
> > + u32 gpo;
> > + u32 gpi;
> > + u32 misci;
> > + u32 _pad_0x1c_0x2f[5];
> > + u32 emr_data0;
> > + u32 emr_data1;
> > + u32 emr_data2;
> > + u32 emr_data3;
> > + u32 emr_data4;
> > + u32 emr_data5;
> > + u32 emr_valid;
> > + u32 emr_en;
> > + u32 jtag_config;
> > + u32 jtag_status;
> > + u32 jtag_kick;
> > + u32 _pad_0x5c_0x5f;
> > + u32 jtag_data_w;
> > + u32 jtag_data_r;
> > + u32 _pad_0x68_0x6f[2];
> > + u32 imgcfg_ctrl_00;
> > + u32 imgcfg_ctrl_01;
> > + u32 imgcfg_ctrl_02;
> > + u32 _pad_0x7c_0x7f;
> > + u32 imgcfg_stat;
> > + u32 intr_masked_status;
> > + u32 intr_mask;
> > + u32 intr_polarity;
> > + u32 dma_config;
> > + u32 imgcfg_fifo_status;
> > +};
> > +
> > +/* Functions */
> > +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > +int fpgamgr_program_fini(void);
> > +int is_fpgamgr_user_mode(void);
> > +int fpgamgr_wait_early_user_mode(void);
> > +
> > +#endif /* __ASSEMBLY__ */
> > +
> > +#endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index b65e5ba..08c9ff8 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> > obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
> > endif
> > diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_
> arria10.c
> > new file mode 100644
> > index 0000000..262e962
> > --- /dev/null
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -0,0 +1,487 @@
> > +/*
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include <asm/io.h>
> > +#include <asm/arch/fpga_manager.h>
> > +#include <asm/arch/reset_manager.h>
> > +#include <asm/arch/system_manager.h>
> > +#include <asm/arch/sdram.h>
> > +#include <asm/arch/misc.h>
> > +#include <altera.h>
> > +#include <common.h>
> > +#include <errno.h>
> > +#include <wait_bit.h>
> > +#include <watchdog.h>
> > +
> > +#define CFGWDTH_32 1
> > +#define MIN_BITSTREAM_SIZECHECK 230
> > +#define ENCRYPTION_OFFSET 69
> > +#define COMPRESSION_OFFSET 229
> > +#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > +#define FPGA_TIMEOUT_CNT 0x1000000
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct socfpga_fpga_manager *fpga_manager_base =
> > + (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > +
> > +static const struct socfpga_system_manager *system_manager_base =
> > + (void *)SOCFPGA_SYSMGR_ADDRESS;
> > +
> > +static void fpgamgr_set_cd_ratio(unsigned long ratio);
> > +
> > +static uint32_t fpgamgr_get_msel(void)
> > +{
> > + u32 reg;
> > +
> > + reg = readl(&fpga_manager_base->imgcfg_stat);
> > + reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
> > +
> > + return reg;
> > +}
> > +
> > +static void fpgamgr_set_cfgwdth(int width)
> > +{
> > + if (width)
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> > + else
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
> > +}
> > +
> > +/* Check whether FPGA Init_Done signal is high */
> > +int is_fpgamgr_initdone_high(void)
>
> static
>
> Okay
> > +{
> > + return (readl(&fpga_manager_base->imgcfg_stat) &
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
> > +}
> > +
> > +int is_fpgamgr_user_mode(void)
>
> static
>
> This function will be exposed to other file in later patch.
> +{
> > + return (readl(&fpga_manager_base->imgcfg_stat) &
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
> > +}
> > +
> > +static int wait_for_user_mode(void)
> > +{
> > + return wait_for_bit(__func__,
> > + &fpga_manager_base->imgcfg_stat,
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
> > + 1, FPGA_TIMEOUT_MSEC, false);
> > +}
> > +
> > +static int is_fpgamgr_early_user_mode(void)
> > +{
> > + return (readl(&fpga_manager_base->imgcfg_stat) &
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
> > +}
> > +
> > +int fpgamgr_wait_early_user_mode(void)
>
> static ?
>
> This function will be exposed to other file in later patch.
> > +{
> > + u32 sync_data = 0xffffffff;
> > + u32 i = 0;
> > + unsigned start = get_timer(0);
> > + unsigned long cd_ratio;
> > +
> > + /* Getting existing CDRATIO */
> > + cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
> > +
> > + /* Using CDRATIO_X1 for better compatibility */
> > + fpgamgr_set_cd_ratio(CDRATIO_x1);
> > +
> > + while (!(is_fpgamgr_early_user_mode())) {
> > + if (get_timer(start) > FPGA_TIMEOUT_MSEC)
> > + return -ETIMEDOUT;
> > + fpgamgr_program_write((const long unsigned int
> *)&sync_data,
> > + sizeof(sync_data));
> > + udelay(FPGA_TIMEOUT_MSEC);
> > + i++;
> > + }
> > +
> > + debug("Additional %i sync word needed\n", i);
> > +
> > + /* restoring original CDRATIO */
> > + fpgamgr_set_cd_ratio(cd_ratio);
> > +
> > + return 0;
> > +}
> > +
> > +/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
> > +static int wait_for_nconfig_pin_and_nstatus_pin(void)
> > +{
> > + unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK
> |
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_
> NSTATUS_PIN_SET_MSK;
> > +
> > + /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
> de-asserted,
> > + * timeout at 1000ms
> > + */
> > + return wait_for_bit(__func__,
> > + &fpga_manager_base->imgcfg_stat,
> > + mask,
> > + false, FPGA_TIMEOUT_MSEC, false);
> > +}
> > +
> > +static int wait_for_f2s_nstatus_pin(unsigned long value)
> > +{
> > + /* Poll until f2s to specific value, timeout at 1000ms */
> > + return wait_for_bit(__func__,
> > + &fpga_manager_base->imgcfg_stat,
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_
> NSTATUS_PIN_SET_MSK,
> > + value, FPGA_TIMEOUT_MSEC, false);
> > +}
> > +
> > +/* set CD ratio */
> > +static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > +{
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> > +
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
> > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
> > +}
> > +
> > +/* get the MSEL value, verify we are set for FPP configuration mode */
> > +static int fpgamgr_verify_msel(void)
> > +{
> > + u32 msel = fpgamgr_get_msel();
> > +
> > + if ((msel != 0) && (msel != 1)) {
> > + printf("Fail: read msel=%d\n", msel);
> > + return -EPERM;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Write cdratio and cdwidth based on whether the bitstream is
> compressed
> > + * and/or encoded
> > + */
> > +static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32
> *rbf_data,
> > + size_t rbf_size)
> > +{
> > + unsigned int cd_ratio;
> > + bool encrypt, compress;
> > +
> > + /*
> > + * According to the bitstream specification,
> > + * both encryption and compression status are
> > + * in location before offset 230 of the buffer.
> > + */
> > + if (rbf_size < MIN_BITSTREAM_SIZECHECK)
> > + return -EINVAL;
> > +
> > + encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
> > + encrypt = encrypt != 0;
> > +
> > + compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
> > + compress = !compress;
> > +
> > + debug("header word %d = %08x\n", 69, rbf_data[69]);
> > + debug("header word %d = %08x\n", 229, rbf_data[229]);
> > + debug("read from rbf header: encrypt=%d compress=%d\n", encrypt,
> compress);
> > +
> > + /*
> > + * from the register map description of cdratio in imgcfg_ctrl_02:
> > + * Normal Configuration : 32bit Passive Parallel
> > + * Partial Reconfiguration : 16bit Passive Parallel
> > + */
> > +
> > + /*
> > + * cd ratio is dependent on cfg width and whether the bitstream
> > + * is encrypted and/or compressed.
> > + *
> > + * | width | encr. | compr. | cd ratio |
> > + * | 16 | 0 | 0 | 1 |
> > + * | 16 | 0 | 1 | 4 |
> > + * | 16 | 1 | 0 | 2 |
> > + * | 16 | 1 | 1 | 4 |
> > + * | 32 | 0 | 0 | 1 |
> > + * | 32 | 0 | 1 | 8 |
> > + * | 32 | 1 | 0 | 4 |
> > + * | 32 | 1 | 1 | 8 |
> > + */
> > + if (!compress && !encrypt) {
> > + cd_ratio = CDRATIO_x1;
> > + } else {
> > + if (compress)
> > + cd_ratio = CDRATIO_x4;
> > + else
> > + cd_ratio = CDRATIO_x2;
> > +
> > + /* if 32 bit, double the cd ratio (so register
> > + field setting is incremented) */
> > + if (cfg_width == CFGWDTH_32)
> > + cd_ratio += 1;
> > + }
> > +
> > + fpgamgr_set_cfgwdth(cfg_width);
> > + fpgamgr_set_cd_ratio(cd_ratio);
> > +
> > + return 0;
> > +}
> > +
> > +static int fpgamgr_reset(void)
> > +{
> > + unsigned long reg;
> > +
> > + /* S2F_NCONFIG = 0 */
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> > +
> > + /* Wait for f2s_nstatus == 0 */
> > + if (wait_for_f2s_nstatus_pin(0))
> > + return -ETIME;
> > +
> > + /* S2F_NCONFIG = 1 */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> > +
> > + /* Wait for f2s_nstatus == 1 */
> > + if (wait_for_f2s_nstatus_pin(1))
> > + return -ETIME;
> > +
> > + /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
> > + reg = readl(&fpga_manager_base->imgcfg_stat);
> > + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
> > + return -EPERM;
> > +
> > + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
> > + return -EPERM;
> > +
> > + return 0;
> > +}
> > +
> > +/* Start the FPGA programming by initialize the FPGA Manager */
> > +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
> > +{
> > + int ret;
> > +
> > + /* Step 1 */
> > + if (fpgamgr_verify_msel())
> > + return -EPERM;
> > +
> > + /* Step 2 */
> > + if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
> > + return -EPERM;
> > +
> > + /*
> > + * Step 3:
> > + * Make sure no other external devices are trying to interfere with
> > + * programming:
> > + */
> > + if (wait_for_nconfig_pin_and_nstatus_pin())
> > + return -ETIME;
> > +
> > + /*
> > + * Step 4:
> > + * Deassert the signal drives from HPS
> > + *
> > + * S2F_NCE = 1
> > + * S2F_PR_REQUEST = 0
> > + * EN_CFG_CTRL = 0
> > + * EN_CFG_DATA = 0
> > + * S2F_NCONFIG = 1
> > + * S2F_NSTATUS_OE = 0
> > + * S2F_CONDONE_OE = 0
> > + */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> > +
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
> > +
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> > +
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
> > +
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
> > +
> > + /*
> > + * Step 5:
> > + * Enable overrides
> > + * S2F_NENABLE_CONFIG = 0
> > + * S2F_NENABLE_NCONFIG = 0
> > + */
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> > +
> > + /*
> > + * Disable driving signals that HPS doesn't need to drive.
> > + * S2F_NENABLE_NSTATUS = 1
> > + * S2F_NENABLE_CONDONE = 1
> > + */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
> > +
> > + /*
> > + * Step 6:
> > + * Drive chip select S2F_NCE = 0
> > + */
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> > +
> > + /* Step 7 */
> > + if (wait_for_nconfig_pin_and_nstatus_pin())
> > + return -ETIME;
> > +
> > + /* Step 8 */
> > + ret = fpgamgr_reset();
> > +
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * Step 9:
> > + * EN_CFG_CTRL and EN_CFG_DATA = 1
> > + */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> > +
> > + return 0;
> > +}
> > +
> > +/* Ensure the FPGA entering config done */
> > +static int fpgamgr_program_poll_cd(void)
> > +{
> > + unsigned long reg, i;
> > +
> > + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > + reg = readl(&fpga_manager_base->imgcfg_stat);
> > + if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
> > + return 0;
> > +
> > + if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK)
> == 0) {
> > + printf("nstatus == 0 while waiting for condone\n");
> > + return -EPERM;
> > + }
> > + }
> > +
> > + if (i == FPGA_TIMEOUT_CNT)
> > + return -ETIME;
> > +
> > + return 0;
> > +}
> > +
> > +/* Ensure the FPGA entering user mode */
> > +static int fpgamgr_program_poll_usermode(void)
> > +{
> > + unsigned long reg;
> > + int ret = 0;
> > +
> > + if (fpgamgr_dclkcnt_set(0xf))
> > + return -ETIME;
> > +
> > + ret = wait_for_user_mode();
> > +
> > + if (ret < 0) {
> > + printf("%s: Failed to enter user mode with ", __func__);
> > + printf("error code %d\n", ret);
> > + return ret;
> > + }
> > +
> > + /*
> > + * Step 14:
> > + * Stop DATA path and Dclk
> > + * EN_CFG_CTRL and EN_CFG_DATA = 0
> > + */
> > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
> > + ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
> > +
> > + /*
> > + * Step 15:
> > + * Disable overrides
> > + * S2F_NENABLE_CONFIG = 1
> > + * S2F_NENABLE_NCONFIG = 1
> > + */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
> > + ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
> > +
> > + /* Disable chip select S2F_NCE = 1 */
> > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
> > + ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
> > +
> > + /*
> > + * Step 16:
> > + * Final check
> > + */
> > + reg = readl(&fpga_manager_base->imgcfg_stat);
> > + if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
> > + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
> > + ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
> > + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
> > + return -EPERM;
> > +
> > + return 0;
> > +}
> > +
> > +int fpgamgr_program_fini(void)
>
> static and how about fpgamgr_program_finish()?
>
> This function will be exposed to other file in later patch. I can change
to finish.
> > +{
> > + /* Ensure the FPGA entering config done */
> > + int status = fpgamgr_program_poll_cd();
> > +
> > + if (status) {
> > + printf("FPGA: Poll CD failed with error code %d\n",
> status);
> > + return -EPERM;
> > + }
> > + WATCHDOG_RESET();
> > +
> > + /* Ensure the FPGA entering user mode */
> > + status = fpgamgr_program_poll_usermode();
> > + if (status) {
> > + printf("FPGA: Poll usermode failed with error code %d\n",
> > + status);
> > + return -EPERM;
> > + }
> > +
> > + printf("Full Configuration Succeeded.\n");
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * FPGA Manager to program the FPGA. This is the interface used by FPGA
> driver.
> > + * Return 0 for sucess, non-zero for error.
> > + */
> > +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> rbf_size)
> > +{
> > + unsigned long status;
> > +
> > + /* disable all signals from hps peripheral controller to fpga */
> > + writel(0, &system_manager_base->fpgaintf_en_global);
> > +
> > + /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> > + socfpga_bridges_reset();
> > +
> > + /* Initialize the FPGA Manager */
> > + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > + if (status)
> > + return status;
> > +
> > + /* Write the RBF data to FPGA Manager */
> > + fpgamgr_program_write(rbf_data, rbf_size);
> > +
> > + return fpgamgr_program_fini();
> > +}
> > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_
> common.h
> > index da7e4ad..992097d 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -105,7 +105,8 @@
> > /*
> > * FPGA Driver
> > */
> > -#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || \
> > + defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>
> I don't think there's a need for the above wrappers at all.
>
> Okay
> Dinh
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-05-18 7:40 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-05-15 10:52 [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-15 10:52 ` [U-Boot] [PATCH v3 1/4] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-05-17 14:41 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-05-17 8:21 ` Ley Foon Tan
2017-05-17 18:37 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 3/4] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
2017-05-17 18:45 ` Dinh Nguyen
2017-05-15 10:52 ` [U-Boot] [PATCH v3 4/4] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
2017-05-17 8:49 ` Ley Foon Tan
2017-05-17 19:03 ` Dinh Nguyen
2017-05-18 7:40 ` chee skywind
2017-05-17 5:12 ` [U-Boot] [PATCH v3 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
2017-05-17 7:24 ` Marek Vasut
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