* [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK
@ 2017-05-08 8:50 Ander Conselvan de Oliveira
2017-05-08 9:07 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-05-24 8:27 ` [PATCH] " Mahesh Kumar
0 siblings, 2 replies; 5+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-05-08 8:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
In Geminilake, a FIFO underrun happens the first time a pipe scaler is
enabled after boot/resume from suspend. Disabling DPF clock gating in
the respective CLKGATE_DIS_PSL register prior to enabling the scaler
works around the issue.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 524fdfd..3157c39 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3424,6 +3424,14 @@ enum {
#define PWM2_GATING_DIS (1 << 14)
#define PWM1_GATING_DIS (1 << 13)
+#define _CLKGATE_DIS_PSL_A 0x46520
+#define _CLKGATE_DIS_PSL_B 0x46524
+#define _CLKGATE_DIS_PSL_C 0x46528
+#define DPF_GATING_DIS (1 << 10)
+
+#define CLKGATE_DIS_PSL(pipe) \
+ _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
+
/*
* Display engine regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 85b9e2f5..c24acdd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
static void skl_detach_scalers(struct intel_crtc *intel_crtc)
{
struct intel_crtc_scaler_state *scaler_state;
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
int i;
scaler_state = &intel_crtc->config->scaler_state;
@@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
if (!scaler_state->scalers[i].in_use)
skl_detach_scaler(intel_crtc, i);
}
+
+ if (IS_GEMINILAKE(dev_priv)) {
+ u32 tmp;
+
+ tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe));
+ tmp &= ~DPF_GATING_DIS;
+ I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp);
+ }
}
u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
@@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
return;
+ if (IS_GEMINILAKE(dev_priv)) {
+ u32 tmp;
+
+ tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe));
+ tmp |= DPF_GATING_DIS;
+ I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp);
+ }
+
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
--
2.9.3
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^ permalink raw reply related [flat|nested] 5+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Work around for underrun when enabling pipe scaler in GLK
2017-05-08 8:50 [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK Ander Conselvan de Oliveira
@ 2017-05-08 9:07 ` Patchwork
2017-05-24 8:27 ` [PATCH] " Mahesh Kumar
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-05-08 9:07 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Work around for underrun when enabling pipe scaler in GLK
URL : https://patchwork.freedesktop.org/series/24100/
State : success
== Summary ==
Series 24100v1 drm/i915: Work around for underrun when enabling pipe scaler in GLK
https://patchwork.freedesktop.org/api/1.0/series/24100/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (fi-bsw-n3050) fdo#100651
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#100651 https://bugs.freedesktop.org/show_bug.cgi?id=100651
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:433s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:587s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:504s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time:553s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:479s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:486s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:409s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:402s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:419s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:498s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:488s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time:570s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:459s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:567s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:456s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:483s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:429s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:527s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:410s
fi-bdw-gvtdvm failed to collect. IGT log at Patchwork_4638/fi-bdw-gvtdvm/igt.log
6e119470388e1434ebfa58125c571c711573f8ad drm-tip: 2017y-05m-08d-08h-22m-53s UTC integration manifest
b4bba5f drm/i915: Work around for underrun when enabling pipe scaler in GLK
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4638/
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK
2017-05-08 8:50 [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK Ander Conselvan de Oliveira
2017-05-08 9:07 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-05-24 8:27 ` Mahesh Kumar
2017-05-24 11:38 ` Ander Conselvan De Oliveira
1 sibling, 1 reply; 5+ messages in thread
From: Mahesh Kumar @ 2017-05-24 8:27 UTC (permalink / raw)
To: Ander Conselvan de Oliveira, intel-gfx
Hi,
On Monday 08 May 2017 02:20 PM, Ander Conselvan de Oliveira wrote:
> In Geminilake, a FIFO underrun happens the first time a pipe scaler is
> enabled after boot/resume from suspend. Disabling DPF clock gating in
> the respective CLKGATE_DIS_PSL register prior to enabling the scaler
> works around the issue.
Is BSpec link or workaround number available for this?
-Mahesh
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 524fdfd..3157c39 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3424,6 +3424,14 @@ enum {
> #define PWM2_GATING_DIS (1 << 14)
> #define PWM1_GATING_DIS (1 << 13)
>
> +#define _CLKGATE_DIS_PSL_A 0x46520
> +#define _CLKGATE_DIS_PSL_B 0x46524
> +#define _CLKGATE_DIS_PSL_C 0x46528
> +#define DPF_GATING_DIS (1 << 10)
> +
> +#define CLKGATE_DIS_PSL(pipe) \
> + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
> +
> /*
> * Display engine regs
> */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 85b9e2f5..c24acdd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> {
> struct intel_crtc_scaler_state *scaler_state;
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> int i;
>
> scaler_state = &intel_crtc->config->scaler_state;
> @@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> if (!scaler_state->scalers[i].in_use)
> skl_detach_scaler(intel_crtc, i);
> }
> +
> + if (IS_GEMINILAKE(dev_priv)) {
> + u32 tmp;
> +
> + tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe));
> + tmp &= ~DPF_GATING_DIS;
> + I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp);
> + }
> }
>
> u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> @@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
> if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
> return;
>
> + if (IS_GEMINILAKE(dev_priv)) {
> + u32 tmp;
> +
> + tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe));
> + tmp |= DPF_GATING_DIS;
> + I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp);
> + }
> +
> id = scaler_state->scaler_id;
> I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK
2017-05-24 8:27 ` [PATCH] " Mahesh Kumar
@ 2017-05-24 11:38 ` Ander Conselvan De Oliveira
2017-05-25 7:59 ` Mahesh Kumar
0 siblings, 1 reply; 5+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-05-24 11:38 UTC (permalink / raw)
To: Mahesh Kumar, intel-gfx
On Wed, 2017-05-24 at 13:57 +0530, Mahesh Kumar wrote:
> Hi,
>
>
> On Monday 08 May 2017 02:20 PM, Ander Conselvan de Oliveira wrote:
> > In Geminilake, a FIFO underrun happens the first time a pipe scaler is
> > enabled after boot/resume from suspend. Disabling DPF clock gating in
> > the respective CLKGATE_DIS_PSL register prior to enabling the scaler
> > works around the issue.
>
> Is BSpec link or workaround number available for this?
This is not a documented workaround yet, still need input from hw engineers.
Ander
>
> -Mahesh
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
> > 2 files changed, 25 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 524fdfd..3157c39 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3424,6 +3424,14 @@ enum {
> > #define PWM2_GATING_DIS (1 << 14)
> > #define PWM1_GATING_DIS (1 << 13)
> >
> > +#define _CLKGATE_DIS_PSL_A 0x46520
> > +#define _CLKGATE_DIS_PSL_B 0x46524
> > +#define _CLKGATE_DIS_PSL_C 0x46528
> > +#define DPF_GATING_DIS (1 << 10)
> > +
> > +#define CLKGATE_DIS_PSL(pipe) \
> > + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
> > +
> > /*
> > * Display engine regs
> > */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 85b9e2f5..c24acdd 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> > static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> > {
> > struct intel_crtc_scaler_state *scaler_state;
> > + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> > int i;
> >
> > scaler_state = &intel_crtc->config->scaler_state;
> > @@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> > if (!scaler_state->scalers[i].in_use)
> > skl_detach_scaler(intel_crtc, i);
> > }
> > +
> > + if (IS_GEMINILAKE(dev_priv)) {
> > + u32 tmp;
> > +
> > + tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe));
> > + tmp &= ~DPF_GATING_DIS;
> > + I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp);
> > + }
> > }
> >
> > u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> > @@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
> > if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
> > return;
> >
> > + if (IS_GEMINILAKE(dev_priv)) {
> > + u32 tmp;
> > +
> > + tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe));
> > + tmp |= DPF_GATING_DIS;
> > + I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp);
> > + }
> > +
> > id = scaler_state->scaler_id;
> > I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
>
>
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK
2017-05-24 11:38 ` Ander Conselvan De Oliveira
@ 2017-05-25 7:59 ` Mahesh Kumar
0 siblings, 0 replies; 5+ messages in thread
From: Mahesh Kumar @ 2017-05-25 7:59 UTC (permalink / raw)
To: Ander Conselvan De Oliveira, intel-gfx
Hi,
On Wednesday 24 May 2017 05:08 PM, Ander Conselvan De Oliveira wrote:
> On Wed, 2017-05-24 at 13:57 +0530, Mahesh Kumar wrote:
>> Hi,
>>
>>
>> On Monday 08 May 2017 02:20 PM, Ander Conselvan de Oliveira wrote:
>>> In Geminilake, a FIFO underrun happens the first time a pipe scaler is
>>> enabled after boot/resume from suspend. Disabling DPF clock gating in
>>> the respective CLKGATE_DIS_PSL register prior to enabling the scaler
>>> works around the issue.
>> Is BSpec link or workaround number available for this?
> This is not a documented workaround yet, still need input from hw engineers.
Let's wait for final WA confirmation from HW engineers.
-Mahesh
>
> Ander
>
>
>> -Mahesh
>>> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>>> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
>>> 2 files changed, 25 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 524fdfd..3157c39 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -3424,6 +3424,14 @@ enum {
>>> #define PWM2_GATING_DIS (1 << 14)
>>> #define PWM1_GATING_DIS (1 << 13)
>>>
>>> +#define _CLKGATE_DIS_PSL_A 0x46520
>>> +#define _CLKGATE_DIS_PSL_B 0x46524
>>> +#define _CLKGATE_DIS_PSL_C 0x46528
>>> +#define DPF_GATING_DIS (1 << 10)
>>> +
>>> +#define CLKGATE_DIS_PSL(pipe) \
>>> + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
>>> +
>>> /*
>>> * Display engine regs
>>> */
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 85b9e2f5..c24acdd 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
>>> static void skl_detach_scalers(struct intel_crtc *intel_crtc)
>>> {
>>> struct intel_crtc_scaler_state *scaler_state;
>>> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>>> int i;
>>>
>>> scaler_state = &intel_crtc->config->scaler_state;
>>> @@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
>>> if (!scaler_state->scalers[i].in_use)
>>> skl_detach_scaler(intel_crtc, i);
>>> }
>>> +
>>> + if (IS_GEMINILAKE(dev_priv)) {
>>> + u32 tmp;
>>> +
>>> + tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe));
>>> + tmp &= ~DPF_GATING_DIS;
>>> + I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp);
>>> + }
>>> }
>>>
>>> u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
>>> @@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
>>> if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
>>> return;
>>>
>>> + if (IS_GEMINILAKE(dev_priv)) {
>>> + u32 tmp;
>>> +
>>> + tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe));
>>> + tmp |= DPF_GATING_DIS;
>>> + I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp);
>>> + }
>>> +
>>> id = scaler_state->scaler_id;
>>> I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
>>> PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
>>
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-05-25 7:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2017-05-08 8:50 [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK Ander Conselvan de Oliveira
2017-05-08 9:07 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-05-24 8:27 ` [PATCH] " Mahesh Kumar
2017-05-24 11:38 ` Ander Conselvan De Oliveira
2017-05-25 7:59 ` Mahesh Kumar
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