All of lore.kernel.org
 help / color / mirror / Atom feed
From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 4/6] drivers: Enable FPGA driver build on SPL
Date: Mon, 5 Jun 2017 04:26:33 +0000	[thread overview]
Message-ID: <1496636789.2428.18.camel@intel.com> (raw)
In-Reply-To: <9d03d7b7-a899-f270-5113-da66fcd6b8ad@denx.de>

On Sab, 2017-06-03 at 13:29 +0200, Marek Vasut wrote:
> On 05/29/2017 06:00 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Enable FPGA driver build for SPL because FPGA driver is needed for
> > SPL
> > to configure and getting DDR up before loading U-boot into DDR and
> > booting from there.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> The thing I fail to understand is why you're sending the patches in
> seemingly random order. You add/change piece of code, then enable
> something and then add the relevant code you're enabling. I really do
> not understand that.
> 
> The patches should have some logical order -- change existing code,
> add
> new code, enable stuff.
> 
> Anyway, please collect the Acks, fix the nit and resubmit.
> 
Sorry for confusing, i enabled the stuff just to detect any break and
bugs as early as possible. I will follow the logical order next time :)
.
> > 
> > ---
> >  drivers/Makefile | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index 64c39d3..4478212 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> >  obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> >  obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> >  obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> > +obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
> >  endif
> >  
> >  ifdef CONFIG_TPL_BUILD
> > 
> 

  reply	other threads:[~2017-06-05  4:26 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-29  4:00 [U-Boot] [PATCH v7 0/6] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-05-29  4:00 ` [U-Boot] [PATCH v7 1/6] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-05-29  4:00 ` [U-Boot] [PATCH v7 2/6] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-05-29  4:00 ` [U-Boot] [PATCH v7 3/6] arm: socfpga: Enable FPGA driver on SPL tien.fong.chee at intel.com
2017-06-03 11:27   ` Marek Vasut
2017-06-05  3:32     ` Chee, Tien Fong
2017-06-05  4:02       ` Chee, Tien Fong
2017-06-05 11:24         ` Marek Vasut
2017-06-05 12:06           ` Chee, Tien Fong
2017-06-05 12:08             ` Marek Vasut
2017-06-05 12:11               ` Chee, Tien Fong
2017-06-05 12:15                 ` Marek Vasut
2017-06-05 12:23                   ` Chee, Tien Fong
2017-06-05 12:25                     ` Marek Vasut
2017-06-05 12:57                       ` Chee, Tien Fong
2017-06-05 13:00                         ` Marek Vasut
2017-06-06  3:46                           ` Chee, Tien Fong
2017-06-06  7:56                             ` Marek Vasut
2017-05-29  4:00 ` [U-Boot] [PATCH v7 4/6] drivers: Enable FPGA driver build " tien.fong.chee at intel.com
2017-06-03 11:29   ` Marek Vasut
2017-06-05  4:26     ` Chee, Tien Fong [this message]
2017-05-29  4:00 ` [U-Boot] [PATCH v7 5/6] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
2017-05-29  4:00 ` [U-Boot] [PATCH v7 6/6] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
2017-05-30 13:48 ` [U-Boot] [PATCH v7 0/6] Add Intel Arria 10 SoC FPGA driver Dinh Nguyen
2017-06-01  3:23   ` Ley Foon Tan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1496636789.2428.18.camel@intel.com \
    --to=tien.fong.chee@intel.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.