All of lore.kernel.org
 help / color / mirror / Atom feed
From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v3 0/6] irqchip: meson: add support for the gpio interrupt controller
Date: Fri, 16 Jun 2017 12:23:07 +0200	[thread overview]
Message-ID: <1497608587.3086.42.camel@baylibre.com> (raw)
In-Reply-To: <8742df56-42ef-bf70-0ec1-9e8418ec0063@arm.com>

On Fri, 2017-06-16 at 09:46 +0100, Marc Zyngier wrote:
> On 15/06/17 17:17, Jerome Brunet wrote:
> > This patch series adds support for the GPIO interrupt controller found on
> > Amlogic's meson SoC families.
> > 
> > Unlike what the name suggests, this controller is not part of the SoC
> > GPIO subsystem. It is a separate controller from which can watch almost
> > all pads of the SoC and generate and interrupt from it. Some pins, which
> > are not part of the public datasheet, don't seem to have this capability
> > though.
> > 
> > Hardware wise, the controller is a 256 to 8 router with filtering block
> > to select edge or level input and the polarity of the signal.??As there
> > we can't setup the filtring to generate a signal on both the high and low
> > polarity, there is no easy way to support IRQ_TYPE_EDGE_BOTH at the
> > moment
> > 
> > The number of interrupt line routed to the controller depends on the SoC,
> > and essentially the number of GPIO available on the SoC.
> > 
> > This series has been tested on Amlogic S905-P200 board with the front
> > panel power button.
> > 
> > This work is derived from the previous work of Carlo Caione [1].
> 
> [...]
> 
> So we have two competing series, all based on the same stuff. I must say
> this is rather disappointing that people can't manage to collaborate and
> work towards a common goal.
> 
> I'm going to review the irqchip part, because I've done that on Heiner's
> series as well, but that's where I'm going to stop.
> 
> Heiner, Jerome: please sort this out between yourselves *BEFORE* sending
> any other patch series. This is wasting everybody's time, both yours and
> mine (and frankly, this a rather rare commodity these days).

I really don't enjoy doing things that way, and I understand the feeling.

I also spent a lot of time reviewing Heiner's patches, only to see comments
repeatedly ignored. You know well how time consuming those reviews are. 

After 7 versions, some comments have been taken into account, some are still
completely ignored, even with Kevin and Neil's warnings. I wouldn't have posted
a competing if things were not stuck.

Like you, I have things far more interesting to do than duplicating efforts, and
I sincerely hope better collaboration can be achieved.

Anyway, thanks for your time and sorry for the mess. 

Cheers
Jerome

> 
> Thanks,
> 
> 	M.

WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 0/6] irqchip: meson: add support for the gpio interrupt controller
Date: Fri, 16 Jun 2017 12:23:07 +0200	[thread overview]
Message-ID: <1497608587.3086.42.camel@baylibre.com> (raw)
In-Reply-To: <8742df56-42ef-bf70-0ec1-9e8418ec0063@arm.com>

On Fri, 2017-06-16 at 09:46 +0100, Marc Zyngier wrote:
> On 15/06/17 17:17, Jerome Brunet wrote:
> > This patch series adds support for the GPIO interrupt controller found on
> > Amlogic's meson SoC families.
> > 
> > Unlike what the name suggests, this controller is not part of the SoC
> > GPIO subsystem. It is a separate controller from which can watch almost
> > all pads of the SoC and generate and interrupt from it. Some pins, which
> > are not part of the public datasheet, don't seem to have this capability
> > though.
> > 
> > Hardware wise, the controller is a 256 to 8 router with filtering block
> > to select edge or level input and the polarity of the signal.??As there
> > we can't setup the filtring to generate a signal on both the high and low
> > polarity, there is no easy way to support IRQ_TYPE_EDGE_BOTH at the
> > moment
> > 
> > The number of interrupt line routed to the controller depends on the SoC,
> > and essentially the number of GPIO available on the SoC.
> > 
> > This series has been tested on Amlogic S905-P200 board with the front
> > panel power button.
> > 
> > This work is derived from the previous work of Carlo Caione [1].
> 
> [...]
> 
> So we have two competing series, all based on the same stuff. I must say
> this is rather disappointing that people can't manage to collaborate and
> work towards a common goal.
> 
> I'm going to review the irqchip part, because I've done that on Heiner's
> series as well, but that's where I'm going to stop.
> 
> Heiner, Jerome: please sort this out between yourselves *BEFORE* sending
> any other patch series. This is wasting everybody's time, both yours and
> mine (and frankly, this a rather rare commodity these days).

I really don't enjoy doing things that way, and I understand the feeling.

I also spent a lot of time reviewing Heiner's patches, only to see comments
repeatedly ignored. You know well how time consuming those reviews are. 

After 7 versions, some comments have been taken into account, some are still
completely ignored, even with Kevin and Neil's warnings. I wouldn't have posted
a competing if things were not stuck.

Like you, I have things far more interesting to do than duplicating efforts, and
I sincerely hope better collaboration can be achieved.

Anyway, thanks for your time and sorry for the mess. 

Cheers
Jerome

> 
> Thanks,
> 
> 	M.

WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
To: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
	Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
	Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
	Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Cc: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>,
	linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Heiner Kallweit
	<hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v3 0/6] irqchip: meson: add support for the gpio interrupt controller
Date: Fri, 16 Jun 2017 12:23:07 +0200	[thread overview]
Message-ID: <1497608587.3086.42.camel@baylibre.com> (raw)
In-Reply-To: <8742df56-42ef-bf70-0ec1-9e8418ec0063-5wv7dgnIgG8@public.gmane.org>

On Fri, 2017-06-16 at 09:46 +0100, Marc Zyngier wrote:
> On 15/06/17 17:17, Jerome Brunet wrote:
> > This patch series adds support for the GPIO interrupt controller found on
> > Amlogic's meson SoC families.
> > 
> > Unlike what the name suggests, this controller is not part of the SoC
> > GPIO subsystem. It is a separate controller from which can watch almost
> > all pads of the SoC and generate and interrupt from it. Some pins, which
> > are not part of the public datasheet, don't seem to have this capability
> > though.
> > 
> > Hardware wise, the controller is a 256 to 8 router with filtering block
> > to select edge or level input and the polarity of the signal.  As there
> > we can't setup the filtring to generate a signal on both the high and low
> > polarity, there is no easy way to support IRQ_TYPE_EDGE_BOTH at the
> > moment
> > 
> > The number of interrupt line routed to the controller depends on the SoC,
> > and essentially the number of GPIO available on the SoC.
> > 
> > This series has been tested on Amlogic S905-P200 board with the front
> > panel power button.
> > 
> > This work is derived from the previous work of Carlo Caione [1].
> 
> [...]
> 
> So we have two competing series, all based on the same stuff. I must say
> this is rather disappointing that people can't manage to collaborate and
> work towards a common goal.
> 
> I'm going to review the irqchip part, because I've done that on Heiner's
> series as well, but that's where I'm going to stop.
> 
> Heiner, Jerome: please sort this out between yourselves *BEFORE* sending
> any other patch series. This is wasting everybody's time, both yours and
> mine (and frankly, this a rather rare commodity these days).

I really don't enjoy doing things that way, and I understand the feeling.

I also spent a lot of time reviewing Heiner's patches, only to see comments
repeatedly ignored. You know well how time consuming those reviews are. 

After 7 versions, some comments have been taken into account, some are still
completely ignored, even with Kevin and Neil's warnings. I wouldn't have posted
a competing if things were not stuck.

Like you, I have things far more interesting to do than duplicating efforts, and
I sincerely hope better collaboration can be achieved.

Anyway, thanks for your time and sorry for the mess. 

Cheers
Jerome

> 
> Thanks,
> 
> 	M.

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	Kevin Hilman <khilman@baylibre.com>
Cc: Carlo Caione <carlo@caione.org>,
	linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Heiner Kallweit <hkallweit1@gmail.com>
Subject: Re: [PATCH v3 0/6] irqchip: meson: add support for the gpio interrupt controller
Date: Fri, 16 Jun 2017 12:23:07 +0200	[thread overview]
Message-ID: <1497608587.3086.42.camel@baylibre.com> (raw)
In-Reply-To: <8742df56-42ef-bf70-0ec1-9e8418ec0063@arm.com>

On Fri, 2017-06-16 at 09:46 +0100, Marc Zyngier wrote:
> On 15/06/17 17:17, Jerome Brunet wrote:
> > This patch series adds support for the GPIO interrupt controller found on
> > Amlogic's meson SoC families.
> > 
> > Unlike what the name suggests, this controller is not part of the SoC
> > GPIO subsystem. It is a separate controller from which can watch almost
> > all pads of the SoC and generate and interrupt from it. Some pins, which
> > are not part of the public datasheet, don't seem to have this capability
> > though.
> > 
> > Hardware wise, the controller is a 256 to 8 router with filtering block
> > to select edge or level input and the polarity of the signal.  As there
> > we can't setup the filtring to generate a signal on both the high and low
> > polarity, there is no easy way to support IRQ_TYPE_EDGE_BOTH at the
> > moment
> > 
> > The number of interrupt line routed to the controller depends on the SoC,
> > and essentially the number of GPIO available on the SoC.
> > 
> > This series has been tested on Amlogic S905-P200 board with the front
> > panel power button.
> > 
> > This work is derived from the previous work of Carlo Caione [1].
> 
> [...]
> 
> So we have two competing series, all based on the same stuff. I must say
> this is rather disappointing that people can't manage to collaborate and
> work towards a common goal.
> 
> I'm going to review the irqchip part, because I've done that on Heiner's
> series as well, but that's where I'm going to stop.
> 
> Heiner, Jerome: please sort this out between yourselves *BEFORE* sending
> any other patch series. This is wasting everybody's time, both yours and
> mine (and frankly, this a rather rare commodity these days).

I really don't enjoy doing things that way, and I understand the feeling.

I also spent a lot of time reviewing Heiner's patches, only to see comments
repeatedly ignored. You know well how time consuming those reviews are. 

After 7 versions, some comments have been taken into account, some are still
completely ignored, even with Kevin and Neil's warnings. I wouldn't have posted
a competing if things were not stuck.

Like you, I have things far more interesting to do than duplicating efforts, and
I sincerely hope better collaboration can be achieved.

Anyway, thanks for your time and sorry for the mess. 

Cheers
Jerome

> 
> Thanks,
> 
> 	M.

  reply	other threads:[~2017-06-16 10:23 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-15 16:17 [PATCH v3 0/6] irqchip: meson: add support for the gpio interrupt controller Jerome Brunet
2017-06-15 16:17 ` Jerome Brunet
2017-06-15 16:17 ` Jerome Brunet
2017-06-15 16:17 ` Jerome Brunet
2017-06-15 16:17 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: add DT binding for meson GPIO " Jerome Brunet
2017-06-15 16:17   ` Jerome Brunet
2017-06-15 16:17   ` Jerome Brunet
2017-06-15 16:17   ` Jerome Brunet
2017-06-15 16:18 ` [PATCH v3 2/6] irqchip: meson: add support for gpio " Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-16  9:35   ` Marc Zyngier
2017-06-16  9:35     ` Marc Zyngier
2017-06-16  9:35     ` Marc Zyngier
2017-06-16  9:35     ` Marc Zyngier
2017-06-16 10:02     ` Jerome Brunet
2017-06-16 10:02       ` Jerome Brunet
2017-06-16 10:02       ` Jerome Brunet
2017-06-16 10:02       ` Jerome Brunet
2017-06-16 10:28       ` Marc Zyngier
2017-06-16 10:28         ` Marc Zyngier
2017-06-16 10:28         ` Marc Zyngier
2017-06-16 10:28         ` Marc Zyngier
2017-06-15 16:18 ` [PATCH v3 3/6] ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18 ` [PATCH v3 4/6] ARM64: meson: enable MESON_IRQ_GPIO in Kconfig Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18 ` [PATCH v3 5/6] ARM: dts: meson8b: enable gpio interrupt controller Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18 ` [PATCH v3 6/6] ARM64: dts: meson-gx: add " Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-15 16:18   ` Jerome Brunet
2017-06-16  8:46 ` [PATCH v3 0/6] irqchip: meson: add support for the " Marc Zyngier
2017-06-16  8:46   ` Marc Zyngier
2017-06-16  8:46   ` Marc Zyngier
2017-06-16  8:46   ` Marc Zyngier
2017-06-16 10:23   ` Jerome Brunet [this message]
2017-06-16 10:23     ` Jerome Brunet
2017-06-16 10:23     ` Jerome Brunet
2017-06-16 10:23     ` Jerome Brunet

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1497608587.3086.42.camel@baylibre.com \
    --to=jbrunet@baylibre.com \
    --cc=linus-amlogic@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.