* [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
@ 2017-06-16 20:15 Rodrigo Vivi
2017-06-16 21:18 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-16 23:55 ` [PATCH] " Paulo Zanoni
0 siblings, 2 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-06-16 20:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Paulo noticed that we were missing few bits clear
before writing values back to the register on
these RMW MMIO operations.
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd535f1..d4edc79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
#define CURSOR_COEFF(x) ((x) << 0)
+#define POST_CURSOR_COEFF_MASK (0x3F << 6)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
#define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db80938..e66947a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~(SCALING_MODE_SEL_MASK);
val |= SCALING_MODE_SEL(2);
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+ val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+ RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Rcomp scalar is fixed as 0x98 for every table entry */
@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* We cannot write to GRP. It would overrite individual loadgen */
for (ln = 0; ln < 4; ln++) {
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+ val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+ POST_CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Program PORT_TX_DW5 */
/* All DW5 values are fixed for every table entry */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~(RTERM_SELECT_MASK);
val |= RTERM_SELECT(6);
val |= TAP3_DISABLE;
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW7 */
val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix RMW on ddi vswing sequence.
2017-06-16 20:15 [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence Rodrigo Vivi
@ 2017-06-16 21:18 ` Patchwork
2017-06-16 23:55 ` [PATCH] " Paulo Zanoni
1 sibling, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-06-16 21:18 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix RMW on ddi vswing sequence.
URL : https://patchwork.freedesktop.org/series/25935/
State : success
== Summary ==
Series 25935v1 drm/i915/cnl: Fix RMW on ddi vswing sequence.
https://patchwork.freedesktop.org/api/1.0/series/25935/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass -> SKIP (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
dmesg-warn -> PASS (fi-skl-6700hq) fdo#101154 +19
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101154 https://bugs.freedesktop.org/show_bug.cgi?id=101154
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:460s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:480s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:571s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:555s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:492s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:499s
fi-glk-2a total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:587s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:433s
fi-hsw-4770r total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:16 time:422s
fi-ilk-650 total:278 pass:227 dwarn:0 dfail:0 fail:0 skip:50 time:466s
fi-ivb-3520m total:278 pass:255 dwarn:0 dfail:0 fail:0 skip:22 time:492s
fi-ivb-3770 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:18 time:513s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:470s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time:566s
fi-kbl-r total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time:580s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:478s
fi-skl-6700hq total:278 pass:228 dwarn:1 dfail:0 fail:27 skip:22 time:436s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:514s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:501s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:509s
fi-snb-2520m total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:28 time:662s
fi-snb-2600 total:278 pass:247 dwarn:0 dfail:0 fail:1 skip:29 time:403s
473e5a3f4cc108756ffeeb6f4ccf9337e9050648 drm-tip: 2017y-06m-16d-20h-10m-15s UTC integration manifest
c1f8826 drm/i915/cnl: Fix RMW on ddi vswing sequence.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4975/
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
2017-06-16 20:15 [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence Rodrigo Vivi
2017-06-16 21:18 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-06-16 23:55 ` Paulo Zanoni
1 sibling, 0 replies; 8+ messages in thread
From: Paulo Zanoni @ 2017-06-16 23:55 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Em Sex, 2017-06-16 às 13:15 -0700, Rodrigo Vivi escreveu:
> Paulo noticed that we were missing few bits clear
> before writing values back to the register on
> these RMW MMIO operations.
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index bd535f1..d4edc79 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW2
> _LN0_AE, \
> _CNL_PORT_TX_DW2
> _LN0_F)
> #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
> +#define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
> +#define SWING_SEL_LOWER_MASK (0x7 << 11)
> #define RCOMP_SCALAR(x) ((x) << 0)
> +#define RCOMP_SCALAR_MASK (0xFF << 0)
>
> #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
> #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
> @@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW4
> _LN0_F)
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> +#define POST_CURSOR_1_MASK (0x3F << 12)
> #define POST_CURSOR_2(x) ((x) << 6)
> +#define POST_CURSOR_2_MASK (0x3F << 6)
> #define CURSOR_COEFF(x) ((x) << 0)
> +#define POST_CURSOR_COEFF_MASK (0x3F << 6)
s/POST_CURSOR_COEFF_MASK/CURSOR_COEFF_MASK/, there's no "post" in the
name of this field.
With that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
As a side note, I really think all these CNL definitions lack the name
of the registers as prefix. I worry about future namespace collision.
But that's a discussion for another patch.
>
> #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
> #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
> @@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
> #define TX_TRAINING_EN (1 << 31)
> #define TAP3_DISABLE (1 << 29)
> #define SCALING_MODE_SEL(x) ((x) << 18)
> +#define SCALING_MODE_SEL_MASK (0x7 << 18)
> #define RTERM_SELECT(x) ((x) << 3)
> +#define RTERM_SELECT_MASK (0x7 << 3)
>
> #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
> #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
> @@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW7
> _LN0_AE, \
> _CNL_PORT_TX_DW7
> _LN0_F)
> #define N_SCALAR(x) ((x) << 24)
> +#define N_SCALAR_MASK (0x7F << 24)
>
> /* The spec defines this only for BXT PHY0, but lets assume that
> this
> * would exist for PHY1 too if it had a second channel.
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index db80938..e66947a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct
> drm_i915_private *dev_priv,
>
> /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~(SCALING_MODE_SEL_MASK);
> val |= SCALING_MODE_SEL(2);
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> + val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> + RCOMP_SCALAR_MASK);
> val |=
> SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> val |=
> SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Rcomp scalar is fixed as 0x98 for every table entry */
> @@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct
> drm_i915_private *dev_priv,
> /* We cannot write to GRP. It would overrite individual
> loadgen */
> for (ln = 0; ln < 4; ln++) {
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> + val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> + POST_CURSOR_COEFF_MASK);
> val |=
> POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> val |=
> POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> val |=
> CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> @@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct
> drm_i915_private *dev_priv,
> /* Program PORT_TX_DW5 */
> /* All DW5 values are fixed for every table entry */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~(RTERM_SELECT_MASK);
> val |= RTERM_SELECT(6);
> val |= TAP3_DISABLE;
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW7 */
> val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> }
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
@ 2017-06-17 0:26 Rodrigo Vivi
2017-06-19 9:31 ` Jani Nikula
0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2017-06-17 0:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Paulo noticed that we were missing few bits clear
before writing values back to the register on
these RMW MMIO operations.
v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd535f1..c8647cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
#define CURSOR_COEFF(x) ((x) << 0)
+#define CURSOR_COEFF_MASK (0x3F << 6)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
#define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db80938..b4371e6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~(SCALING_MODE_SEL_MASK);
val |= SCALING_MODE_SEL(2);
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+ val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+ RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Rcomp scalar is fixed as 0x98 for every table entry */
@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* We cannot write to GRP. It would overrite individual loadgen */
for (ln = 0; ln < 4; ln++) {
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+ val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+ CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Program PORT_TX_DW5 */
/* All DW5 values are fixed for every table entry */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~(RTERM_SELECT_MASK);
val |= RTERM_SELECT(6);
val |= TAP3_DISABLE;
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW7 */
val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
2017-06-17 0:26 Rodrigo Vivi
@ 2017-06-19 9:31 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2017-06-19 9:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
On Fri, 16 Jun 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Paulo noticed that we were missing few bits clear
> before writing values back to the register on
> these RMW MMIO operations.
>
> v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bd535f1..c8647cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW2_LN0_AE, \
> _CNL_PORT_TX_DW2_LN0_F)
> #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
> +#define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
> +#define SWING_SEL_LOWER_MASK (0x7 << 11)
> #define RCOMP_SCALAR(x) ((x) << 0)
> +#define RCOMP_SCALAR_MASK (0xFF << 0)
>
> #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
> #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
> @@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW4_LN0_F)
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> +#define POST_CURSOR_1_MASK (0x3F << 12)
> #define POST_CURSOR_2(x) ((x) << 6)
> +#define POST_CURSOR_2_MASK (0x3F << 6)
> #define CURSOR_COEFF(x) ((x) << 0)
> +#define CURSOR_COEFF_MASK (0x3F << 6)
>
> #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
> #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
> @@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
> #define TX_TRAINING_EN (1 << 31)
> #define TAP3_DISABLE (1 << 29)
> #define SCALING_MODE_SEL(x) ((x) << 18)
> +#define SCALING_MODE_SEL_MASK (0x7 << 18)
> #define RTERM_SELECT(x) ((x) << 3)
> +#define RTERM_SELECT_MASK (0x7 << 3)
>
> #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
> #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
> @@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW7_LN0_AE, \
> _CNL_PORT_TX_DW7_LN0_F)
> #define N_SCALAR(x) ((x) << 24)
> +#define N_SCALAR_MASK (0x7F << 24)
>
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index db80938..b4371e6 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
>
> /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~(SCALING_MODE_SEL_MASK);
Unnecessary braces.
> val |= SCALING_MODE_SEL(2);
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> + val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> + RCOMP_SCALAR_MASK);
> val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Rcomp scalar is fixed as 0x98 for every table entry */
> @@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> /* We cannot write to GRP. It would overrite individual loadgen */
> for (ln = 0; ln < 4; ln++) {
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> + val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> + CURSOR_COEFF_MASK);
> val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> @@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> /* Program PORT_TX_DW5 */
> /* All DW5 values are fixed for every table entry */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~(RTERM_SELECT_MASK);
Unnecessary braces.
> val |= RTERM_SELECT(6);
> val |= TAP3_DISABLE;
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW7 */
> val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> }
--
Jani Nikula, Intel Open Source Technology Center
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* [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
@ 2017-06-19 17:08 Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-06-19 17:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni, Rodrigo Vivi
Paulo noticed that we were missing few bits clear
before writing values back to the register on
these RMW MMIO operations.
v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
v3: Remove unnecessary braces. (Jani).
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd535f1..c8647cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
#define CURSOR_COEFF(x) ((x) << 0)
+#define CURSOR_COEFF_MASK (0x3F << 6)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
#define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db80938..80e96f1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~SCALING_MODE_SEL_MASK;
val |= SCALING_MODE_SEL(2);
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+ val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+ RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Rcomp scalar is fixed as 0x98 for every table entry */
@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* We cannot write to GRP. It would overrite individual loadgen */
for (ln = 0; ln < 4; ln++) {
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+ val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+ CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Program PORT_TX_DW5 */
/* All DW5 values are fixed for every table entry */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~RTERM_SELECT_MASK;
val |= RTERM_SELECT(6);
val |= TAP3_DISABLE;
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW7 */
val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
@ 2017-06-19 18:39 Rodrigo Vivi
2017-06-19 21:09 ` Rodrigo Vivi
0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2017-06-19 18:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni, Rodrigo Vivi
Paulo noticed that we were missing few bits clear
before writing values back to the register on
these RMW MMIO operations.
v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
v3: Remove unnecessary braces. (Jani).
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd535f1..c8647cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
#define CURSOR_COEFF(x) ((x) << 0)
+#define CURSOR_COEFF_MASK (0x3F << 6)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
#define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db80938..80e96f1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~SCALING_MODE_SEL_MASK;
val |= SCALING_MODE_SEL(2);
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+ val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+ RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Rcomp scalar is fixed as 0x98 for every table entry */
@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* We cannot write to GRP. It would overrite individual loadgen */
for (ln = 0; ln < 4; ln++) {
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+ val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+ CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Program PORT_TX_DW5 */
/* All DW5 values are fixed for every table entry */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+ val &= ~RTERM_SELECT_MASK;
val |= RTERM_SELECT(6);
val |= TAP3_DISABLE;
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW7 */
val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence.
2017-06-19 18:39 Rodrigo Vivi
@ 2017-06-19 21:09 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-06-19 21:09 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx, Paulo Zanoni
Patch merged to dinq, thanks for spotting this and also for reviews
and comments.
On Mon, Jun 19, 2017 at 11:39 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Paulo noticed that we were missing few bits clear
> before writing values back to the register on
> these RMW MMIO operations.
>
> v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
> v3: Remove unnecessary braces. (Jani).
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bd535f1..c8647cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW2_LN0_AE, \
> _CNL_PORT_TX_DW2_LN0_F)
> #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
> +#define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
> +#define SWING_SEL_LOWER_MASK (0x7 << 11)
> #define RCOMP_SCALAR(x) ((x) << 0)
> +#define RCOMP_SCALAR_MASK (0xFF << 0)
>
> #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
> #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
> @@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW4_LN0_F)
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> +#define POST_CURSOR_1_MASK (0x3F << 12)
> #define POST_CURSOR_2(x) ((x) << 6)
> +#define POST_CURSOR_2_MASK (0x3F << 6)
> #define CURSOR_COEFF(x) ((x) << 0)
> +#define CURSOR_COEFF_MASK (0x3F << 6)
>
> #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
> #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
> @@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
> #define TX_TRAINING_EN (1 << 31)
> #define TAP3_DISABLE (1 << 29)
> #define SCALING_MODE_SEL(x) ((x) << 18)
> +#define SCALING_MODE_SEL_MASK (0x7 << 18)
> #define RTERM_SELECT(x) ((x) << 3)
> +#define RTERM_SELECT_MASK (0x7 << 3)
>
> #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
> #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
> @@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
> _CNL_PORT_TX_DW7_LN0_AE, \
> _CNL_PORT_TX_DW7_LN0_F)
> #define N_SCALAR(x) ((x) << 24)
> +#define N_SCALAR_MASK (0x7F << 24)
>
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index db80938..80e96f1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
>
> /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~SCALING_MODE_SEL_MASK;
> val |= SCALING_MODE_SEL(2);
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> + val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> + RCOMP_SCALAR_MASK);
> val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Rcomp scalar is fixed as 0x98 for every table entry */
> @@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> /* We cannot write to GRP. It would overrite individual loadgen */
> for (ln = 0; ln < 4; ln++) {
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> + val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> + CURSOR_COEFF_MASK);
> val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> @@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> /* Program PORT_TX_DW5 */
> /* All DW5 values are fixed for every table entry */
> val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> + val &= ~RTERM_SELECT_MASK;
> val |= RTERM_SELECT(6);
> val |= TAP3_DISABLE;
> I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW7 */
> val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> }
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-06-19 21:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-06-16 20:15 [PATCH] drm/i915/cnl: Fix RMW on ddi vswing sequence Rodrigo Vivi
2017-06-16 21:18 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-16 23:55 ` [PATCH] " Paulo Zanoni
-- strict thread matches above, loose matches on Subject: below --
2017-06-17 0:26 Rodrigo Vivi
2017-06-19 9:31 ` Jani Nikula
2017-06-19 17:08 Rodrigo Vivi
2017-06-19 18:39 Rodrigo Vivi
2017-06-19 21:09 ` Rodrigo Vivi
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