From: Dinh Nguyen <dinguyen@kernel.org>
To: robh+dt@kernel.org
Cc: dinguyen@kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, sboyd@codeaurora.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCHv1 2/4] ARM: dts: socfpga: add a bypass-reg binding for Stratix10
Date: Fri, 7 Jul 2017 14:03:17 -0500 [thread overview]
Message-ID: <1499454199-31901-2-git-send-email-dinguyen@kernel.org> (raw)
In-Reply-To: <1499454199-31901-1-git-send-email-dinguyen@kernel.org>
Add a 'bypass-reg' binding property for the Stratix10 clock. There are quite a
few clocks on the Stratix10 platform that have a separate bypass setting from
the clock's original parent.
The 'bypass-reg' binding contains the bypass register offset from the clock
manager's base address and a bit index.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
Documentation/devicetree/bindings/clock/altr_socfpga.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 1c32658..9e2754a 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -42,3 +42,6 @@ Optional properties:
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.
+- bypass-reg : There are a few clocks on the Stratix10 platform that can be
+ bypassed from their original parents to a separate clock. This binding
+ property contains the bypass register and the bit index.
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: dinguyen@kernel.org (Dinh Nguyen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv1 2/4] ARM: dts: socfpga: add a bypass-reg binding for Stratix10
Date: Fri, 7 Jul 2017 14:03:17 -0500 [thread overview]
Message-ID: <1499454199-31901-2-git-send-email-dinguyen@kernel.org> (raw)
In-Reply-To: <1499454199-31901-1-git-send-email-dinguyen@kernel.org>
Add a 'bypass-reg' binding property for the Stratix10 clock. There are quite a
few clocks on the Stratix10 platform that have a separate bypass setting from
the clock's original parent.
The 'bypass-reg' binding contains the bypass register offset from the clock
manager's base address and a bit index.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
Documentation/devicetree/bindings/clock/altr_socfpga.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 1c32658..9e2754a 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -42,3 +42,6 @@ Optional properties:
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.
+- bypass-reg : There are a few clocks on the Stratix10 platform that can be
+ bypassed from their original parents to a separate clock. This binding
+ property contains the bypass register and the bit index.
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [PATCHv1 2/4] ARM: dts: socfpga: add a bypass-reg binding for Stratix10
Date: Fri, 7 Jul 2017 14:03:17 -0500 [thread overview]
Message-ID: <1499454199-31901-2-git-send-email-dinguyen@kernel.org> (raw)
In-Reply-To: <1499454199-31901-1-git-send-email-dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Add a 'bypass-reg' binding property for the Stratix10 clock. There are quite a
few clocks on the Stratix10 platform that have a separate bypass setting from
the clock's original parent.
The 'bypass-reg' binding contains the bypass register offset from the clock
manager's base address and a bit index.
Signed-off-by: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/clock/altr_socfpga.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 1c32658..9e2754a 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -42,3 +42,6 @@ Optional properties:
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.
+- bypass-reg : There are a few clocks on the Stratix10 platform that can be
+ bypassed from their original parents to a separate clock. This binding
+ property contains the bypass register and the bit index.
--
2.7.4
--
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next prev parent reply other threads:[~2017-07-07 19:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-07 19:03 [PATCHv1 1/4] ARM: dts: socfpga: update documentation for clock bindings Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen [this message]
2017-07-07 19:03 ` [PATCHv1 2/4] ARM: dts: socfpga: add a bypass-reg binding for Stratix10 Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen
2017-07-07 19:03 ` [PATCHv1 3/4] arm64: dts: add complete clock tree for SoCFPGA Stratix10 Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen
2017-07-07 19:03 ` [PATCHv1 4/4] clk: socfpga: Add a clock driver for the SoCFPGA Stratix10 platform Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen
2017-07-07 19:03 ` Dinh Nguyen
2017-07-10 15:51 ` [PATCHv1 1/4] ARM: dts: socfpga: update documentation for clock bindings Rob Herring
2017-07-10 15:51 ` Rob Herring
2017-07-21 20:38 ` Stephen Boyd
2017-07-21 20:38 ` Stephen Boyd
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