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These PLL has +> > same +> > dividers and corresponding control registers mapped to different +> > addresses. +> > So we add one common driver for such PLLs. +> > +> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and +> > ODIV. Output clock value is managed using these dividers. +> > +> > We add pre-defined tables with supported rate values and +> > appropriate +> > configurations of IDIV, FBDIV and ODIV for each value. +> > +> > As of today we add support for PLLs that generate clock for the +> > following devices: +> > ?* ARC core on AXC CPU tiles. +> > ?* ARC PGU on ARC SDP Mainboard. +> > and more to come later. +> > +> > By this patch we add support for two plls (arc core pll and pgu +> > pll), +> > so we had to use two different init types: CLK_OF_DECLARE for arc +> > core pll and +> > regular probing for pgu pll. +> > +> > Acked-by: Rob Herring <robh at kernel.org> +> > Acked-by: Jose Abreu <joabreu at synopsys.com> +> > +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com> +> > Signed-off-by: Jose Abreu <joabreu at synopsys.com> +> +> Sorry this missed the cutoff for new code for v4.13. Should be in +> clk-next next week though. +> +> > +} +> > + +> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct +> > clk_hw *hw) +> > +{ +> > + return container_of(hw, struct axs10x_pll_clk, hw); +> > +} +> > + +> > +static inline u32 axs10x_div_get_value(u32 reg) +> > +{ +> > + if (PLL_REG_GET_BYPASS(reg)) +> > + return 1; +> > + +> > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg); +> > +} +> > + +> > +static inline u32 axs10x_encode_div(unsigned int id, int upd) +> > +{ +> > + u32 div = 0; +> > + +> > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + +> > 1); +> > + PLL_REG_SET_HIGH(div, id >> 1); +> > + PLL_REG_SET_EDGE(div, id % 2); +> > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0); +> > + PLL_REG_SET_NOUPD(div, !upd); +> +> So sparse complains here about a "dubious !x & y". Perhaps this +> can be changed to +> +> PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0); +> +> That way sparse doesn't complain. I can make the change when +> applying if you agree. + +Sure, thanks a lot. + +-- +?Eugeniy Paltsev diff --git a/a/content_digest b/N1/content_digest index 74ac619..11ea578 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,59 +1,86 @@ "ref\020170621191626.32248-1-Eugeniy.Paltsev@synopsys.com\0" "ref\020170712052535.GY22780@codeaurora.org\0" - "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" - "Subject\0Re: [PATCH v4] clk: axs10x: introduce AXS10X pll driver\0" + "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" + "Subject\0[PATCH v4] clk: axs10x: introduce AXS10X pll driver\0" "Date\0Wed, 12 Jul 2017 08:01:43 +0000\0" - "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - Jose.Abreu@synopsys.com <Jose.Abreu@synopsys.com> - mturquette@baylibre.com <mturquette@baylibre.com> - Eugeniy.Paltsev@synopsys.com <Eugeniy.Paltsev@synopsys.com> - linux-clk@vger.kernel.org <linux-clk@vger.kernel.org> - " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE3LTA3LTExIGF0IDIyOjI1IC0wNzAwLCBTdGVwaGVuIEJveWQgd3JvdGU6DQo+\n" - "IE9uIDA2LzIxLCBFdWdlbml5IFBhbHRzZXYgd3JvdGU6DQo+ID4gQVhTMTBYIGJvYXJkcyBtYW5h\n" - "Z2VzIGl0J3MgY2xvY2tzIHVzaW5nIHZhcmlvdXMgUExMcy4gVGhlc2UgUExMIGhhcw0KPiA+IHNh\n" - "bWUNCj4gPiBkaXZpZGVycyBhbmQgY29ycmVzcG9uZGluZyBjb250cm9sIHJlZ2lzdGVycyBtYXBw\n" - "ZWQgdG8gZGlmZmVyZW50DQo+ID4gYWRkcmVzc2VzLg0KPiA+IFNvIHdlIGFkZCBvbmUgY29tbW9u\n" - "IGRyaXZlciBmb3Igc3VjaCBQTExzLg0KPiA+IA0KPiA+IEVhY2ggUExMIG9uIEFYUzEwWCBib2Fy\n" - "ZCBjb25zaXN0IG9mIHRocmVlIGRpdmlkZXJzOiBJRElWLCBGQkRJViBhbmQNCj4gPiBPRElWLiBP\n" - "dXRwdXQgY2xvY2sgdmFsdWUgaXMgbWFuYWdlZCB1c2luZyB0aGVzZSBkaXZpZGVycy4NCj4gPiAN\n" - "Cj4gPiBXZSBhZGQgcHJlLWRlZmluZWQgdGFibGVzIHdpdGggc3VwcG9ydGVkIHJhdGUgdmFsdWVz\n" - "IGFuZA0KPiA+IGFwcHJvcHJpYXRlDQo+ID4gY29uZmlndXJhdGlvbnMgb2YgSURJViwgRkJESVYg\n" - "YW5kIE9ESVYgZm9yIGVhY2ggdmFsdWUuDQo+ID4gDQo+ID4gQXMgb2YgdG9kYXkgd2UgYWRkIHN1\n" - "cHBvcnQgZm9yIFBMTHMgdGhhdCBnZW5lcmF0ZSBjbG9jayBmb3IgdGhlDQo+ID4gZm9sbG93aW5n\n" - "IGRldmljZXM6DQo+ID4gwqAqIEFSQyBjb3JlIG9uIEFYQyBDUFUgdGlsZXMuDQo+ID4gwqAqIEFS\n" - "QyBQR1Ugb24gQVJDIFNEUCBNYWluYm9hcmQuDQo+ID4gYW5kIG1vcmUgdG8gY29tZSBsYXRlci4N\n" - "Cj4gPiANCj4gPiBCeSB0aGlzIHBhdGNoIHdlIGFkZCBzdXBwb3J0IGZvciB0d28gcGxscyAoYXJj\n" - "IGNvcmUgcGxsIGFuZCBwZ3UNCj4gPiBwbGwpLA0KPiA+IHNvIHdlIGhhZCB0byB1c2UgdHdvIGRp\n" - "ZmZlcmVudCBpbml0IHR5cGVzOiBDTEtfT0ZfREVDTEFSRSBmb3IgYXJjDQo+ID4gY29yZSBwbGwg\n" - "YW5kDQo+ID4gcmVndWxhciBwcm9iaW5nIGZvciBwZ3UgcGxsLg0KPiA+IA0KPiA+IEFja2VkLWJ5\n" - "OiBSb2IgSGVycmluZyA8cm9iaEBrZXJuZWwub3JnPg0KPiA+IEFja2VkLWJ5OiBKb3NlIEFicmV1\n" - "IDxqb2FicmV1QHN5bm9wc3lzLmNvbT4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBFdWdlbml5\n" - "IFBhbHRzZXYgPEV1Z2VuaXkuUGFsdHNldkBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i\n" - "eTogVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i\n" - "eTogSm9zZSBBYnJldSA8am9hYnJldUBzeW5vcHN5cy5jb20+DQo+IA0KPiBTb3JyeSB0aGlzIG1p\n" - "c3NlZCB0aGUgY3V0b2ZmIGZvciBuZXcgY29kZSBmb3IgdjQuMTMuIFNob3VsZCBiZSBpbg0KPiBj\n" - "bGstbmV4dCBuZXh0IHdlZWsgdGhvdWdoLg0KPiANCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGlj\n" - "IGlubGluZSBzdHJ1Y3QgYXhzMTB4X3BsbF9jbGsgKnRvX2F4czEweF9wbGxfY2xrKHN0cnVjdA0K\n" - "PiA+IGNsa19odyAqaHcpDQo+ID4gK3sNCj4gPiArCXJldHVybiBjb250YWluZXJfb2YoaHcsIHN0\n" - "cnVjdCBheHMxMHhfcGxsX2NsaywgaHcpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5s\n" - "aW5lIHUzMiBheHMxMHhfZGl2X2dldF92YWx1ZSh1MzIgcmVnKQ0KPiA+ICt7DQo+ID4gKwlpZiAo\n" - "UExMX1JFR19HRVRfQllQQVNTKHJlZykpDQo+ID4gKwkJcmV0dXJuIDE7DQo+ID4gKw0KPiA+ICsJ\n" - "cmV0dXJuIFBMTF9SRUdfR0VUX0hJR0gocmVnKSArIFBMTF9SRUdfR0VUX0xPVyhyZWcpOw0KPiA+\n" - "ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5saW5lIHUzMiBheHMxMHhfZW5jb2RlX2Rpdih1bnNp\n" - "Z25lZCBpbnQgaWQsIGludCB1cGQpDQo+ID4gK3sNCj4gPiArCXUzMiBkaXYgPSAwOw0KPiA+ICsN\n" - "Cj4gPiArCVBMTF9SRUdfU0VUX0xPVyhkaXYsIChpZCAlIDIgPT0gMCkgPyBpZCA+PiAxIDogKGlk\n" - "ID4+IDEpICsNCj4gPiAxKTsNCj4gPiArCVBMTF9SRUdfU0VUX0hJR0goZGl2LCBpZCA+PiAxKTsN\n" - "Cj4gPiArCVBMTF9SRUdfU0VUX0VER0UoZGl2LCBpZCAlIDIpOw0KPiA+ICsJUExMX1JFR19TRVRf\n" - "QllQQVNTKGRpdiwgaWQgPT0gMSA/IDEgOiAwKTsNCj4gPiArCVBMTF9SRUdfU0VUX05PVVBEKGRp\n" - "diwgIXVwZCk7DQo+IA0KPiBTbyBzcGFyc2UgY29tcGxhaW5zIGhlcmUgYWJvdXQgYSAiZHViaW91\n" - "cyAheCAmIHkiLiBQZXJoYXBzIHRoaXMNCj4gY2FuIGJlIGNoYW5nZWQgdG8NCj4gDQo+IAlQTExf\n" - "UkVHX1NFVF9OT1VQRChkaXYsIHVwZCA9PSAwID8gMSA6IDApOw0KPiANCj4gVGhhdCB3YXkgc3Bh\n" - "cnNlIGRvZXNuJ3QgY29tcGxhaW4uIEkgY2FuIG1ha2UgdGhlIGNoYW5nZSB3aGVuDQo+IGFwcGx5\n" - "aW5nIGlmIHlvdSBhZ3JlZS4NCg0KU3VyZSwgdGhhbmtzIGEgbG90Lg0KDQotLSANCsKgRXVnZW5p\n" - eSBQYWx0c2V2 + "On Tue, 2017-07-11@22:25 -0700, Stephen Boyd wrote:\n" + "> On 06/21, Eugeniy Paltsev wrote:\n" + "> > AXS10X boards manages it's clocks using various PLLs. These PLL has\n" + "> > same\n" + "> > dividers and corresponding control registers mapped to different\n" + "> > addresses.\n" + "> > So we add one common driver for such PLLs.\n" + "> > \n" + "> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and\n" + "> > ODIV. Output clock value is managed using these dividers.\n" + "> > \n" + "> > We add pre-defined tables with supported rate values and\n" + "> > appropriate\n" + "> > configurations of IDIV, FBDIV and ODIV for each value.\n" + "> > \n" + "> > As of today we add support for PLLs that generate clock for the\n" + "> > following devices:\n" + "> > ?* ARC core on AXC CPU tiles.\n" + "> > ?* ARC PGU on ARC SDP Mainboard.\n" + "> > and more to come later.\n" + "> > \n" + "> > By this patch we add support for two plls (arc core pll and pgu\n" + "> > pll),\n" + "> > so we had to use two different init types: CLK_OF_DECLARE for arc\n" + "> > core pll and\n" + "> > regular probing for pgu pll.\n" + "> > \n" + "> > Acked-by: Rob Herring <robh at kernel.org>\n" + "> > Acked-by: Jose Abreu <joabreu at synopsys.com>\n" + "> > \n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com>\n" + "> > Signed-off-by: Jose Abreu <joabreu at synopsys.com>\n" + "> \n" + "> Sorry this missed the cutoff for new code for v4.13. Should be in\n" + "> clk-next next week though.\n" + "> \n" + "> > +}\n" + "> > +\n" + "> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct\n" + "> > clk_hw *hw)\n" + "> > +{\n" + "> > +\treturn container_of(hw, struct axs10x_pll_clk, hw);\n" + "> > +}\n" + "> > +\n" + "> > +static inline u32 axs10x_div_get_value(u32 reg)\n" + "> > +{\n" + "> > +\tif (PLL_REG_GET_BYPASS(reg))\n" + "> > +\t\treturn 1;\n" + "> > +\n" + "> > +\treturn PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);\n" + "> > +}\n" + "> > +\n" + "> > +static inline u32 axs10x_encode_div(unsigned int id, int upd)\n" + "> > +{\n" + "> > +\tu32 div = 0;\n" + "> > +\n" + "> > +\tPLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +\n" + "> > 1);\n" + "> > +\tPLL_REG_SET_HIGH(div, id >> 1);\n" + "> > +\tPLL_REG_SET_EDGE(div, id % 2);\n" + "> > +\tPLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);\n" + "> > +\tPLL_REG_SET_NOUPD(div, !upd);\n" + "> \n" + "> So sparse complains here about a \"dubious !x & y\". Perhaps this\n" + "> can be changed to\n" + "> \n" + "> \tPLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);\n" + "> \n" + "> That way sparse doesn't complain. I can make the change when\n" + "> applying if you agree.\n" + "\n" + "Sure, thanks a lot.\n" + "\n" + "-- \n" + ?Eugeniy Paltsev -970d7bfeb7c447778e8a5603f0809bc3536a50e704affca77ea3148ecd57b4ee +a7da8176494eea5b8c57543c497e9e4974556c21fc99933a8665206ddd0ecdb6
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These PLL has +> > same +> > dividers and corresponding control registers mapped to different +> > addresses. +> > So we add one common driver for such PLLs. +> > +> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and +> > ODIV. Output clock value is managed using these dividers. +> > +> > We add pre-defined tables with supported rate values and +> > appropriate +> > configurations of IDIV, FBDIV and ODIV for each value. +> > +> > As of today we add support for PLLs that generate clock for the +> > following devices: +> > * ARC core on AXC CPU tiles. +> > * ARC PGU on ARC SDP Mainboard. +> > and more to come later. +> > +> > By this patch we add support for two plls (arc core pll and pgu +> > pll), +> > so we had to use two different init types: CLK_OF_DECLARE for arc +> > core pll and +> > regular probing for pgu pll. +> > +> > Acked-by: Rob Herring <robh@kernel.org> +> > Acked-by: Jose Abreu <joabreu@synopsys.com> +> > +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> +> > Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> +> > Signed-off-by: Jose Abreu <joabreu@synopsys.com> +> +> Sorry this missed the cutoff for new code for v4.13. Should be in +> clk-next next week though. +> +> > +} +> > + +> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct +> > clk_hw *hw) +> > +{ +> > + return container_of(hw, struct axs10x_pll_clk, hw); +> > +} +> > + +> > +static inline u32 axs10x_div_get_value(u32 reg) +> > +{ +> > + if (PLL_REG_GET_BYPASS(reg)) +> > + return 1; +> > + +> > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg); +> > +} +> > + +> > +static inline u32 axs10x_encode_div(unsigned int id, int upd) +> > +{ +> > + u32 div = 0; +> > + +> > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + +> > 1); +> > + PLL_REG_SET_HIGH(div, id >> 1); +> > + PLL_REG_SET_EDGE(div, id % 2); +> > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0); +> > + PLL_REG_SET_NOUPD(div, !upd); +> +> So sparse complains here about a "dubious !x & y". Perhaps this +> can be changed to +> +> PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0); +> +> That way sparse doesn't complain. I can make the change when +> applying if you agree. + +Sure, thanks a lot. + +-- + Eugeniy Paltsev diff --git a/a/content_digest b/N2/content_digest index 74ac619..52df9e0 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -12,48 +12,81 @@ " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE3LTA3LTExIGF0IDIyOjI1IC0wNzAwLCBTdGVwaGVuIEJveWQgd3JvdGU6DQo+\n" - "IE9uIDA2LzIxLCBFdWdlbml5IFBhbHRzZXYgd3JvdGU6DQo+ID4gQVhTMTBYIGJvYXJkcyBtYW5h\n" - "Z2VzIGl0J3MgY2xvY2tzIHVzaW5nIHZhcmlvdXMgUExMcy4gVGhlc2UgUExMIGhhcw0KPiA+IHNh\n" - "bWUNCj4gPiBkaXZpZGVycyBhbmQgY29ycmVzcG9uZGluZyBjb250cm9sIHJlZ2lzdGVycyBtYXBw\n" - "ZWQgdG8gZGlmZmVyZW50DQo+ID4gYWRkcmVzc2VzLg0KPiA+IFNvIHdlIGFkZCBvbmUgY29tbW9u\n" - "IGRyaXZlciBmb3Igc3VjaCBQTExzLg0KPiA+IA0KPiA+IEVhY2ggUExMIG9uIEFYUzEwWCBib2Fy\n" - "ZCBjb25zaXN0IG9mIHRocmVlIGRpdmlkZXJzOiBJRElWLCBGQkRJViBhbmQNCj4gPiBPRElWLiBP\n" - "dXRwdXQgY2xvY2sgdmFsdWUgaXMgbWFuYWdlZCB1c2luZyB0aGVzZSBkaXZpZGVycy4NCj4gPiAN\n" - "Cj4gPiBXZSBhZGQgcHJlLWRlZmluZWQgdGFibGVzIHdpdGggc3VwcG9ydGVkIHJhdGUgdmFsdWVz\n" - "IGFuZA0KPiA+IGFwcHJvcHJpYXRlDQo+ID4gY29uZmlndXJhdGlvbnMgb2YgSURJViwgRkJESVYg\n" - "YW5kIE9ESVYgZm9yIGVhY2ggdmFsdWUuDQo+ID4gDQo+ID4gQXMgb2YgdG9kYXkgd2UgYWRkIHN1\n" - "cHBvcnQgZm9yIFBMTHMgdGhhdCBnZW5lcmF0ZSBjbG9jayBmb3IgdGhlDQo+ID4gZm9sbG93aW5n\n" - "IGRldmljZXM6DQo+ID4gwqAqIEFSQyBjb3JlIG9uIEFYQyBDUFUgdGlsZXMuDQo+ID4gwqAqIEFS\n" - "QyBQR1Ugb24gQVJDIFNEUCBNYWluYm9hcmQuDQo+ID4gYW5kIG1vcmUgdG8gY29tZSBsYXRlci4N\n" - "Cj4gPiANCj4gPiBCeSB0aGlzIHBhdGNoIHdlIGFkZCBzdXBwb3J0IGZvciB0d28gcGxscyAoYXJj\n" - "IGNvcmUgcGxsIGFuZCBwZ3UNCj4gPiBwbGwpLA0KPiA+IHNvIHdlIGhhZCB0byB1c2UgdHdvIGRp\n" - "ZmZlcmVudCBpbml0IHR5cGVzOiBDTEtfT0ZfREVDTEFSRSBmb3IgYXJjDQo+ID4gY29yZSBwbGwg\n" - "YW5kDQo+ID4gcmVndWxhciBwcm9iaW5nIGZvciBwZ3UgcGxsLg0KPiA+IA0KPiA+IEFja2VkLWJ5\n" - "OiBSb2IgSGVycmluZyA8cm9iaEBrZXJuZWwub3JnPg0KPiA+IEFja2VkLWJ5OiBKb3NlIEFicmV1\n" - "IDxqb2FicmV1QHN5bm9wc3lzLmNvbT4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBFdWdlbml5\n" - "IFBhbHRzZXYgPEV1Z2VuaXkuUGFsdHNldkBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i\n" - "eTogVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i\n" - "eTogSm9zZSBBYnJldSA8am9hYnJldUBzeW5vcHN5cy5jb20+DQo+IA0KPiBTb3JyeSB0aGlzIG1p\n" - "c3NlZCB0aGUgY3V0b2ZmIGZvciBuZXcgY29kZSBmb3IgdjQuMTMuIFNob3VsZCBiZSBpbg0KPiBj\n" - "bGstbmV4dCBuZXh0IHdlZWsgdGhvdWdoLg0KPiANCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGlj\n" - "IGlubGluZSBzdHJ1Y3QgYXhzMTB4X3BsbF9jbGsgKnRvX2F4czEweF9wbGxfY2xrKHN0cnVjdA0K\n" - "PiA+IGNsa19odyAqaHcpDQo+ID4gK3sNCj4gPiArCXJldHVybiBjb250YWluZXJfb2YoaHcsIHN0\n" - "cnVjdCBheHMxMHhfcGxsX2NsaywgaHcpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5s\n" - "aW5lIHUzMiBheHMxMHhfZGl2X2dldF92YWx1ZSh1MzIgcmVnKQ0KPiA+ICt7DQo+ID4gKwlpZiAo\n" - "UExMX1JFR19HRVRfQllQQVNTKHJlZykpDQo+ID4gKwkJcmV0dXJuIDE7DQo+ID4gKw0KPiA+ICsJ\n" - "cmV0dXJuIFBMTF9SRUdfR0VUX0hJR0gocmVnKSArIFBMTF9SRUdfR0VUX0xPVyhyZWcpOw0KPiA+\n" - "ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5saW5lIHUzMiBheHMxMHhfZW5jb2RlX2Rpdih1bnNp\n" - "Z25lZCBpbnQgaWQsIGludCB1cGQpDQo+ID4gK3sNCj4gPiArCXUzMiBkaXYgPSAwOw0KPiA+ICsN\n" - "Cj4gPiArCVBMTF9SRUdfU0VUX0xPVyhkaXYsIChpZCAlIDIgPT0gMCkgPyBpZCA+PiAxIDogKGlk\n" - "ID4+IDEpICsNCj4gPiAxKTsNCj4gPiArCVBMTF9SRUdfU0VUX0hJR0goZGl2LCBpZCA+PiAxKTsN\n" - "Cj4gPiArCVBMTF9SRUdfU0VUX0VER0UoZGl2LCBpZCAlIDIpOw0KPiA+ICsJUExMX1JFR19TRVRf\n" - "QllQQVNTKGRpdiwgaWQgPT0gMSA/IDEgOiAwKTsNCj4gPiArCVBMTF9SRUdfU0VUX05PVVBEKGRp\n" - "diwgIXVwZCk7DQo+IA0KPiBTbyBzcGFyc2UgY29tcGxhaW5zIGhlcmUgYWJvdXQgYSAiZHViaW91\n" - "cyAheCAmIHkiLiBQZXJoYXBzIHRoaXMNCj4gY2FuIGJlIGNoYW5nZWQgdG8NCj4gDQo+IAlQTExf\n" - "UkVHX1NFVF9OT1VQRChkaXYsIHVwZCA9PSAwID8gMSA6IDApOw0KPiANCj4gVGhhdCB3YXkgc3Bh\n" - "cnNlIGRvZXNuJ3QgY29tcGxhaW4uIEkgY2FuIG1ha2UgdGhlIGNoYW5nZSB3aGVuDQo+IGFwcGx5\n" - "aW5nIGlmIHlvdSBhZ3JlZS4NCg0KU3VyZSwgdGhhbmtzIGEgbG90Lg0KDQotLSANCsKgRXVnZW5p\n" - eSBQYWx0c2V2 + "On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:\n" + "> On 06/21, Eugeniy Paltsev wrote:\n" + "> > AXS10X boards manages it's clocks using various PLLs. These PLL has\n" + "> > same\n" + "> > dividers and corresponding control registers mapped to different\n" + "> > addresses.\n" + "> > So we add one common driver for such PLLs.\n" + "> > \n" + "> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and\n" + "> > ODIV. Output clock value is managed using these dividers.\n" + "> > \n" + "> > We add pre-defined tables with supported rate values and\n" + "> > appropriate\n" + "> > configurations of IDIV, FBDIV and ODIV for each value.\n" + "> > \n" + "> > As of today we add support for PLLs that generate clock for the\n" + "> > following devices:\n" + "> > \302\240* ARC core on AXC CPU tiles.\n" + "> > \302\240* ARC PGU on ARC SDP Mainboard.\n" + "> > and more to come later.\n" + "> > \n" + "> > By this patch we add support for two plls (arc core pll and pgu\n" + "> > pll),\n" + "> > so we had to use two different init types: CLK_OF_DECLARE for arc\n" + "> > core pll and\n" + "> > regular probing for pgu pll.\n" + "> > \n" + "> > Acked-by: Rob Herring <robh@kernel.org>\n" + "> > Acked-by: Jose Abreu <joabreu@synopsys.com>\n" + "> > \n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" + "> > Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>\n" + "> > Signed-off-by: Jose Abreu <joabreu@synopsys.com>\n" + "> \n" + "> Sorry this missed the cutoff for new code for v4.13. Should be in\n" + "> clk-next next week though.\n" + "> \n" + "> > +}\n" + "> > +\n" + "> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct\n" + "> > clk_hw *hw)\n" + "> > +{\n" + "> > +\treturn container_of(hw, struct axs10x_pll_clk, hw);\n" + "> > +}\n" + "> > +\n" + "> > +static inline u32 axs10x_div_get_value(u32 reg)\n" + "> > +{\n" + "> > +\tif (PLL_REG_GET_BYPASS(reg))\n" + "> > +\t\treturn 1;\n" + "> > +\n" + "> > +\treturn PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);\n" + "> > +}\n" + "> > +\n" + "> > +static inline u32 axs10x_encode_div(unsigned int id, int upd)\n" + "> > +{\n" + "> > +\tu32 div = 0;\n" + "> > +\n" + "> > +\tPLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +\n" + "> > 1);\n" + "> > +\tPLL_REG_SET_HIGH(div, id >> 1);\n" + "> > +\tPLL_REG_SET_EDGE(div, id % 2);\n" + "> > +\tPLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);\n" + "> > +\tPLL_REG_SET_NOUPD(div, !upd);\n" + "> \n" + "> So sparse complains here about a \"dubious !x & y\". Perhaps this\n" + "> can be changed to\n" + "> \n" + "> \tPLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);\n" + "> \n" + "> That way sparse doesn't complain. I can make the change when\n" + "> applying if you agree.\n" + "\n" + "Sure, thanks a lot.\n" + "\n" + "-- \n" + "\302\240Eugeniy Paltsev" -970d7bfeb7c447778e8a5603f0809bc3536a50e704affca77ea3148ecd57b4ee +3a86d33bba710500fd2646dedda8385c3f84240507082e00e90af571467c7c47
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