From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
To: "sboyd@codeaurora.org" <sboyd@codeaurora.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Eugeniy.Paltsev@synopsys.com" <Eugeniy.Paltsev@synopsys.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>
Subject: Re: [PATCH v4] clk: axs10x: introduce AXS10X pll driver
Date: Wed, 12 Jul 2017 08:01:43 +0000 [thread overview]
Message-ID: <1499846503.9320.1.camel@synopsys.com> (raw)
In-Reply-To: <20170712052535.GY22780@codeaurora.org>
T24gVHVlLCAyMDE3LTA3LTExIGF0IDIyOjI1IC0wNzAwLCBTdGVwaGVuIEJveWQgd3JvdGU6DQo+
IE9uIDA2LzIxLCBFdWdlbml5IFBhbHRzZXYgd3JvdGU6DQo+ID4gQVhTMTBYIGJvYXJkcyBtYW5h
Z2VzIGl0J3MgY2xvY2tzIHVzaW5nIHZhcmlvdXMgUExMcy4gVGhlc2UgUExMIGhhcw0KPiA+IHNh
bWUNCj4gPiBkaXZpZGVycyBhbmQgY29ycmVzcG9uZGluZyBjb250cm9sIHJlZ2lzdGVycyBtYXBw
ZWQgdG8gZGlmZmVyZW50DQo+ID4gYWRkcmVzc2VzLg0KPiA+IFNvIHdlIGFkZCBvbmUgY29tbW9u
IGRyaXZlciBmb3Igc3VjaCBQTExzLg0KPiA+IA0KPiA+IEVhY2ggUExMIG9uIEFYUzEwWCBib2Fy
ZCBjb25zaXN0IG9mIHRocmVlIGRpdmlkZXJzOiBJRElWLCBGQkRJViBhbmQNCj4gPiBPRElWLiBP
dXRwdXQgY2xvY2sgdmFsdWUgaXMgbWFuYWdlZCB1c2luZyB0aGVzZSBkaXZpZGVycy4NCj4gPiAN
Cj4gPiBXZSBhZGQgcHJlLWRlZmluZWQgdGFibGVzIHdpdGggc3VwcG9ydGVkIHJhdGUgdmFsdWVz
IGFuZA0KPiA+IGFwcHJvcHJpYXRlDQo+ID4gY29uZmlndXJhdGlvbnMgb2YgSURJViwgRkJESVYg
YW5kIE9ESVYgZm9yIGVhY2ggdmFsdWUuDQo+ID4gDQo+ID4gQXMgb2YgdG9kYXkgd2UgYWRkIHN1
cHBvcnQgZm9yIFBMTHMgdGhhdCBnZW5lcmF0ZSBjbG9jayBmb3IgdGhlDQo+ID4gZm9sbG93aW5n
IGRldmljZXM6DQo+ID4gwqAqIEFSQyBjb3JlIG9uIEFYQyBDUFUgdGlsZXMuDQo+ID4gwqAqIEFS
QyBQR1Ugb24gQVJDIFNEUCBNYWluYm9hcmQuDQo+ID4gYW5kIG1vcmUgdG8gY29tZSBsYXRlci4N
Cj4gPiANCj4gPiBCeSB0aGlzIHBhdGNoIHdlIGFkZCBzdXBwb3J0IGZvciB0d28gcGxscyAoYXJj
IGNvcmUgcGxsIGFuZCBwZ3UNCj4gPiBwbGwpLA0KPiA+IHNvIHdlIGhhZCB0byB1c2UgdHdvIGRp
ZmZlcmVudCBpbml0IHR5cGVzOiBDTEtfT0ZfREVDTEFSRSBmb3IgYXJjDQo+ID4gY29yZSBwbGwg
YW5kDQo+ID4gcmVndWxhciBwcm9iaW5nIGZvciBwZ3UgcGxsLg0KPiA+IA0KPiA+IEFja2VkLWJ5
OiBSb2IgSGVycmluZyA8cm9iaEBrZXJuZWwub3JnPg0KPiA+IEFja2VkLWJ5OiBKb3NlIEFicmV1
IDxqb2FicmV1QHN5bm9wc3lzLmNvbT4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBFdWdlbml5
IFBhbHRzZXYgPEV1Z2VuaXkuUGFsdHNldkBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i
eTogVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+DQo+ID4gU2lnbmVkLW9mZi1i
eTogSm9zZSBBYnJldSA8am9hYnJldUBzeW5vcHN5cy5jb20+DQo+IA0KPiBTb3JyeSB0aGlzIG1p
c3NlZCB0aGUgY3V0b2ZmIGZvciBuZXcgY29kZSBmb3IgdjQuMTMuIFNob3VsZCBiZSBpbg0KPiBj
bGstbmV4dCBuZXh0IHdlZWsgdGhvdWdoLg0KPiANCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGlj
IGlubGluZSBzdHJ1Y3QgYXhzMTB4X3BsbF9jbGsgKnRvX2F4czEweF9wbGxfY2xrKHN0cnVjdA0K
PiA+IGNsa19odyAqaHcpDQo+ID4gK3sNCj4gPiArCXJldHVybiBjb250YWluZXJfb2YoaHcsIHN0
cnVjdCBheHMxMHhfcGxsX2NsaywgaHcpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5s
aW5lIHUzMiBheHMxMHhfZGl2X2dldF92YWx1ZSh1MzIgcmVnKQ0KPiA+ICt7DQo+ID4gKwlpZiAo
UExMX1JFR19HRVRfQllQQVNTKHJlZykpDQo+ID4gKwkJcmV0dXJuIDE7DQo+ID4gKw0KPiA+ICsJ
cmV0dXJuIFBMTF9SRUdfR0VUX0hJR0gocmVnKSArIFBMTF9SRUdfR0VUX0xPVyhyZWcpOw0KPiA+
ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW5saW5lIHUzMiBheHMxMHhfZW5jb2RlX2Rpdih1bnNp
Z25lZCBpbnQgaWQsIGludCB1cGQpDQo+ID4gK3sNCj4gPiArCXUzMiBkaXYgPSAwOw0KPiA+ICsN
Cj4gPiArCVBMTF9SRUdfU0VUX0xPVyhkaXYsIChpZCAlIDIgPT0gMCkgPyBpZCA+PiAxIDogKGlk
ID4+IDEpICsNCj4gPiAxKTsNCj4gPiArCVBMTF9SRUdfU0VUX0hJR0goZGl2LCBpZCA+PiAxKTsN
Cj4gPiArCVBMTF9SRUdfU0VUX0VER0UoZGl2LCBpZCAlIDIpOw0KPiA+ICsJUExMX1JFR19TRVRf
QllQQVNTKGRpdiwgaWQgPT0gMSA/IDEgOiAwKTsNCj4gPiArCVBMTF9SRUdfU0VUX05PVVBEKGRp
diwgIXVwZCk7DQo+IA0KPiBTbyBzcGFyc2UgY29tcGxhaW5zIGhlcmUgYWJvdXQgYSAiZHViaW91
cyAheCAmIHkiLiBQZXJoYXBzIHRoaXMNCj4gY2FuIGJlIGNoYW5nZWQgdG8NCj4gDQo+IAlQTExf
UkVHX1NFVF9OT1VQRChkaXYsIHVwZCA9PSAwID8gMSA6IDApOw0KPiANCj4gVGhhdCB3YXkgc3Bh
cnNlIGRvZXNuJ3QgY29tcGxhaW4uIEkgY2FuIG1ha2UgdGhlIGNoYW5nZSB3aGVuDQo+IGFwcGx5
aW5nIGlmIHlvdSBhZ3JlZS4NCg0KU3VyZSwgdGhhbmtzIGEgbG90Lg0KDQotLSANCsKgRXVnZW5p
eSBQYWx0c2V2
WARNING: multiple messages have this Message-ID (diff)
From: Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH v4] clk: axs10x: introduce AXS10X pll driver
Date: Wed, 12 Jul 2017 08:01:43 +0000 [thread overview]
Message-ID: <1499846503.9320.1.camel@synopsys.com> (raw)
In-Reply-To: <20170712052535.GY22780@codeaurora.org>
On Tue, 2017-07-11@22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
> > So we add one common driver for such PLLs.
> >
> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > ODIV. Output clock value is managed using these dividers.
> >
> > We add pre-defined tables with supported rate values and
> > appropriate
> > configurations of IDIV, FBDIV and ODIV for each value.
> >
> > As of today we add support for PLLs that generate clock for the
> > following devices:
> > ?* ARC core on AXC CPU tiles.
> > ?* ARC PGU on ARC SDP Mainboard.
> > and more to come later.
> >
> > By this patch we add support for two plls (arc core pll and pgu
> > pll),
> > so we had to use two different init types: CLK_OF_DECLARE for arc
> > core pll and
> > regular probing for pgu pll.
> >
> > Acked-by: Rob Herring <robh at kernel.org>
> > Acked-by: Jose Abreu <joabreu at synopsys.com>
> >
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
> > Signed-off-by: Vlad Zakharov <vzakhar at synopsys.com>
> > Signed-off-by: Jose Abreu <joabreu at synopsys.com>
>
> Sorry this missed the cutoff for new code for v4.13. Should be in
> clk-next next week though.
>
> > +}
> > +
> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct
> > clk_hw *hw)
> > +{
> > + return container_of(hw, struct axs10x_pll_clk, hw);
> > +}
> > +
> > +static inline u32 axs10x_div_get_value(u32 reg)
> > +{
> > + if (PLL_REG_GET_BYPASS(reg))
> > + return 1;
> > +
> > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
> > +}
> > +
> > +static inline u32 axs10x_encode_div(unsigned int id, int upd)
> > +{
> > + u32 div = 0;
> > +
> > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +
> > 1);
> > + PLL_REG_SET_HIGH(div, id >> 1);
> > + PLL_REG_SET_EDGE(div, id % 2);
> > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
> > + PLL_REG_SET_NOUPD(div, !upd);
>
> So sparse complains here about a "dubious !x & y". Perhaps this
> can be changed to
>
> PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
>
> That way sparse doesn't complain. I can make the change when
> applying if you agree.
Sure, thanks a lot.
--
?Eugeniy Paltsev
WARNING: multiple messages have this Message-ID (diff)
From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
To: "sboyd@codeaurora.org" <sboyd@codeaurora.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Eugeniy.Paltsev@synopsys.com" <Eugeniy.Paltsev@synopsys.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>
Subject: Re: [PATCH v4] clk: axs10x: introduce AXS10X pll driver
Date: Wed, 12 Jul 2017 08:01:43 +0000 [thread overview]
Message-ID: <1499846503.9320.1.camel@synopsys.com> (raw)
In-Reply-To: <20170712052535.GY22780@codeaurora.org>
On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
> > So we add one common driver for such PLLs.
> >
> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > ODIV. Output clock value is managed using these dividers.
> >
> > We add pre-defined tables with supported rate values and
> > appropriate
> > configurations of IDIV, FBDIV and ODIV for each value.
> >
> > As of today we add support for PLLs that generate clock for the
> > following devices:
> > * ARC core on AXC CPU tiles.
> > * ARC PGU on ARC SDP Mainboard.
> > and more to come later.
> >
> > By this patch we add support for two plls (arc core pll and pgu
> > pll),
> > so we had to use two different init types: CLK_OF_DECLARE for arc
> > core pll and
> > regular probing for pgu pll.
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Jose Abreu <joabreu@synopsys.com>
> >
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
> > Signed-off-by: Jose Abreu <joabreu@synopsys.com>
>
> Sorry this missed the cutoff for new code for v4.13. Should be in
> clk-next next week though.
>
> > +}
> > +
> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct
> > clk_hw *hw)
> > +{
> > + return container_of(hw, struct axs10x_pll_clk, hw);
> > +}
> > +
> > +static inline u32 axs10x_div_get_value(u32 reg)
> > +{
> > + if (PLL_REG_GET_BYPASS(reg))
> > + return 1;
> > +
> > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
> > +}
> > +
> > +static inline u32 axs10x_encode_div(unsigned int id, int upd)
> > +{
> > + u32 div = 0;
> > +
> > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +
> > 1);
> > + PLL_REG_SET_HIGH(div, id >> 1);
> > + PLL_REG_SET_EDGE(div, id % 2);
> > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
> > + PLL_REG_SET_NOUPD(div, !upd);
>
> So sparse complains here about a "dubious !x & y". Perhaps this
> can be changed to
>
> PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
>
> That way sparse doesn't complain. I can make the change when
> applying if you agree.
Sure, thanks a lot.
--
Eugeniy Paltsev
next prev parent reply other threads:[~2017-07-12 8:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-21 19:16 [PATCH v4] clk: axs10x: introduce AXS10X pll driver Eugeniy Paltsev
2017-06-21 19:16 ` Eugeniy Paltsev
2017-07-05 11:23 ` Eugeniy Paltsev
2017-07-05 11:23 ` Eugeniy Paltsev
2017-07-05 11:23 ` Eugeniy Paltsev
2017-07-12 5:25 ` Stephen Boyd
2017-07-12 5:25 ` Stephen Boyd
2017-07-12 8:01 ` Eugeniy Paltsev [this message]
2017-07-12 8:01 ` Eugeniy Paltsev
2017-07-12 8:01 ` Eugeniy Paltsev
2017-07-12 23:05 ` sboyd
2017-07-12 23:05 ` sboyd
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