[PATCH v3 0/2] Add platform support for Adaptrum Anarion SOC

[PATCH v3 0/2] Add platform support for Adaptrum Anarion SOC

[Alexandru Gagniuc]

Changes since v2:
 * Changed compatible binding of uart[1-3] to "ns16550" (they are not DW UARTs)
 * Add support under plat-nsim instead of creating a new stub platform
 * Changed board model to "adaptrum,endor-fpga" to allow LEDE scripts to ID the board
 * Prefix compatible binding with 'arc-'

Changes since v1:
 * Updated CPU core clock to 24 MHz to match HW changes.

Alexandru Gagniuc (2):
  ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
  ARC: DTS: Add device-tree for Anarion-based development board

 arch/arc/boot/dts/adaptrum_anarion.dtsi     | 110 ++++++++++++++++++++++++++++
 arch/arc/boot/dts/adaptrum_anarion_fpga.dts |  51 +++++++++++++
 arch/arc/plat-sim/platform.c                |   1 +
 3 files changed, 162 insertions(+)
 create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
 create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts

-- 
2.9.3

[PATCH v3 1/2] ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC

[Alexandru Gagniuc]

Anarion does not require any special configuration during early boot.
This is compatible with nsim, hence-why it is added here.

As development continues, should we need to add any drivers via
Kconfig, we can do that by adding and sourcing a "Kconfig.anarion".
This approach was chosen --as opposed to adding plat-anarion/--
because it doesn't add a bunch of extra files.

Signed-off-by: Alexandru Gagniuc <alex.g at adaptrum.com>
---
 arch/arc/plat-sim/platform.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arc/plat-sim/platform.c b/arch/arc/plat-sim/platform.c
index 5cda56b..a5dbfab 100644
--- a/arch/arc/plat-sim/platform.c
+++ b/arch/arc/plat-sim/platform.c
@@ -21,6 +21,7 @@
 
 static const char *simulation_compat[] __initconst = {
 #ifdef CONFIG_ISA_ARCOMPACT
+	"adaptrum,arc-anarion",
 	"snps,nsim",
 	"snps,nsimosci",
 #else
-- 
2.9.3

[PATCH v3 2/2] ARC: DTS: Add device-tree for Anarion-based development board

[Alexandru Gagniuc]

This is split into the SOC bindings, and the board dts. The Endor
board is currently an FPGA emulation. Once real, silicon arrives, we
plan to remove Endor support.

Signed-off-by: Alexandru Gagniuc <alex.g at adaptrum.com>
---
 arch/arc/boot/dts/adaptrum_anarion.dtsi     | 110 ++++++++++++++++++++++++++++
 arch/arc/boot/dts/adaptrum_anarion_fpga.dts |  51 +++++++++++++
 2 files changed, 161 insertions(+)
 create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
 create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts

diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi b/arch/arc/boot/dts/adaptrum_anarion.dtsi
new file mode 100644
index 0000000..e177a24
--- /dev/null
+++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Skeleton for Adaptrum Anarion SOC
+ *
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for Adaptrum, Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
+
+/* This skeleton is based on the ARC700 CPU */
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "adaptrum,anarion";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	soc {
+		compatible = "simple-bus";
+		device_type = "soc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&core_intc>;
+
+		core_intc: interrupt-controller {
+			compatible = "snps,arc700-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		uart0: serial at f2202100 {
+			compatible = "ns16550";
+			reg = <0xf2202100 0x20>;
+			interrupts = <8>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <192000000>;
+			status = "disabled";
+		};
+
+		uart1: serial at f2202200 {
+			compatible = "ns16550";
+			reg = <0xf2202200 0x20>;
+			interrupts = <8>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <192000000>;
+			status = "disabled";
+		};
+
+		uart2: serial at f2202300 {
+			compatible = "ns16550";
+			reg = <0xf2202300 0x20>;
+			interrupts = <8>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <192000000>;
+			status = "disabled";
+		};
+
+		uart3: serial at f2202400 {
+			compatible = "ns16550";
+			reg = <0xf2202400 0x20>;
+			interrupts = <8>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <192000000>;
+			status = "disabled";
+		};
+
+		qspi: qspi at f200f000 {
+			compatible = "adaptrum,anarion-qspi";
+			reg = <0xf200f000 0x1000>,
+			      <0x20000000 0x08000000>;
+
+			interrupts = <10>;
+			status = "disabled";
+		};
+
+		gmac0: ethernet at f2010000 {
+			compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+			reg = <0xf2010000 0x4000>;
+
+			interrupt-parent = <&core_intc>;
+			interrupts = <20>;
+			interrupt-names = "macirq";
+
+			clocks = <&core_clk>;
+			clock-names = "stmmaceth";
+
+			snps,pbl = <32>;
+			status = "disabled";
+		};
+
+		gmac1: ethernet at f2014000 {
+			compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+			reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+			interrupt-parent = <&core_intc>;
+			interrupts = <21>;
+			interrupt-names = "macirq";
+
+			clocks = <&core_clk>;
+			clock-names = "stmmaceth";
+
+			snps,pbl = <32>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arc/boot/dts/adaptrum_anarion_fpga.dts b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
new file mode 100644
index 0000000..6b2e22f
--- /dev/null
+++ b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
@@ -0,0 +1,51 @@
+/*
+ * Adaptrum Endor -- Anarion based FPGA emulation platform
+ *
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for Adaptrum, Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
+
+/dts-v1/;
+
+#include "adaptrum_anarion.dtsi"
+
+/ {
+	model = "adaptrum,endor-fpga";
+	compatible = "adaptrum,arc-anarion";
+
+	chosen {
+		bootargs = "earlycon console=ttyS0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	core_clk: core_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	flash0: w25q128fvn at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <70000000>;
+		m25p,fast-read;
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	status = "okay";
+};
-- 
2.9.3

[PATCH v3 2/2] ARC: DTS: Add device-tree for Anarion-based development board

[Eugeniy Paltsev]

Hi Alexandru,

On Wed, 2017-08-16@15:15 -0700, Alexandru Gagniuc wrote:
> This is split into the SOC bindings, and the board dts. The Endor
> board is currently an FPGA emulation. Once real, silicon arrives, we
> plan to remove Endor support.
> 
> Signed-off-by: Alexandru Gagniuc <alex.g at adaptrum.com>
> ---
> ?arch/arc/boot/dts/adaptrum_anarion.dtsi?????| 110
> ++++++++++++++++++++++++++++
> ?arch/arc/boot/dts/adaptrum_anarion_fpga.dts |??51 +++++++++++++
> ?2 files changed, 161 insertions(+)
> ?create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
> ?create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
> 
> diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi
> b/arch/arc/boot/dts/adaptrum_anarion.dtsi
> new file mode 100644
> index 0000000..e177a24
> --- /dev/null
> +++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi
> @@ -0,0 +1,110 @@
> +/*
> + * Skeleton for Adaptrum Anarion SOC
> + *
> + * (C) Copyright 2017 Adaptrum, Inc.
> + * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for Adaptrum,
> Inc.
> + * Licensed under the GPLv2 or (at your option) any later version
> + */
> +
> +/* This skeleton is based on the ARC700 CPU */
> +#include "skeleton.dtsi"

Perhaps it is better not to use skeleton.dtsi as we are planning to
get rid of it.

-- 
?Eugeniy Paltsev

[PATCH v3 2/2] ARC: DTS: Add device-tree for Anarion-based development board

[Eugeniy Paltsev]

On Thu, 2017-08-17@11:11 +0000, Eugeniy Paltsev wrote:
> Hi Alexandru,
> 
> On Wed, 2017-08-16@15:15 -0700, Alexandru Gagniuc wrote:
> > This is split into the SOC bindings, and the board dts. The Endor
> > board is currently an FPGA emulation. Once real, silicon arrives,
> > we
> > plan to remove Endor support.
> > 
> > Signed-off-by: Alexandru Gagniuc <alex.g at adaptrum.com>
> > ---
> > ?arch/arc/boot/dts/adaptrum_anarion.dtsi?????| 110
> > ++++++++++++++++++++++++++++
> > ?arch/arc/boot/dts/adaptrum_anarion_fpga.dts |??51 +++++++++++++
> > ?2 files changed, 161 insertions(+)
> > ?create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
> > ?create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
> > 
> > diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi
> > b/arch/arc/boot/dts/adaptrum_anarion.dtsi
> > new file mode 100644
> > index 0000000..e177a24
> > --- /dev/null
> > +++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi
> > @@ -0,0 +1,110 @@
> > +/*
> > + * Skeleton for Adaptrum Anarion SOC
> > + *
> > + * (C) Copyright 2017 Adaptrum, Inc.
> > + * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for
> > Adaptrum,
> > Inc.
> > + * Licensed under the GPLv2 or (at your option) any later version
> > + */
> > +
> > +/* This skeleton is based on the ARC700 CPU */
> > +#include "skeleton.dtsi"
> 
Perhaps it is better not to use skeleton.dtsi as we are planning to
get rid of it.

---
Little more explanation:

We faced with fact what we had to override almost all nodes defined in
skeleton.dtsi (and other skeletons files like skeleton_hs_idu.dtsi) for
our boards. Only the timers nodes are left not overridden.
So there is no much sense in skeletons files using and that's why we
are planning to get rid of it.

> --?
> ?Eugeniy Paltsev
> _______________________________________________
> linux-snps-arc mailing list
> linux-snps-arc at lists.infradead.org?
-- 
?Eugeniy Paltsev

[PATCH v3 2/2] ARC: DTS: Add device-tree for Anarion-based development board

[Alexey Brodkin]

Hi Alexandru,

On Wed, 2017-08-16@15:15 -0700, Alexandru Gagniuc wrote:
> +#include "skeleton.dtsi"

Eugeniy already commented on that - most probably you'll end up
overriding most if not all entries from "skeleton.dtsi" so why
bother with it at all?

And I don't see any mention of your own memory node so I assume you rely on
the one from our skeleton.dtsi? The first question is if it really matches your setup?
I.e. 256 Mb mapped to 0x8000_0000. And even if that's the case what if we change
this to something else later?

IMHO having your own "memory" node makes some sens :)

> +
> +		gmac0: ethernet at f2010000 {
> +			compatible = "adaptrum,anarion-gmac", "snps,dwmac";
> +			reg = <0xf2010000 0x4000>;
> +
> +			interrupt-parent = <&core_intc>;

You already specified default INTC above, so you may just drop "interrupt-parent"
property from this node.

> +
> +		gmac1: ethernet at f2014000 {
> +			compatible = "adaptrum,anarion-gmac", "snps,dwmac";
> +			reg = <0xf2014000 0x4000>, <0xf2018100 8>;
> +
> +			interrupt-parent = <&core_intc>;

Ditto.

-Alexey

[PATCH v3 0/2] Add platform support for Adaptrum Anarion SOC

[Vineet Gupta]

On 08/16/2017 03:15 PM, Alexandru Gagniuc wrote:
> Changes since v2:
>   * Changed compatible binding of uart[1-3] to "ns16550" (they are not DW UARTs)
>   * Add support under plat-nsim instead of creating a new stub platform
>   * Changed board model to "adaptrum,endor-fpga" to allow LEDE scripts to ID the board
>   * Prefix compatible binding with 'arc-'

Can you provide an updated version soon - it would be nice if it made into next 
merge window !

> 
> Changes since v1:
>   * Updated CPU core clock to 24 MHz to match HW changes.
> 
> Alexandru Gagniuc (2):
>    ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
>    ARC: DTS: Add device-tree for Anarion-based development board
> 
>   arch/arc/boot/dts/adaptrum_anarion.dtsi     | 110 ++++++++++++++++++++++++++++
>   arch/arc/boot/dts/adaptrum_anarion_fpga.dts |  51 +++++++++++++
>   arch/arc/plat-sim/platform.c                |   1 +
>   3 files changed, 162 insertions(+)
>   create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
>   create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
>