[v4 09/11] soc/fsl/qbman: different register offsets on ARM

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From: Roy Pledge <roy.pledge@nxp.com>
To: <leoyang.li@nxp.com>, <linuxppc-dev@lists.ozlabs.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <oss@buserror.net>, <madalin.bucur@nxp.com>,
	<catalin.marinas@arm.com>, <linux@armlinux.org.uk>,
	<arnd@arndb.de>, <mark.rutland@arm.com>,
	Claudiu Manoil <claudiu.manoil@nxp.com>,
	Roy Pledge <roy.pledge@nxp.com>
Subject: [v4 09/11] soc/fsl/qbman: different register offsets on ARM
Date: Thu, 24 Aug 2017 16:37:53 -0400	[thread overview]
Message-ID: <1503607075-28970-10-git-send-email-roy.pledge@nxp.com> (raw)
In-Reply-To: <1503607075-28970-1-git-send-email-roy.pledge@nxp.com>

From: Madalin Bucur <madalin.bucur@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 22 ++++++++++++++++++++++
 drivers/soc/fsl/qbman/qman.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index e31c843..265048d 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH	0x3000
+#define BM_REG_RCR_CI_CINH	0x3100
+#define BM_REG_RCR_ITR		0x3200
+#define BM_REG_CFG		0x3300
+#define BM_REG_SCN(n)		(0x3400 + ((n) << 6))
+#define BM_REG_ISR		0x3e00
+#define BM_REG_IER		0x3e40
+#define BM_REG_ISDR		0x3e80
+#define BM_REG_IIR		0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR		0x0000
+#define BM_CL_RR0		0x0100
+#define BM_CL_RR1		0x0140
+#define BM_CL_RCR		0x1000
+#define BM_CL_RCR_PI_CENA	0x3000
+#define BM_CL_RCR_CI_CENA	0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH	0x0000
 #define BM_REG_RCR_CI_CINH	0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR		0x1000
 #define BM_CL_RCR_PI_CENA	0x3000
 #define BM_CL_RCR_CI_CENA	0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 668fab1..fdd4c65 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH	0x3000
+#define QM_REG_EQCR_CI_CINH	0x3040
+#define QM_REG_EQCR_ITR		0x3080
+#define QM_REG_DQRR_PI_CINH	0x3100
+#define QM_REG_DQRR_CI_CINH	0x3140
+#define QM_REG_DQRR_ITR		0x3180
+#define QM_REG_DQRR_DCAP	0x31C0
+#define QM_REG_DQRR_SDQCR	0x3200
+#define QM_REG_DQRR_VDQCR	0x3240
+#define QM_REG_DQRR_PDQCR	0x3280
+#define QM_REG_MR_PI_CINH	0x3300
+#define QM_REG_MR_CI_CINH	0x3340
+#define QM_REG_MR_ITR		0x3380
+#define QM_REG_CFG		0x3500
+#define QM_REG_ISR		0x3600
+#define QM_REG_IER		0x3640
+#define QM_REG_ISDR		0x3680
+#define QM_REG_IIR		0x36C0
+#define QM_REG_ITPR		0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR		0x0000
+#define QM_CL_DQRR		0x1000
+#define QM_CL_MR		0x2000
+#define QM_CL_EQCR_PI_CENA	0x3000
+#define QM_CL_EQCR_CI_CENA	0x3040
+#define QM_CL_DQRR_PI_CENA	0x3100
+#define QM_CL_DQRR_CI_CENA	0x3140
+#define QM_CL_MR_PI_CENA	0x3300
+#define QM_CL_MR_CI_CENA	0x3340
+#define QM_CL_CR		0x3800
+#define QM_CL_RR0		0x3900
+#define QM_CL_RR1		0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH	0x0000
 #define QM_REG_EQCR_CI_CINH	0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR		0x3800
 #define QM_CL_RR0		0x3900
 #define QM_CL_RR1		0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)

From: roy.pledge@nxp.com (Roy Pledge)
To: linux-arm-kernel@lists.infradead.org
Subject: [v4 09/11] soc/fsl/qbman: different register offsets on ARM
Date: Thu, 24 Aug 2017 16:37:53 -0400	[thread overview]
Message-ID: <1503607075-28970-10-git-send-email-roy.pledge@nxp.com> (raw)
In-Reply-To: <1503607075-28970-1-git-send-email-roy.pledge@nxp.com>

From: Madalin Bucur <madalin.bucur@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 22 ++++++++++++++++++++++
 drivers/soc/fsl/qbman/qman.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index e31c843..265048d 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH	0x3000
+#define BM_REG_RCR_CI_CINH	0x3100
+#define BM_REG_RCR_ITR		0x3200
+#define BM_REG_CFG		0x3300
+#define BM_REG_SCN(n)		(0x3400 + ((n) << 6))
+#define BM_REG_ISR		0x3e00
+#define BM_REG_IER		0x3e40
+#define BM_REG_ISDR		0x3e80
+#define BM_REG_IIR		0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR		0x0000
+#define BM_CL_RR0		0x0100
+#define BM_CL_RR1		0x0140
+#define BM_CL_RCR		0x1000
+#define BM_CL_RCR_PI_CENA	0x3000
+#define BM_CL_RCR_CI_CENA	0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH	0x0000
 #define BM_REG_RCR_CI_CINH	0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR		0x1000
 #define BM_CL_RCR_PI_CENA	0x3000
 #define BM_CL_RCR_CI_CENA	0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 668fab1..fdd4c65 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH	0x3000
+#define QM_REG_EQCR_CI_CINH	0x3040
+#define QM_REG_EQCR_ITR		0x3080
+#define QM_REG_DQRR_PI_CINH	0x3100
+#define QM_REG_DQRR_CI_CINH	0x3140
+#define QM_REG_DQRR_ITR		0x3180
+#define QM_REG_DQRR_DCAP	0x31C0
+#define QM_REG_DQRR_SDQCR	0x3200
+#define QM_REG_DQRR_VDQCR	0x3240
+#define QM_REG_DQRR_PDQCR	0x3280
+#define QM_REG_MR_PI_CINH	0x3300
+#define QM_REG_MR_CI_CINH	0x3340
+#define QM_REG_MR_ITR		0x3380
+#define QM_REG_CFG		0x3500
+#define QM_REG_ISR		0x3600
+#define QM_REG_IER		0x3640
+#define QM_REG_ISDR		0x3680
+#define QM_REG_IIR		0x36C0
+#define QM_REG_ITPR		0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR		0x0000
+#define QM_CL_DQRR		0x1000
+#define QM_CL_MR		0x2000
+#define QM_CL_EQCR_PI_CENA	0x3000
+#define QM_CL_EQCR_CI_CENA	0x3040
+#define QM_CL_DQRR_PI_CENA	0x3100
+#define QM_CL_DQRR_CI_CENA	0x3140
+#define QM_CL_MR_PI_CENA	0x3300
+#define QM_CL_MR_CI_CENA	0x3340
+#define QM_CL_CR		0x3800
+#define QM_CL_RR0		0x3900
+#define QM_CL_RR1		0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH	0x0000
 #define QM_REG_EQCR_CI_CINH	0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR		0x3800
 #define QM_CL_RR0		0x3900
 #define QM_CL_RR1		0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

next prev parent reply	other threads:[~2017-08-24 20:38 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-24 20:37 [v4 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms Roy Pledge
2017-08-24 20:37 ` Roy Pledge
2017-08-24 20:37 ` [v4 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-09-14 13:46   ` Catalin Marinas
2017-09-14 13:46     ` Catalin Marinas
2017-08-24 20:37 ` [v4 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan " Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-08-24 20:37 ` [v4 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-09-14 13:47   ` Catalin Marinas
2017-09-14 13:47     ` Catalin Marinas
2017-08-24 20:37 ` [v4 04/11] soc/fsl/qbman: Drop set/clear_bits usage Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-08-24 20:37 ` [v4 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-09-14 13:49   ` Catalin Marinas
2017-09-14 13:49     ` Catalin Marinas
2017-09-14 18:30     ` Roy Pledge
2017-09-14 18:30       ` Roy Pledge
2017-09-14 18:30       ` Roy Pledge
2017-08-24 20:37 ` [v4 06/11] soc/fsl/qbman: Fix ARM32 typo Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-08-24 20:37 ` [v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-09-14 14:00   ` Catalin Marinas
2017-09-14 14:00     ` Catalin Marinas
2017-09-14 19:07     ` Roy Pledge
2017-09-14 19:07       ` Roy Pledge
2017-09-14 19:07       ` Roy Pledge
2017-09-15 21:49       ` Catalin Marinas
2017-09-15 21:49         ` Catalin Marinas
2017-09-18 18:48         ` Roy Pledge
2017-09-18 18:48           ` Roy Pledge
2017-09-18 18:48           ` Roy Pledge
2017-08-24 20:37 ` [v4 08/11] soc/fsl/qbman: add QMAN_REV32 Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-08-24 20:37 ` Roy Pledge [this message]
2017-08-24 20:37   ` [v4 09/11] soc/fsl/qbman: different register offsets on ARM Roy Pledge
2017-08-24 20:37 ` [v4 10/11] soc/fsl/qbman: Add missing headers " Roy Pledge
2017-08-24 20:37   ` Roy Pledge
2017-08-24 20:37 ` [v4 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config " Roy Pledge
2017-08-24 20:37   ` Roy Pledge

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