All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: [Qemu-arm] [PATCH 04/20] target/arm: Restore security state on exception return
Date: Fri, 22 Sep 2017 15:59:51 +0100	[thread overview]
Message-ID: <1506092407-26985-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1506092407-26985-1-git-send-email-peter.maydell@linaro.org>

Now that we can handle the CONTROL.SPSEL bit not necessarily being
in sync with the current stack pointer, we can restore the correct
security state on exception return. This happens before we start
to read registers off the stack frame, but after we have taken
possible usage faults for bad exception return magic values and
updated CONTROL.SPSEL.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 509a1aa..a3c63c3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6371,6 +6371,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
      */
     write_v7m_control_spsel(env, return_to_sp_process);
 
+    switch_v7m_security_state(env, return_to_secure);
+
     {
         /* The stack pointer we should be reading the exception frame from
          * depends on bits in the magic exception return type value (and
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return
Date: Fri, 22 Sep 2017 15:59:51 +0100	[thread overview]
Message-ID: <1506092407-26985-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1506092407-26985-1-git-send-email-peter.maydell@linaro.org>

Now that we can handle the CONTROL.SPSEL bit not necessarily being
in sync with the current stack pointer, we can restore the correct
security state on exception return. This happens before we start
to read registers off the stack frame, but after we have taken
possible usage faults for bad exception return magic values and
updated CONTROL.SPSEL.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 509a1aa..a3c63c3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6371,6 +6371,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
      */
     write_v7m_control_spsel(env, return_to_sp_process);
 
+    switch_v7m_security_state(env, return_to_secure);
+
     {
         /* The stack pointer we should be reading the exception frame from
          * depends on bits in the magic exception return type value (and
-- 
2.7.4

  parent reply	other threads:[~2017-09-22 15:01 UTC|newest]

Thread overview: 109+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 14:59 [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Peter Maydell
2017-09-22 14:59 ` [Qemu-devel] " Peter Maydell
2017-09-22 14:59 ` [Qemu-arm] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-09-23  0:34   ` [Qemu-arm] " Richard Henderson
2017-09-23  0:34     ` Richard Henderson
2017-09-29 21:03   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-29 21:03     ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-09-22 14:59 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-05  4:44   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05  4:44     ` Philippe Mathieu-Daudé
2017-10-05 16:04   ` [Qemu-arm] " Richard Henderson
2017-10-05 16:04     ` Richard Henderson
2017-10-05 16:20     ` Peter Maydell
2017-10-06 13:22       ` [Qemu-arm] " Peter Maydell
2017-10-06 13:22         ` Peter Maydell
2017-10-06 13:24         ` [Qemu-arm] " Richard Henderson
2017-10-06 13:24           ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05  3:25   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05  3:25     ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-10-05 16:09   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 16:09     ` Richard Henderson
2017-09-22 14:59 ` Peter Maydell [this message]
2017-09-22 14:59   ` [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-05 16:14   ` [Qemu-arm] " Richard Henderson
2017-10-05 16:14     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05 16:18   ` [Qemu-arm] " Richard Henderson
2017-10-05 16:18     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05 16:25   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-09-29 21:05   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:28   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-09-29 21:07   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-29 21:07     ` Philippe Mathieu-Daudé
2017-10-05 16:32   ` [Qemu-arm] " Richard Henderson
2017-10-05 16:32     ` Richard Henderson
2017-10-05 16:34     ` [Qemu-arm] " Richard Henderson
2017-10-05 16:34       ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05 16:39   ` [Qemu-arm] " Richard Henderson
2017-10-05 16:39     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 10/20] target/arm: Update excret sanity checks for v8M Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05 17:16   ` [Qemu-arm] " Richard Henderson
2017-10-05 17:16     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context Peter Maydell
2017-10-05 17:30   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-arm] [PATCH 12/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-09-22 14:59   ` [Qemu-devel] " Peter Maydell
2017-10-05 18:31   ` [Qemu-arm] " Richard Henderson
2017-10-05 18:31     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 13/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05 18:33   ` [Qemu-arm] " Richard Henderson
2017-10-05 18:33     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05 18:39   ` [Qemu-arm] " Richard Henderson
2017-10-05 18:39     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05  4:46   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05  4:46     ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-10-05 18:41   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 18:41     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05  3:29   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:42   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 18:42     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-09-22 17:18   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2017-10-05 18:50   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 18:50     ` Richard Henderson
2017-10-05 18:55     ` [Qemu-arm] " Peter Maydell
2017-10-05 18:55       ` Peter Maydell
2017-10-05 18:57       ` [Qemu-arm] " Richard Henderson
2017-10-05 18:57         ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 18/20] target/arm: Implement BLXNS Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05 13:07   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 13:07     ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-10-05 18:56   ` [Qemu-devel] " Richard Henderson
2017-10-05 19:40     ` [Qemu-arm] " Peter Maydell
2017-10-05 19:40       ` Peter Maydell
2017-09-22 15:00 ` [Qemu-arm] [PATCH 19/20] target/arm: Implement secure function return Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05 13:11   ` [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 13:11     ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-10-05 19:00   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 19:00     ` Richard Henderson
2017-09-22 15:00 ` [Qemu-arm] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-09-22 15:00   ` [Qemu-devel] " Peter Maydell
2017-10-05  4:33   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:01   ` [Qemu-arm] [Qemu-devel] " Richard Henderson
2017-10-05 19:01     ` Richard Henderson
2017-10-05  4:51 ` [Qemu-devel] [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Philippe Mathieu-Daudé
2017-10-06 13:29 ` Peter Maydell
2017-10-06 13:29   ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1506092407-26985-5-git-send-email-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=patches@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.