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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface
Date: Mon, 23 Oct 2017 07:04:00 +0000	[thread overview]
Message-ID: <1508742240.3650.16.camel@intel.com> (raw)
In-Reply-To: <1507882137-27841-4-git-send-email-tien.fong.chee@intel.com>

On Jum, 2017-10-13 at 16:08 +0800, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 10
> SoCFPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  cmd/fpga.c            |  2 +-
>  drivers/fpga/altera.c | 40 ++++++++++++++++++++++++++++++++--------
>  drivers/fpga/fpga.c   |  8 ++++++++
>  include/fpga.h        |  2 ++
>  4 files changed, 43 insertions(+), 9 deletions(-)
> 
> diff --git a/cmd/fpga.c b/cmd/fpga.c
> index ac6f504..3cb0bcd 100644
> --- a/cmd/fpga.c
> +++ b/cmd/fpga.c
Add more reviewers.

> @@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
>  	   "(Xilinx only)\n"
>  #endif
>  #if defined(CONFIG_CMD_FPGA_LOADFS)
> -	   "Load device from filesystem (FAT by default) (Xilinx
> only)\n"
> +	   "Load device from filesystem (FAT by default)\n"
>  	   "  loadfs [dev] [address] [image size] [blocksize]
> <interface>\n"
>  	   "        [<dev[:part]>] <filename>\n"
>  #endif
> diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
> index 135a357..a03e835 100644
> --- a/drivers/fpga/altera.c
> +++ b/drivers/fpga/altera.c
> @@ -23,25 +23,31 @@ static const struct altera_fpga {
>  	enum altera_family	family;
>  	const char		*name;
>  	int			(*load)(Altera_desc *, const void
> *, size_t);
> +	int (*loadfs)(Altera_desc *, const void *, size_t,
> fpga_fs_info *);
>  	int			(*dump)(Altera_desc *, const void
> *, size_t);
>  	int			(*info)(Altera_desc *);
>  } altera_fpga[] = {
>  #if defined(CONFIG_FPGA_ACEX1K)
> -	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump,
> ACEX1K_info },
> -	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump,
> ACEX1K_info },
> +	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
> +	 ACEX1K_info },
> +	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
> +	 ACEX1K_info },
>  #elif defined(CONFIG_FPGA_CYCLON2)
> -	{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump,
> CYC2_info },
> -	{ Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump,
> CYC2_info },
> +	{ Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump,
> CYC2_info },
> +	{ Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump,
> CYC2_info },
>  #endif
>  #if defined(CONFIG_FPGA_STRATIX_II)
> -	{ Altera_StratixII, "StratixII", StratixII_load,
> +	{ Altera_StratixII, "StratixII", StratixII_load, NULL,
>  	  StratixII_dump, StratixII_info },
>  #endif
>  #if defined(CONFIG_FPGA_STRATIX_V)
> -	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
> +	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL,
> NULL },
>  #endif
> -#if defined(CONFIG_FPGA_SOCFPGA)
> -	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
> +#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)
> +	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs,
> NULL,
> +	 NULL },
> +#elif defined(CONFIG_FPGA_SOCFPGA)
> +	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL
> },
>  #endif
>  };
>  
> @@ -174,3 +180,21 @@ int altera_info(Altera_desc *desc)
>  
>  	return FPGA_SUCCESS;
>  }
> +
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
> +		   fpga_fs_info *fpga_fsinfo)
> +{
> +	const struct altera_fpga *fpga = altera_desc_to_fpga(desc,
> __func__);
> +
> +	if (!fpga)
> +		return FPGA_FAIL;
> +
> +	debug_cond(FPGA_DEBUG, "%s: Launching the %s FS
> Loader...\n",
> +		   __func__, fpga->name);
> +	if (fpga->loadfs)
> +		return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
> +
> +	return -EINVAL;
> +}
> +#endif
> diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
> index e0fb1b4..42e901e 100644
> --- a/drivers/fpga/fpga.c
> +++ b/drivers/fpga/fpga.c
> @@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf,
> size_t size,
>  			fpga_no_sup((char *)__func__, "Xilinx
> devices");
>  #endif
>  			break;
> +#if defined(CONFIG_FPGA_ALTERA)
> +		case fpga_altera:
> +			ret_val = altera_loadfs(desc->devdesc, buf,
> size,
> +						fpga_fsinfo);
> +#else
> +			fpga_no_sup((char *)__func__, "Altera
> devices");
> +#endif
> +			break;
>  		default:
>  			printf("%s: Invalid or unsupported device
> type %d\n",
>  			       __func__, desc->devtype);
> diff --git a/include/fpga.h b/include/fpga.h
> index d768fb1..8920016 100644
> --- a/include/fpga.h
> +++ b/include/fpga.h
> @@ -56,8 +56,10 @@ int fpga_count(void);
>  const fpga_desc *const fpga_get_desc(int devnum);
>  int fpga_load(int devnum, const void *buf, size_t bsize,
>  	      bitstream_type bstype);
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>  int fpga_fsload(int devnum, const void *buf, size_t size,
>  		fpga_fs_info *fpga_fsinfo);
> +#endif
>  int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
>  		       bitstream_type bstype);
>  int fpga_dump(int devnum, const void *buf, size_t bsize);

  parent reply	other threads:[~2017-10-23  7:04 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-13  8:08 [U-Boot] [PATCH v3 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface tien.fong.chee at intel.com
2017-10-16 12:39   ` Dinh Nguyen
2017-10-23  6:46     ` Chee, Tien Fong
2017-10-23  7:04   ` Chee, Tien Fong [this message]
2017-10-13  8:08 ` [U-Boot] [PATCH v3 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 05/20] fs: Enable generic filesystems interface support in SPL tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system tien.fong.chee at intel.com
2017-10-16 14:08   ` Dinh Nguyen
2017-10-16 14:41     ` Marek Vasut
2017-10-23  6:37       ` Chee, Tien Fong
2017-10-26 12:51         ` Lukasz Majewski
2017-10-27  9:23           ` Chee, Tien Fong
2017-10-27 10:35             ` Lukasz Majewski
2017-10-28 11:32               ` Marek Vasut
2017-10-28 21:43                 ` Lukasz Majewski
2017-10-29  9:35                   ` Marek Vasut
2017-10-29 22:57                     ` Lukasz Majewski
2017-10-29 22:59                       ` Marek Vasut
2017-10-13  8:08 ` [U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct polling status bit tien.fong.chee at intel.com
2017-10-16 15:29   ` Dinh Nguyen
2017-10-23  6:49     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 08/20] arm: socfpga: Add drivers for programing FPGA from flash tien.fong.chee at intel.com
2017-10-16 15:33   ` Dinh Nguyen
2017-10-24  5:52     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 10/20] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-10-13  8:08 ` [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-10-17  3:08   ` Dinh Nguyen
2017-10-23  7:45     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 12/20] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-10-17  3:21   ` Dinh Nguyen
2017-10-13  8:08 ` [U-Boot] [PATCH v3 13/20] arm: socfpga: Enable SPL memory allocation tien.fong.chee at intel.com
2017-10-17  3:44   ` Dinh Nguyen
2017-10-13  8:08 ` [U-Boot] [PATCH v3 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header tien.fong.chee at intel.com
2017-10-20 14:18   ` Dinh Nguyen
2017-10-13  8:08 ` [U-Boot] [PATCH v3 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-10-20 14:19   ` Dinh Nguyen
2017-10-13  8:08 ` [U-Boot] [PATCH v3 16/20] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-10-20 14:29   ` Dinh Nguyen
2017-10-23  8:02     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-10-20 14:33   ` Dinh Nguyen
2017-10-23  8:13     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 18/20] arm: socfpga: Enable function visible to other file tien.fong.chee at intel.com
2017-10-20 14:39   ` Dinh Nguyen
2017-10-23  8:19     ` Chee, Tien Fong
2017-10-23 14:24       ` Dinh Nguyen
2017-10-24  5:11         ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working tien.fong.chee at intel.com
2017-10-20 15:11   ` Dinh Nguyen
2017-10-24  5:34     ` Chee, Tien Fong
2017-10-13  8:08 ` [U-Boot] [PATCH v3 20/20] arm: socfpga: Enable SPL booting U-boot tien.fong.chee at intel.com
2017-10-20 15:21   ` Dinh Nguyen
2017-10-24  5:37     ` Chee, Tien Fong

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