From: Lukasz Majewski <lukma@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system
Date: Sat, 28 Oct 2017 23:43:50 +0200 [thread overview]
Message-ID: <20171028234350.4560ad94@jawa> (raw)
In-Reply-To: <dd090c0e-ad76-e9e6-fbe4-6c47b4bdd0bc@denx.de>
Hi Marek,
> On 10/27/2017 12:35 PM, Lukasz Majewski wrote:
> [...]
> >>>>>>> common/Makefile | 2 +
> >>>>>>> common/load_fs.c | 163
> >>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >>>>>>> include/load_fs.h | 40 ++++++++++++++
> >>>>>>> 3 files changed, 205 insertions(+)
> >>>>>>> create mode 100644 common/load_fs.c
> >>>>>>> create mode 100644 include/load_fs.h
> >>>>>> There is alot of change here and the commit message doesn't
> >>>>>> tell
> >>>>>> me anything! Please describe, in detail, what your patch is
> >>>>>> doing.
> >>>>>>
> >>>>>> Also you need to include more people in the review path for
> >>>>>> this
> >>>>>> patch.
> >>>> These are the code factored out from splash loader, contains some
> >>>> common functions which can be used by other file system loader
> >>>> such as
> >>>> fpga loadfs.
> >>> Would it be possible to provide ./doc entry to explain how one can
> >>> use
> >>> this set of tools (splash/loadfs loaders) ?
> >>>
> >> Sure. I will provide a./doc or comment in next version. Basically,
> >> the idea is factoring out the common code which specific handlle
> >> image in file format loading from flash to target(memory/device)
> >> between splash loader and fpga loadfs. So, you will see i have
> >> declared a few weak functions, which is used for defined speficic
> >> handling algorithm such as get_file, and fs_loading.
> >>
> >> Initially, my plan is creating a more generic function name and
> >> geneirc file name, then replacing those splash_loader fs at
> >> separate patch set.
> >>
> >> Now, i am working directly on splash loader. Anyway, i also like
> >> more discussion and good comments while i am working on it.
> >
> > I've asked for a documentation, since I do have one idea in the
> > back of my head.
> >
> > I'm wondering if other SoCs could benefit from this solution? For
> > example when we treat the FPGA as a DSP processor which needs to
> > have bitstream ( or better firmware ) loaded to some physical
> > address. I'm also wondering if your work would allow for start/stop
> > of the code execution?
>
> This is supposed to be a firmware loader (kind-of like the firmware
> loader in Linux),
So in principle I should be able to load any bitstream (firmware) to
any FPGA/SoC/whatever.
I do have in mind the ADI's SHARC DSP cores...
> so I have no idea what you mean by "start/stop"
> execution.
Ok. This can be done in a separate driver. No issues with that.
>
> > It would be best to have some kind of common code and extensions per
> > soc/architecture.
>
> I can't see a usecase for that.
The use case would be to reuse/tweak this code to be able to load
firmware for the SHARC DSP processors.
>
> > I cannot help much with review/design phase since I know very
> > little on this particular Altera (up.. sorry Intel) solution.[...]
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
next prev parent reply other threads:[~2017-10-28 21:43 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 8:08 [U-Boot] [PATCH v3 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface tien.fong.chee at intel.com
2017-10-16 12:39 ` Dinh Nguyen
2017-10-23 6:46 ` Chee, Tien Fong
2017-10-23 7:04 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 05/20] fs: Enable generic filesystems interface support in SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system tien.fong.chee at intel.com
2017-10-16 14:08 ` Dinh Nguyen
2017-10-16 14:41 ` Marek Vasut
2017-10-23 6:37 ` Chee, Tien Fong
2017-10-26 12:51 ` Lukasz Majewski
2017-10-27 9:23 ` Chee, Tien Fong
2017-10-27 10:35 ` Lukasz Majewski
2017-10-28 11:32 ` Marek Vasut
2017-10-28 21:43 ` Lukasz Majewski [this message]
2017-10-29 9:35 ` Marek Vasut
2017-10-29 22:57 ` Lukasz Majewski
2017-10-29 22:59 ` Marek Vasut
2017-10-13 8:08 ` [U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct polling status bit tien.fong.chee at intel.com
2017-10-16 15:29 ` Dinh Nguyen
2017-10-23 6:49 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 08/20] arm: socfpga: Add drivers for programing FPGA from flash tien.fong.chee at intel.com
2017-10-16 15:33 ` Dinh Nguyen
2017-10-24 5:52 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 10/20] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-10-17 3:08 ` Dinh Nguyen
2017-10-23 7:45 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 12/20] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-10-17 3:21 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 13/20] arm: socfpga: Enable SPL memory allocation tien.fong.chee at intel.com
2017-10-17 3:44 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header tien.fong.chee at intel.com
2017-10-20 14:18 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-10-20 14:19 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 16/20] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-10-20 14:29 ` Dinh Nguyen
2017-10-23 8:02 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-10-20 14:33 ` Dinh Nguyen
2017-10-23 8:13 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 18/20] arm: socfpga: Enable function visible to other file tien.fong.chee at intel.com
2017-10-20 14:39 ` Dinh Nguyen
2017-10-23 8:19 ` Chee, Tien Fong
2017-10-23 14:24 ` Dinh Nguyen
2017-10-24 5:11 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working tien.fong.chee at intel.com
2017-10-20 15:11 ` Dinh Nguyen
2017-10-24 5:34 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 20/20] arm: socfpga: Enable SPL booting U-boot tien.fong.chee at intel.com
2017-10-20 15:21 ` Dinh Nguyen
2017-10-24 5:37 ` Chee, Tien Fong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171028234350.4560ad94@jawa \
--to=lukma@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.