From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode
Date: Mon, 13 Nov 2017 17:36:02 +0100 [thread overview]
Message-ID: <1510590962.3607.1.camel@baylibre.com> (raw)
In-Reply-To: <66991733-9d1a-dbd2-9857-bba1ffca1cf8@gmail.com>
On Sun, 2017-11-12 at 16:16 +0100, Heiner Kallweit wrote:
> After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
> interrupt on some platforms" ethernet stopped working on my Odroid-C2
> which has a RTL8211F phy.
>
> It turned out that no interrupts were triggered. Further analysis
> showed the register INER can't be altered on page 0.
> Because register INSR needs to be accessed via page 0xa43 I assumed
> that register INER needs to be accessed via some page too.
> Some brute force check resulted in page 0xa42 being the right one.
>
> With this patch the phy is working properly in interrupt mode.
>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Heiner Kallweit <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>,
Shengzhou Liu <Shengzhou.Liu@freescale.com>
Subject: Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode
Date: Mon, 13 Nov 2017 17:36:02 +0100 [thread overview]
Message-ID: <1510590962.3607.1.camel@baylibre.com> (raw)
In-Reply-To: <66991733-9d1a-dbd2-9857-bba1ffca1cf8@gmail.com>
On Sun, 2017-11-12 at 16:16 +0100, Heiner Kallweit wrote:
> After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
> interrupt on some platforms" ethernet stopped working on my Odroid-C2
> which has a RTL8211F phy.
>
> It turned out that no interrupts were triggered. Further analysis
> showed the register INER can't be altered on page 0.
> Because register INSR needs to be accessed via page 0xa43 I assumed
> that register INER needs to be accessed via some page too.
> Some brute force check resulted in page 0xa42 being the right one.
>
> With this patch the phy is working properly in interrupt mode.
>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
next prev parent reply other threads:[~2017-11-13 16:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-12 15:16 [PATCH] net: phy: realtek: fix RTL8211F interrupt mode Heiner Kallweit
2017-11-12 15:16 ` Heiner Kallweit
2017-11-12 18:25 ` Andrew Lunn
2017-11-12 18:25 ` Andrew Lunn
2017-11-12 18:36 ` Jerome Brunet
2017-11-12 18:36 ` Jerome Brunet
2017-11-12 20:06 ` Andrew Lunn
2017-11-12 20:06 ` Andrew Lunn
2017-11-12 20:10 ` Jerome Brunet
2017-11-12 20:10 ` Jerome Brunet
2017-11-12 18:29 ` Florian Fainelli
2017-11-12 18:29 ` Florian Fainelli
2017-11-12 18:39 ` Jerome Brunet
2017-11-12 18:39 ` Jerome Brunet
2017-11-13 16:36 ` Jerome Brunet [this message]
2017-11-13 16:36 ` Jerome Brunet
2017-11-14 12:34 ` David Miller
2017-11-14 12:34 ` David Miller
2017-12-02 17:14 ` Martin Blumenstingl
2017-12-02 17:14 ` Martin Blumenstingl
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