* [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linus-amlogic This patch series try to add PWM controller driver for the Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. Jian Hu (3): dt-bindings: pwm: update bindings for the Meson-AXG pwm: meson: add clock source configuratin for Meson-AXG ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC .../devicetree/bindings/pwm/pwm-meson.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++ drivers/pwm/pwm-meson.c | 26 +++++ 3 files changed, 148 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel This patch series try to add PWM controller driver for the Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. Jian Hu (3): dt-bindings: pwm: update bindings for the Meson-AXG pwm: meson: add clock source configuratin for Meson-AXG ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC .../devicetree/bindings/pwm/pwm-meson.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++ drivers/pwm/pwm-meson.c | 26 +++++ 3 files changed, 148 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linux-arm-kernel This patch series try to add PWM controller driver for the Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. Jian Hu (3): dt-bindings: pwm: update bindings for the Meson-AXG pwm: meson: add clock source configuratin for Meson-AXG ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC .../devicetree/bindings/pwm/pwm-meson.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++ drivers/pwm/pwm-meson.c | 26 +++++ 3 files changed, 148 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel This patch series try to add PWM controller driver for the Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. Jian Hu (3): dt-bindings: pwm: update bindings for the Meson-AXG pwm: meson: add clock source configuratin for Meson-AXG ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC .../devicetree/bindings/pwm/pwm-meson.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++ drivers/pwm/pwm-meson.c | 26 +++++ 3 files changed, 148 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG 2017-12-04 6:00 ` Yixun Lan (?) (?) @ 2017-12-04 6:00 ` Yixun Lan -1 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linus-amlogic From: Jian Hu <jian.hu@amlogic.com> Update the doc to explicitly support Meson-AXG Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt index 1ee81321c35e..1fa3f7182133 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt @@ -5,6 +5,8 @@ Required properties: - compatible: Shall contain "amlogic,meson8b-pwm" or "amlogic,meson-gxbb-pwm" or "amlogic,meson-gxbb-ao-pwm" + or "amlogic,meson-axg-ee-pwm" + or "amlogic,meson-axg-ao-pwm" - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel From: Jian Hu <jian.hu@amlogic.com> Update the doc to explicitly support Meson-AXG Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt index 1ee81321c35e..1fa3f7182133 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt @@ -5,6 +5,8 @@ Required properties: - compatible: Shall contain "amlogic,meson8b-pwm" or "amlogic,meson-gxbb-pwm" or "amlogic,meson-gxbb-ao-pwm" + or "amlogic,meson-axg-ee-pwm" + or "amlogic,meson-axg-ao-pwm" - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linux-arm-kernel From: Jian Hu <jian.hu@amlogic.com> Update the doc to explicitly support Meson-AXG Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt index 1ee81321c35e..1fa3f7182133 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt @@ -5,6 +5,8 @@ Required properties: - compatible: Shall contain "amlogic,meson8b-pwm" or "amlogic,meson-gxbb-pwm" or "amlogic,meson-gxbb-ao-pwm" + or "amlogic,meson-axg-ee-pwm" + or "amlogic,meson-axg-ao-pwm" - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Mark Rutland, devicetree, Neil Armstrong, Yixun Lan, linux-kernel, Rob Herring, Jian Hu, Carlo Caione, linux-arm-kernel, Jerome Brunet From: Jian Hu <jian.hu@amlogic.com> Update the doc to explicitly support Meson-AXG Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt index 1ee81321c35e..1fa3f7182133 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt @@ -5,6 +5,8 @@ Required properties: - compatible: Shall contain "amlogic,meson8b-pwm" or "amlogic,meson-gxbb-pwm" or "amlogic,meson-gxbb-ao-pwm" + or "amlogic,meson-axg-ee-pwm" + or "amlogic,meson-axg-ao-pwm" - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG 2017-12-04 6:00 ` Yixun Lan (?) @ 2017-12-04 22:39 ` Rob Herring -1 siblings, 0 replies; 29+ messages in thread From: Rob Herring @ 2017-12-04 22:39 UTC (permalink / raw) To: linus-amlogic On Mon, Dec 04, 2017 at 02:00:16PM +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Update the doc to explicitly support Meson-AXG > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG @ 2017-12-04 22:39 ` Rob Herring 0 siblings, 0 replies; 29+ messages in thread From: Rob Herring @ 2017-12-04 22:39 UTC (permalink / raw) To: linux-arm-kernel On Mon, Dec 04, 2017 at 02:00:16PM +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Update the doc to explicitly support Meson-AXG > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG @ 2017-12-04 22:39 ` Rob Herring 0 siblings, 0 replies; 29+ messages in thread From: Rob Herring @ 2017-12-04 22:39 UTC (permalink / raw) To: Yixun Lan Cc: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, linux-arm-kernel, linux-kernel On Mon, Dec 04, 2017 at 02:00:16PM +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Update the doc to explicitly support Meson-AXG > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > Documentation/devicetree/bindings/pwm/pwm-meson.txt | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG 2017-12-04 6:00 ` Yixun Lan (?) (?) @ 2017-12-04 6:00 ` Yixun Lan -1 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linus-amlogic From: Jian Hu <jian.hu@amlogic.com> For PWM controller in the Meson-AXG SoC, the EE domain and AO domain have different clock source. This patch try to describe them in the DT compatible data. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 1f44b288af57..dcacc5c6ac1e 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -421,6 +421,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "aoclk81", "xtal", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -434,6 +452,14 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-gxbb-ao-pwm", .data = &pwm_gxbb_ao_data }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel From: Jian Hu <jian.hu@amlogic.com> For PWM controller in the Meson-AXG SoC, the EE domain and AO domain have different clock source. This patch try to describe them in the DT compatible data. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 1f44b288af57..dcacc5c6ac1e 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -421,6 +421,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "aoclk81", "xtal", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -434,6 +452,14 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-gxbb-ao-pwm", .data = &pwm_gxbb_ao_data }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linux-arm-kernel From: Jian Hu <jian.hu@amlogic.com> For PWM controller in the Meson-AXG SoC, the EE domain and AO domain have different clock source. This patch try to describe them in the DT compatible data. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 1f44b288af57..dcacc5c6ac1e 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -421,6 +421,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "aoclk81", "xtal", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -434,6 +452,14 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-gxbb-ao-pwm", .data = &pwm_gxbb_ao_data }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel From: Jian Hu <jian.hu@amlogic.com> For PWM controller in the Meson-AXG SoC, the EE domain and AO domain have different clock source. This patch try to describe them in the DT compatible data. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 1f44b288af57..dcacc5c6ac1e 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -421,6 +421,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "aoclk81", "xtal", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -434,6 +452,14 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-gxbb-ao-pwm", .data = &pwm_gxbb_ao_data }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linus-amlogic From: Jian Hu <jian.hu@amlogic.com> Add PWM DT info for the Amlogic's Meson-Axg SoC. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 92f65eec3e18..f7f228701df1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -177,6 +177,24 @@ clock-names = "clk_i2c"; }; + pwm_ab: pwm at 1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm at 1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_A: serial at 24000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x24000 0x0 0x14>; @@ -368,6 +386,90 @@ function = "i2c3"; }; }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; }; }; @@ -435,6 +537,24 @@ clock-names = "clk_i2c"; }; + pwm_AO_ab: pwm at 7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_AO_cd: pwm at 2000 { + compatible = "amlogic,axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_AO: serial at 3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel, linux-kernel From: Jian Hu <jian.hu@amlogic.com> Add PWM DT info for the Amlogic's Meson-Axg SoC. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 92f65eec3e18..f7f228701df1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -177,6 +177,24 @@ clock-names = "clk_i2c"; }; + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_A: serial@24000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x24000 0x0 0x14>; @@ -368,6 +386,90 @@ function = "i2c3"; }; }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; }; }; @@ -435,6 +537,24 @@ clock-names = "clk_i2c"; }; + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_AO: serial@3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: linux-arm-kernel From: Jian Hu <jian.hu@amlogic.com> Add PWM DT info for the Amlogic's Meson-Axg SoC. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 92f65eec3e18..f7f228701df1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -177,6 +177,24 @@ clock-names = "clk_i2c"; }; + pwm_ab: pwm at 1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm at 1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_A: serial at 24000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x24000 0x0 0x14>; @@ -368,6 +386,90 @@ function = "i2c3"; }; }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; }; }; @@ -435,6 +537,24 @@ clock-names = "clk_i2c"; }; + pwm_AO_ab: pwm at 7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_AO_cd: pwm at 2000 { + compatible = "amlogic,axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_AO: serial at 3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; -- 2.15.0 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 6:00 ` Yixun Lan 0 siblings, 0 replies; 29+ messages in thread From: Yixun Lan @ 2017-12-04 6:00 UTC (permalink / raw) To: Thierry Reding, Kevin Hilman, linux-pwm-u79uwXL29TY76Z2rM5mHXA, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, Yixun Lan, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA From: Jian Hu <jian.hu-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> Add PWM DT info for the Amlogic's Meson-Axg SoC. Signed-off-by: Jian Hu <jian.hu-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 92f65eec3e18..f7f228701df1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -177,6 +177,24 @@ clock-names = "clk_i2c"; }; + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_A: serial@24000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x24000 0x0 0x14>; @@ -368,6 +386,90 @@ function = "i2c3"; }; }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; }; }; @@ -435,6 +537,24 @@ clock-names = "clk_i2c"; }; + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_AO: serial@3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC 2017-12-04 6:00 ` Yixun Lan (?) @ 2017-12-04 9:17 ` Jerome Brunet -1 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:17 UTC (permalink / raw) To: linus-amlogic On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > +++++++++++++++++++++++++++++ > 1 file changed, 120 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index 92f65eec3e18..f7f228701df1 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -177,6 +177,24 @@ > [...] > > @@ -435,6 +537,24 @@ > clock-names = "clk_i2c"; > }; > > + pwm_AO_ab: pwm at 7000 { > + compatible = "amlogic,meson-axg-ao-pwm"; > + reg = <0x0 0x07000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, Later on, if we want to "correctly" get the clock from DT, it will have to gothrough a new compatible, I guess. > + status = "disabled"; > + }; > + > + pwm_AO_cd: pwm at 2000 { > + compatible = "amlogic,axg-ao-pwm"; > + reg = <0x0 0x02000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; > + status = "disabled"; > + }; > + > uart_AO: serial at 3000 { > compatible = "amlogic,meson-gx-uart", > "amlogic,meson-ao-uart"; > reg = <0x0 0x3000 0x0 0x18>; ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:17 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:17 UTC (permalink / raw) To: linux-arm-kernel On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > +++++++++++++++++++++++++++++ > 1 file changed, 120 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index 92f65eec3e18..f7f228701df1 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -177,6 +177,24 @@ > [...] > > @@ -435,6 +537,24 @@ > clock-names = "clk_i2c"; > }; > > + pwm_AO_ab: pwm at 7000 { > + compatible = "amlogic,meson-axg-ao-pwm"; > + reg = <0x0 0x07000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, Later on, if we want to "correctly" get the clock from DT, it will have to gothrough a new compatible, I guess. > + status = "disabled"; > + }; > + > + pwm_AO_cd: pwm at 2000 { > + compatible = "amlogic,axg-ao-pwm"; > + reg = <0x0 0x02000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; > + status = "disabled"; > + }; > + > uart_AO: serial at 3000 { > compatible = "amlogic,meson-gx-uart", > "amlogic,meson-ao-uart"; > reg = <0x0 0x3000 0x0 0x18>; ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:17 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:17 UTC (permalink / raw) To: Yixun Lan, Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Mark Rutland, Carlo Caione, Jian Hu, linux-arm-kernel, linux-kernel On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > From: Jian Hu <jian.hu@amlogic.com> > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > +++++++++++++++++++++++++++++ > 1 file changed, 120 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index 92f65eec3e18..f7f228701df1 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -177,6 +177,24 @@ > [...] > > @@ -435,6 +537,24 @@ > clock-names = "clk_i2c"; > }; > > + pwm_AO_ab: pwm@7000 { > + compatible = "amlogic,meson-axg-ao-pwm"; > + reg = <0x0 0x07000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, Later on, if we want to "correctly" get the clock from DT, it will have to gothrough a new compatible, I guess. > + status = "disabled"; > + }; > + > + pwm_AO_cd: pwm@2000 { > + compatible = "amlogic,axg-ao-pwm"; > + reg = <0x0 0x02000 0x0 0x20>; > + #pwm-cells = <3>; > + clocks = <&xtal>, <&xtal>; > + clock-names = "clkin0", "clkin1"; > + status = "disabled"; > + }; > + > uart_AO: serial@3000 { > compatible = "amlogic,meson-gx-uart", > "amlogic,meson-ao-uart"; > reg = <0x0 0x3000 0x0 0x18>; ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:29 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:29 UTC (permalink / raw) To: linus-amlogic On Mon, 2017-12-04 at 10:17 +0100, Jerome Brunet wrote: > On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > > From: Jian Hu <jian.hu@amlogic.com> > > > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > > --- > > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > > +++++++++++++++++++++++++++++ > > 1 file changed, 120 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > index 92f65eec3e18..f7f228701df1 100644 > > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > @@ -177,6 +177,24 @@ > > > > [...] > > > > > @@ -435,6 +537,24 @@ > > clock-names = "clk_i2c"; > > }; > > > > + pwm_AO_ab: pwm at 7000 { > > + compatible = "amlogic,meson-axg-ao-pwm"; > > + reg = <0x0 0x07000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, > Later on, if we want to "correctly" get the clock from DT, it will have to > gothrough a new compatible, I guess. Please ignore this comment (monday morning...) However clock bindings for this should be defined in the board dts, not the soc one > > > + status = "disabled"; > > + }; > > + > > + pwm_AO_cd: pwm at 2000 { > > + compatible = "amlogic,axg-ao-pwm"; > > + reg = <0x0 0x02000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > + status = "disabled"; > > + }; > > + > > uart_AO: serial at 3000 { > > compatible = "amlogic,meson-gx-uart", > > "amlogic,meson-ao-uart"; > > reg = <0x0 0x3000 0x0 0x18>; > > ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:29 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:29 UTC (permalink / raw) To: Yixun Lan, Thierry Reding, Kevin Hilman, linux-pwm, linux-amlogic Cc: Rob Herring, devicetree, Neil Armstrong, Mark Rutland, Carlo Caione, Jian Hu, linux-arm-kernel, linux-kernel On Mon, 2017-12-04 at 10:17 +0100, Jerome Brunet wrote: > On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > > From: Jian Hu <jian.hu@amlogic.com> > > > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > > --- > > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > > +++++++++++++++++++++++++++++ > > 1 file changed, 120 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > index 92f65eec3e18..f7f228701df1 100644 > > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > @@ -177,6 +177,24 @@ > > > > [...] > > > > > @@ -435,6 +537,24 @@ > > clock-names = "clk_i2c"; > > }; > > > > + pwm_AO_ab: pwm@7000 { > > + compatible = "amlogic,meson-axg-ao-pwm"; > > + reg = <0x0 0x07000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, > Later on, if we want to "correctly" get the clock from DT, it will have to > gothrough a new compatible, I guess. Please ignore this comment (monday morning...) However clock bindings for this should be defined in the board dts, not the soc one > > > + status = "disabled"; > > + }; > > + > > + pwm_AO_cd: pwm@2000 { > > + compatible = "amlogic,axg-ao-pwm"; > > + reg = <0x0 0x02000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > + status = "disabled"; > > + }; > > + > > uart_AO: serial@3000 { > > compatible = "amlogic,meson-gx-uart", > > "amlogic,meson-ao-uart"; > > reg = <0x0 0x3000 0x0 0x18>; > > ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:29 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:29 UTC (permalink / raw) To: linux-arm-kernel On Mon, 2017-12-04 at 10:17 +0100, Jerome Brunet wrote: > On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > > From: Jian Hu <jian.hu@amlogic.com> > > > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > > --- > > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > > +++++++++++++++++++++++++++++ > > 1 file changed, 120 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > index 92f65eec3e18..f7f228701df1 100644 > > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > @@ -177,6 +177,24 @@ > > > > [...] > > > > > @@ -435,6 +537,24 @@ > > clock-names = "clk_i2c"; > > }; > > > > + pwm_AO_ab: pwm at 7000 { > > + compatible = "amlogic,meson-axg-ao-pwm"; > > + reg = <0x0 0x07000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, > Later on, if we want to "correctly" get the clock from DT, it will have to > gothrough a new compatible, I guess. Please ignore this comment (monday morning...) However clock bindings for this should be defined in the board dts, not the soc one > > > + status = "disabled"; > > + }; > > + > > + pwm_AO_cd: pwm at 2000 { > > + compatible = "amlogic,axg-ao-pwm"; > > + reg = <0x0 0x02000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > + status = "disabled"; > > + }; > > + > > uart_AO: serial at 3000 { > > compatible = "amlogic,meson-gx-uart", > > "amlogic,meson-ao-uart"; > > reg = <0x0 0x3000 0x0 0x18>; > > ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC @ 2017-12-04 9:29 ` Jerome Brunet 0 siblings, 0 replies; 29+ messages in thread From: Jerome Brunet @ 2017-12-04 9:29 UTC (permalink / raw) To: Yixun Lan, Thierry Reding, Kevin Hilman, linux-pwm-u79uwXL29TY76Z2rM5mHXA, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA, Neil Armstrong, Mark Rutland, Carlo Caione, Jian Hu, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Mon, 2017-12-04 at 10:17 +0100, Jerome Brunet wrote: > On Mon, 2017-12-04 at 14:00 +0800, Yixun Lan wrote: > > From: Jian Hu <jian.hu-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> > > > > Add PWM DT info for the Amlogic's Meson-Axg SoC. > > > > Signed-off-by: Jian Hu <jian.hu-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> > > Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> > > --- > > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 > > +++++++++++++++++++++++++++++ > > 1 file changed, 120 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > index 92f65eec3e18..f7f228701df1 100644 > > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > > @@ -177,6 +177,24 @@ > > > > [...] > > > > > @@ -435,6 +537,24 @@ > > clock-names = "clk_i2c"; > > }; > > > > + pwm_AO_ab: pwm@7000 { > > + compatible = "amlogic,meson-axg-ao-pwm"; > > + reg = <0x0 0x07000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > like gxbb, "amlogic,meson-axg-ao-pwm" does not have such clock bindings, > Later on, if we want to "correctly" get the clock from DT, it will have to > gothrough a new compatible, I guess. Please ignore this comment (monday morning...) However clock bindings for this should be defined in the board dts, not the soc one > > > + status = "disabled"; > > + }; > > + > > + pwm_AO_cd: pwm@2000 { > > + compatible = "amlogic,axg-ao-pwm"; > > + reg = <0x0 0x02000 0x0 0x20>; > > + #pwm-cells = <3>; > > + clocks = <&xtal>, <&xtal>; > > + clock-names = "clkin0", "clkin1"; > > + status = "disabled"; > > + }; > > + > > uart_AO: serial@3000 { > > compatible = "amlogic,meson-gx-uart", > > "amlogic,meson-ao-uart"; > > reg = <0x0 0x3000 0x0 0x18>; > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 0/3] pwm: meson-axg: add pwm controller driver 2017-12-04 6:00 ` Yixun Lan (?) @ 2017-12-05 8:52 ` Thierry Reding -1 siblings, 0 replies; 29+ messages in thread From: Thierry Reding @ 2017-12-05 8:52 UTC (permalink / raw) To: linus-amlogic On Mon, Dec 04, 2017 at 02:00:15PM +0800, Yixun Lan wrote: > This patch series try to add PWM controller driver for the > Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. > > Jian Hu (3): > dt-bindings: pwm: update bindings for the Meson-AXG > pwm: meson: add clock source configuratin for Meson-AXG Applied both of these, thanks. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-amlogic/attachments/20171205/79d728d5/attachment.sig> ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-05 8:52 ` Thierry Reding 0 siblings, 0 replies; 29+ messages in thread From: Thierry Reding @ 2017-12-05 8:52 UTC (permalink / raw) To: linux-arm-kernel On Mon, Dec 04, 2017 at 02:00:15PM +0800, Yixun Lan wrote: > This patch series try to add PWM controller driver for the > Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. > > Jian Hu (3): > dt-bindings: pwm: update bindings for the Meson-AXG > pwm: meson: add clock source configuratin for Meson-AXG Applied both of these, thanks. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20171205/79d728d5/attachment.sig> ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 0/3] pwm: meson-axg: add pwm controller driver @ 2017-12-05 8:52 ` Thierry Reding 0 siblings, 0 replies; 29+ messages in thread From: Thierry Reding @ 2017-12-05 8:52 UTC (permalink / raw) To: Yixun Lan Cc: Kevin Hilman, linux-pwm, linux-amlogic, Rob Herring, devicetree, Neil Armstrong, Jerome Brunet, Mark Rutland, Carlo Caione, Jian Hu, linux-arm-kernel, linux-kernel [-- Attachment #1: Type: text/plain, Size: 368 bytes --] On Mon, Dec 04, 2017 at 02:00:15PM +0800, Yixun Lan wrote: > This patch series try to add PWM controller driver for the > Amlogic's Meson-AXG SoC. Update the Clock sources, pin DT. > > Jian Hu (3): > dt-bindings: pwm: update bindings for the Meson-AXG > pwm: meson: add clock source configuratin for Meson-AXG Applied both of these, thanks. Thierry [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2017-12-05 8:52 UTC | newest] Thread overview: 29+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-12-04 6:00 [PATCH 0/3] pwm: meson-axg: add pwm controller driver Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` [PATCH 1/3] dt-bindings: pwm: update bindings for the Meson-AXG Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 22:39 ` Rob Herring 2017-12-04 22:39 ` Rob Herring 2017-12-04 22:39 ` Rob Herring 2017-12-04 6:00 ` [PATCH 2/3] pwm: meson: add clock source configuratin for Meson-AXG Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 6:00 ` Yixun Lan 2017-12-04 9:17 ` Jerome Brunet 2017-12-04 9:17 ` Jerome Brunet 2017-12-04 9:17 ` Jerome Brunet 2017-12-04 9:29 ` Jerome Brunet 2017-12-04 9:29 ` Jerome Brunet 2017-12-04 9:29 ` Jerome Brunet 2017-12-04 9:29 ` Jerome Brunet 2017-12-05 8:52 ` [PATCH 0/3] pwm: meson-axg: add pwm controller driver Thierry Reding 2017-12-05 8:52 ` Thierry Reding 2017-12-05 8:52 ` Thierry Reding
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