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-NTdsZG5yRldlUzU3UmhmYw0KPiA+IE1odW45Mm9VMCZlPQ0KPiANCj4gV2h5IGNhbid0IHdlIHVz -ZSBhc3NpZ25lZC1jbG9jay1yYXRlcz8gVGhhdCB3b3VsZCBiYXNpY2FsbHkgY2FsbA0KPiBjbGtf -c2V0X3JhdGUoKSBvbiB0aGUgY2xrIG9uY2UgaXQncyBhZGRlZC4NCg0KVGhhbmtzIGZvciB0aGUg -aGludCwgYXNzaWduZWQtY2xvY2stcmF0ZXMgd29ya3MgZm9yIHVzLg0KDQotLSANCsKgRXVnZW5p -eSBQYWx0c2V2 +On Tue, 2017-11-14@15:46 -0800, sboyd@codeaurora.org wrote: +> On 11/14, Alexey Brodkin wrote: +> > Hi Vladimir, +> > +> > On Tue, 2017-11-14@19:01 +0200, Vladimir Zapolskiy wrote: +> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote: +> > > > +> > > > Add option to set initial output frequency of plls via +> > > > "clock-frequency" property in pll's device tree node. +> > > > This frequency will be set while pll driver probed. +> > > > +> > > > The usage example is setting CPU clock frequency on boot +> > > > See discussion: +> > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c= +> > > > DPL6 +> > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29k +> > > > VMLW +> > > > chYfhSGT2M&e= +> > > > +> > > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > > > --- +> > > > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++ +> > > > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++ +> > > > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++-- +> > > > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++-- +> > > > ?4 files changed, 74 insertions(+), 4 deletions(-) +> > > > +> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > index c56c755..5703059 100644 +> > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > @@ -13,6 +13,10 @@ Required properties: +> > > > ?- clocks: shall be the input parent clock phandle for the PLL. +> > > > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > > > ? +> > > > +Optional properties: +> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > > > +while probing. Should be a single cell. +> > > > + +> > > > ?Example: +> > > > ? input_clk: input-clk { +> > > > ? clock-frequency = <33333333>; +> > > > @@ -25,4 +29,5 @@ Example: +> > > > ? reg = <0x00 0x10>; +> > > > ? #clock-cells = <0>; +> > > > ? clocks = <&input_clk>; +> > > > + clock-frequency = <1000000000>; +> > > > ? }; +> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > index 11fe487..5908f99 100644 +> > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> > > > ?- clocks: shall be the input parent clock phandle for the PLL. +> > > > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > > > ? +> > > > +Optional properties: +> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > > > +while probing. Should be a single cell. +> > > > + +> > > > ?Example: +> > > > ? input-clk: input-clk { +> > > > ? clock-frequency = <33333333>; +> > > > @@ -25,4 +29,5 @@ Example: +> > > > ? reg = <0x80 0x10>, <0x100 0x10>; +> > > > ? #clock-cells = <0>; +> > > > ? clocks = <&input-clk>; +> > > > + clock-frequency = <100000000>; +> > > > ? }; +> > > +> > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt +> > > about how to assign initial clock rates, in general 'clock-frequency' +> > > property is a property of clock consumers with two exceptions of simple +> > > clock sources, namely it is used in fixed clock and PWM clock bindings. +> > +> > I think that's what we agreed on with Rob Herring back in the day. +> > Have you checked this post of him on the topic? +> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002909.html&d=DwIDAw&c=DPL6_ +> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=yGJfHbjH2T75YeIJLB14_iDjfsKi1E5aaX +> > Yu3QJBUIk&e= +> > +> > Just FYI it all started from my question here: +> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002900.html&d=DwIDAw&c=DPL6_ +> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=Jkzt2G_J4aE9JfePPQ57ldnrFWeS57Rhfc +> > Mhun92oU0&e= +> +> Why can't we use assigned-clock-rates? That would basically call +> clk_set_rate() on the clk once it's added. + +Thanks for the hint, assigned-clock-rates works for us. + +-- +?Eugeniy Paltsev diff --git a/a/content_digest b/N1/content_digest index b9927a4..a5d8551 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,107 +2,104 @@ "ref\01b07abf9-c94d-1759-4182-519b77c8bb37@mentor.com\0" "ref\01510694373.15407.1.camel@synopsys.com\0" "ref\020171114234643.GD11955@codeaurora.org\0" - "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" - "Subject\0Re: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" + "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" + "Subject\0[PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" "Date\0Sat, 9 Dec 2017 13:50:49 +0000\0" - "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>" - " Alexey.Brodkin@synopsys.com <Alexey.Brodkin@synopsys.com>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - robh+dt@kernel.org <robh+dt@kernel.org> - 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"aGludCwgYXNzaWduZWQtY2xvY2stcmF0ZXMgd29ya3MgZm9yIHVzLg0KDQotLSANCsKgRXVnZW5p\n" - eSBQYWx0c2V2 + "On Tue, 2017-11-14@15:46 -0800, sboyd@codeaurora.org wrote:\n" + "> On 11/14, Alexey Brodkin wrote:\n" + "> > Hi Vladimir,\n" + "> > \n" + "> > On Tue, 2017-11-14@19:01 +0200, Vladimir Zapolskiy wrote:\n" + "> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:\n" + "> > > > \n" + "> > > > Add option to set initial output frequency of plls via\n" + "> > > > \"clock-frequency\" property in pll's device tree node.\n" + "> > > > This frequency will be set while pll driver probed.\n" + "> > > > \n" + "> > > > The usage example is setting CPU clock frequency on boot\n" + "> > > > See discussion:\n" + "> > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=\n" + "> > > > DPL6\n" + "> > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29k\n" + "> > > > VMLW\n" + "> > > > chYfhSGT2M&e=\n" + "> > > > \n" + "> > > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > > > ---\n" + "> > > > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++\n" + "> > > > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++\n" + "> > > > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++--\n" + "> > > > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++--\n" + "> > > > ?4 files changed, 74 insertions(+), 4 deletions(-)\n" + "> > > > \n" + "> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > index c56c755..5703059 100644\n" + "> > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > @@ -13,6 +13,10 @@ Required properties:\n" + "> > > > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > > ?\n" + "> > > > +Optional properties:\n" + "> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > > > +while probing. Should be a single cell.\n" + "> > > > +\n" + "> > > > ?Example:\n" + "> > > > ?\tinput_clk: input-clk {\n" + "> > > > ?\t\tclock-frequency = <33333333>;\n" + "> > > > @@ -25,4 +29,5 @@ Example:\n" + "> > > > ?\t\treg = <0x00 0x10>;\n" + "> > > > ?\t\t#clock-cells = <0>;\n" + "> > > > ?\t\tclocks = <&input_clk>;\n" + "> > > > +\t\tclock-frequency = <1000000000>;\n" + "> > > > ?\t};\n" + "> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > index 11fe487..5908f99 100644\n" + "> > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> > > > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > > ?\n" + "> > > > +Optional properties:\n" + "> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > > > +while probing. Should be a single cell.\n" + "> > > > +\n" + "> > > > ?Example:\n" + "> > > > ?\tinput-clk: input-clk {\n" + "> > > > ?\t\tclock-frequency = <33333333>;\n" + "> > > > @@ -25,4 +29,5 @@ Example:\n" + "> > > > ?\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> > > > ?\t\t#clock-cells = <0>;\n" + "> > > > ?\t\tclocks = <&input-clk>;\n" + "> > > > +\t\tclock-frequency = <100000000>;\n" + "> > > > ?\t};\n" + "> > > \n" + "> > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt\n" + "> > > about how to assign initial clock rates, in general 'clock-frequency'\n" + "> > > property is a property of clock consumers with two exceptions of simple\n" + "> > > clock sources, namely it is used in fixed clock and PWM clock bindings.\n" + "> > \n" + "> > I think that's what we agreed on with Rob Herring back in the day.\n" + "> > Have you checked this post of him on the topic?\n" + "> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002909.html&d=DwIDAw&c=DPL6_\n" + "> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=yGJfHbjH2T75YeIJLB14_iDjfsKi1E5aaX\n" + "> > Yu3QJBUIk&e=\n" + "> > \n" + "> > Just FYI it all started from my question here:\n" + "> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002900.html&d=DwIDAw&c=DPL6_\n" + "> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=Jkzt2G_J4aE9JfePPQ57ldnrFWeS57Rhfc\n" + "> > Mhun92oU0&e=\n" + "> \n" + "> Why can't we use assigned-clock-rates? That would basically call\n" + "> clk_set_rate() on the clk once it's added.\n" + "\n" + "Thanks for the hint, assigned-clock-rates works for us.\n" + "\n" + "-- \n" + ?Eugeniy Paltsev -8f6b6d907f0f1d50f8fea9b8496d5d22edecac2016a504402766cd3a34545b2d +1be104d30436dac415b89a905a5dcd80965e8c52125b40771facd748838925da
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-ZSBhc3NpZ25lZC1jbG9jay1yYXRlcz8gVGhhdCB3b3VsZCBiYXNpY2FsbHkgY2FsbA0KPiBjbGtf -c2V0X3JhdGUoKSBvbiB0aGUgY2xrIG9uY2UgaXQncyBhZGRlZC4NCg0KVGhhbmtzIGZvciB0aGUg -aGludCwgYXNzaWduZWQtY2xvY2stcmF0ZXMgd29ya3MgZm9yIHVzLg0KDQotLSANCsKgRXVnZW5p -eSBQYWx0c2V2 +On Tue, 2017-11-14 at 15:46 -0800, sboyd@codeaurora.org wrote: +> On 11/14, Alexey Brodkin wrote: +> > Hi Vladimir, +> > +> > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote: +> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote: +> > > > +> > > > Add option to set initial output frequency of plls via +> > > > "clock-frequency" property in pll's device tree node. +> > > > This frequency will be set while pll driver probed. +> > > > +> > > > The usage example is setting CPU clock frequency on boot +> > > > See discussion: +> > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c= +> > > > DPL6 +> > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29k +> > > > VMLW +> > > > chYfhSGT2M&e= +> > > > +> > > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> +> > > > --- +> > > > .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ +> > > > .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ +> > > > drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- +> > > > drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- +> > > > 4 files changed, 74 insertions(+), 4 deletions(-) +> > > > +> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > index c56c755..5703059 100644 +> > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > > > @@ -13,6 +13,10 @@ Required properties: +> > > > - clocks: shall be the input parent clock phandle for the PLL. +> > > > - #clock-cells: from common clock binding; Should always be set to 0. +> > > > +> > > > +Optional properties: +> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > > > +while probing. Should be a single cell. +> > > > + +> > > > Example: +> > > > input_clk: input-clk { +> > > > clock-frequency = <33333333>; +> > > > @@ -25,4 +29,5 @@ Example: +> > > > reg = <0x00 0x10>; +> > > > #clock-cells = <0>; +> > > > clocks = <&input_clk>; +> > > > + clock-frequency = <1000000000>; +> > > > }; +> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > index 11fe487..5908f99 100644 +> > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> > > > - clocks: shall be the input parent clock phandle for the PLL. +> > > > - #clock-cells: from common clock binding; Should always be set to 0. +> > > > +> > > > +Optional properties: +> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > > > +while probing. Should be a single cell. +> > > > + +> > > > Example: +> > > > input-clk: input-clk { +> > > > clock-frequency = <33333333>; +> > > > @@ -25,4 +29,5 @@ Example: +> > > > reg = <0x80 0x10>, <0x100 0x10>; +> > > > #clock-cells = <0>; +> > > > clocks = <&input-clk>; +> > > > + clock-frequency = <100000000>; +> > > > }; +> > > +> > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt +> > > about how to assign initial clock rates, in general 'clock-frequency' +> > > property is a property of clock consumers with two exceptions of simple +> > > clock sources, namely it is used in fixed clock and PWM clock bindings. +> > +> > I think that's what we agreed on with Rob Herring back in the day. +> > Have you checked this post of him on the topic? +> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002909.html&d=DwIDAw&c=DPL6_ +> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=yGJfHbjH2T75YeIJLB14_iDjfsKi1E5aaX +> > Yu3QJBUIk&e= +> > +> > Just FYI it all started from my question here: +> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002900.html&d=DwIDAw&c=DPL6_ +> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=Jkzt2G_J4aE9JfePPQ57ldnrFWeS57Rhfc +> > Mhun92oU0&e= +> +> Why can't we use assigned-clock-rates? That would basically call +> clk_set_rate() on the clk once it's added. + +Thanks for the hint, assigned-clock-rates works for us. + +-- + Eugeniy Paltsev diff --git a/a/content_digest b/N2/content_digest index b9927a4..da84cf1 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -17,92 +17,98 @@ " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" "\00:1\0" "b\0" - "T24gVHVlLCAyMDE3LTExLTE0IGF0IDE1OjQ2IC0wODAwLCBzYm95ZEBjb2RlYXVyb3JhLm9yZyB3\n" - "cm90ZToNCj4gT24gMTEvMTQsIEFsZXhleSBCcm9ka2luIHdyb3RlOg0KPiA+IEhpIFZsYWRpbWly\n" - "LA0KPiA+IA0KPiA+IE9uIFR1ZSwgMjAxNy0xMS0xNCBhdCAxOTowMSArMDIwMCwgVmxhZGltaXIg\n" - "WmFwb2xza2l5IHdyb3RlOg0KPiA+ID4gT24gMTEvMTQvMjAxNyAwMjoyMCBQTSwgRXVnZW5peSBQ\n" - "YWx0c2V2IHdyb3RlOg0KPiA+ID4gPiANCj4gPiA+ID4gQWRkIG9wdGlvbiB0byBzZXQgaW5pdGlh\n" - "bCBvdXRwdXQgZnJlcXVlbmN5IG9mIHBsbHMgdmlhDQo+ID4gPiA+ICJjbG9jay1mcmVxdWVuY3ki\n" - "IHByb3BlcnR5IGluIHBsbCdzIGRldmljZSB0cmVlIG5vZGUuDQo+ID4gPiA+IFRoaXMgZnJlcXVl\n" - "bmN5IHdpbGwgYmUgc2V0IHdoaWxlIHBsbCBkcml2ZXIgcHJvYmVkLg0KPiA+ID4gPiANCj4gPiA+\n" - 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eSBQYWx0c2V2 + "On Tue, 2017-11-14 at 15:46 -0800, sboyd@codeaurora.org wrote:\n" + "> On 11/14, Alexey Brodkin wrote:\n" + "> > Hi Vladimir,\n" + "> > \n" + "> > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:\n" + "> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:\n" + "> > > > \n" + "> > > > Add option to set initial output frequency of plls via\n" + "> > > > \"clock-frequency\" property in pll's device tree node.\n" + "> > > > This frequency will be set while pll driver probed.\n" + "> > > > \n" + "> > > > The usage example is setting CPU clock frequency on boot\n" + "> > > > See discussion:\n" + "> > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=\n" + "> > > > DPL6\n" + "> > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29k\n" + "> > > > VMLW\n" + "> > > > chYfhSGT2M&e=\n" + "> > > > \n" + "> > > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" + "> > > > ---\n" + "> > > > \302\240.../bindings/clock/snps,hsdk-pll-clock.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> > > > \302\240.../devicetree/bindings/clock/snps,pll-clock.txt\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> > > > \302\240drivers/clk/axs10x/pll_clock.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> > > > \302\240drivers/clk/clk-hsdk-pll.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> > > > \302\2404 files changed, 74 insertions(+), 4 deletions(-)\n" + "> > > > \n" + "> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > index c56c755..5703059 100644\n" + "> > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > > > @@ -13,6 +13,10 @@ Required properties:\n" + "> > > > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > > \302\240\n" + "> > > > +Optional properties:\n" + "> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > > > +while probing. Should be a single cell.\n" + "> > > > +\n" + "> > > > \302\240Example:\n" + "> > > > \302\240\tinput_clk: input-clk {\n" + "> > > > \302\240\t\tclock-frequency = <33333333>;\n" + "> > > > @@ -25,4 +29,5 @@ Example:\n" + "> > > > \302\240\t\treg = <0x00 0x10>;\n" + "> > > > \302\240\t\t#clock-cells = <0>;\n" + "> > > > \302\240\t\tclocks = <&input_clk>;\n" + "> > > > +\t\tclock-frequency = <1000000000>;\n" + "> > > > \302\240\t};\n" + "> > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > index 11fe487..5908f99 100644\n" + "> > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> > > > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > > > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > > > \302\240\n" + "> > > > +Optional properties:\n" + "> > > > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > > > +while probing. Should be a single cell.\n" + "> > > > +\n" + "> > > > \302\240Example:\n" + "> > > > \302\240\tinput-clk: input-clk {\n" + "> > > > \302\240\t\tclock-frequency = <33333333>;\n" + "> > > > @@ -25,4 +29,5 @@ Example:\n" + "> > > > \302\240\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> > > > \302\240\t\t#clock-cells = <0>;\n" + "> > > > \302\240\t\tclocks = <&input-clk>;\n" + "> > > > +\t\tclock-frequency = <100000000>;\n" + "> > > > \302\240\t};\n" + "> > > \n" + "> > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt\n" + "> > > about how to assign initial clock rates, in general 'clock-frequency'\n" + "> > > property is a property of clock consumers with two exceptions of simple\n" + "> > > clock sources, namely it is used in fixed clock and PWM clock bindings.\n" + "> > \n" + "> > I think that's what we agreed on with Rob Herring back in the day.\n" + "> > Have you checked this post of him on the topic?\n" + "> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002909.html&d=DwIDAw&c=DPL6_\n" + "> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=yGJfHbjH2T75YeIJLB14_iDjfsKi1E5aaX\n" + "> > Yu3QJBUIk&e=\n" + "> > \n" + "> > Just FYI it all started from my question here:\n" + "> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002900.html&d=DwIDAw&c=DPL6_\n" + "> > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=Jkzt2G_J4aE9JfePPQ57ldnrFWeS57Rhfc\n" + "> > Mhun92oU0&e=\n" + "> \n" + "> Why can't we use assigned-clock-rates? That would basically call\n" + "> clk_set_rate() on the clk once it's added.\n" + "\n" + "Thanks for the hint, assigned-clock-rates works for us.\n" + "\n" + "-- \n" + "\302\240Eugeniy Paltsev" -8f6b6d907f0f1d50f8fea9b8496d5d22edecac2016a504402766cd3a34545b2d +444d48ea7eee20e34f369529119c7c34fea0aee847776a830bd21b09aae7fda8
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