* [PATCH v2 1/4] drm/i915/gvt: refine trace_render_mmio
2017-12-12 2:09 [PATCH v2 0/4] mmio save restore refine in vgpu switch Weinan Li
@ 2017-12-12 2:09 ` Weinan Li
2017-12-12 2:09 ` [PATCH v2 2/4] drm/i915/gvt: optimize for vGPU mmio switch Weinan Li
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Weinan Li @ 2017-12-12 2:09 UTC (permalink / raw)
To: intel-gfx
Refine trace_render_mmio to show the vm id before and after vgpu switch,
tag host id as '0', this patch will be used in the future patch for refine
mocs switch policy.
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++--
drivers/gpu/drm/i915/gvt/trace.h | 15 +++++++++------
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 8a52b56..77d3a0d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -304,7 +304,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
I915_WRITE_FW(mmio->reg, v);
- trace_render_mmio(vgpu->id, "load",
+ trace_render_mmio(0, vgpu->id, "switch",
i915_mmio_reg_offset(mmio->reg),
mmio->value, v);
}
@@ -340,7 +340,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
I915_WRITE_FW(mmio->reg, v);
- trace_render_mmio(vgpu->id, "restore",
+ trace_render_mmio(vgpu->id, 0, "switch",
i915_mmio_reg_offset(mmio->reg),
mmio->value, v);
}
diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h
index 8c15038..7a25115 100644
--- a/drivers/gpu/drm/i915/gvt/trace.h
+++ b/drivers/gpu/drm/i915/gvt/trace.h
@@ -330,13 +330,14 @@
);
TRACE_EVENT(render_mmio,
- TP_PROTO(int id, char *action, unsigned int reg,
+ TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,
unsigned int old_val, unsigned int new_val),
- TP_ARGS(id, action, reg, new_val, old_val),
+ TP_ARGS(old_id, new_id, action, reg, new_val, old_val),
TP_STRUCT__entry(
- __field(int, id)
+ __field(int, old_id)
+ __field(int, new_id)
__array(char, buf, GVT_TEMP_STR_LEN)
__field(unsigned int, reg)
__field(unsigned int, old_val)
@@ -344,15 +345,17 @@
),
TP_fast_assign(
- __entry->id = id;
+ __entry->old_id = old_id;
+ __entry->new_id = new_id;
snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", action);
__entry->reg = reg;
__entry->old_val = old_val;
__entry->new_val = new_val;
),
- TP_printk("VM%u %s reg %x, old %08x new %08x\n",
- __entry->id, __entry->buf, __entry->reg,
+ TP_printk("VM%u -> VM%u %s reg %x, old %08x new %08x\n",
+ __entry->old_id, __entry->new_id,
+ __entry->buf, __entry->reg,
__entry->old_val, __entry->new_val)
);
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/4] drm/i915/gvt: optimize for vGPU mmio switch
2017-12-12 2:09 [PATCH v2 0/4] mmio save restore refine in vgpu switch Weinan Li
2017-12-12 2:09 ` [PATCH v2 1/4] drm/i915/gvt: refine trace_render_mmio Weinan Li
@ 2017-12-12 2:09 ` Weinan Li
2017-12-12 2:09 ` [PATCH v2 3/4] drm/i915/gvt: refine mocs save restore policy Weinan Li
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Weinan Li @ 2017-12-12 2:09 UTC (permalink / raw)
To: intel-gfx
Now mmio switch between vGPUs need to switch to host first then to expected
vGPU, it waste one time mmio save/restore. r/w mmio usually is
time-consuming, and there are so many mocs registers need to save/restore
during vGPU switch. Combine the switch_to_host and switch_to_vgpu can
reduce 1 time mmio save/restore, it will reduce the CPU utilization and
performance while there is multi VMs with heavy work load.
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 196 ++++++++++++++------------------
1 file changed, 85 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 77d3a0d..5ad72fc 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -198,9 +198,10 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}
-static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
+static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
+ int ring_id)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
u32 regs[] = {
[RCS] = 0xc800,
@@ -211,54 +212,44 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
};
int i;
+ dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
return;
offset.reg = regs[ring_id];
- for (i = 0; i < 64; i++) {
- gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
- I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
- offset.reg += 4;
- }
-
- if (ring_id == RCS) {
- l3_offset.reg = 0xb020;
- for (i = 0; i < 32; i++) {
- gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
- I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
- l3_offset.reg += 4;
- }
- }
-}
-static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
-{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
- int i;
+ for (i = 0; i < 64; i++) {
+ if (pre)
+ vgpu_vreg(pre, offset) =
+ I915_READ_FW(offset);
+ else
+ gen9_render_mocs[ring_id][i] =
+ I915_READ_FW(offset);
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
+ if (next)
+ I915_WRITE_FW(offset, vgpu_vreg(next, offset));
+ else
+ I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
- offset.reg = regs[ring_id];
- for (i = 0; i < 64; i++) {
- vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
- I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
offset.reg += 4;
}
if (ring_id == RCS) {
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
- vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
- I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
+ if (pre)
+ vgpu_vreg(pre, l3_offset) =
+ I915_READ_FW(l3_offset);
+ else
+ gen9_render_mocs_L3[i] =
+ I915_READ_FW(l3_offset);
+ if (next)
+ I915_WRITE_FW(l3_offset,
+ vgpu_vreg(next, l3_offset));
+ else
+ I915_WRITE_FW(l3_offset,
+ gen9_render_mocs_L3[i]);
+
l3_offset.reg += 4;
}
}
@@ -266,84 +257,77 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
#define CTX_CONTEXT_CONTROL_VAL 0x03
-/* Switch ring mmio values (context) from host to a vgpu. */
-static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
+/* Switch ring mmio values (context). */
+static void switch_mmio(struct intel_vgpu *pre,
+ struct intel_vgpu *next,
+ int ring_id)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- struct intel_vgpu_submission *s = &vgpu->submission;
- u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
- u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
+ struct drm_i915_private *dev_priv;
+ struct intel_vgpu_submission *s;
+ u32 *reg_state, ctx_ctrl;
u32 inhibit_mask =
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
struct engine_mmio *mmio;
- u32 v;
-
- if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- load_mocs(vgpu, ring_id);
-
- mmio = vgpu->gvt->engine_mmio_list;
- while (i915_mmio_reg_offset((mmio++)->reg)) {
- if (mmio->ring_id != ring_id)
- continue;
-
- mmio->value = I915_READ_FW(mmio->reg);
-
- /*
- * if it is an inhibit context, load in_context mmio
- * into HW by mmio write. If it is not, skip this mmio
- * write.
- */
- if (mmio->in_context &&
- (ctx_ctrl & inhibit_mask) != inhibit_mask)
- continue;
-
- if (mmio->mask)
- v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
- else
- v = vgpu_vreg(vgpu, mmio->reg);
-
- I915_WRITE_FW(mmio->reg, v);
-
- trace_render_mmio(0, vgpu->id, "switch",
- i915_mmio_reg_offset(mmio->reg),
- mmio->value, v);
- }
-
- handle_tlb_pending_event(vgpu, ring_id);
-}
-
-/* Switch ring mmio values (context) from vgpu to host. */
-static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
-{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- struct engine_mmio *mmio;
- u32 v;
+ u32 old_v, new_v;
+ dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- restore_mocs(vgpu, ring_id);
+ switch_mocs(pre, next, ring_id);
- mmio = vgpu->gvt->engine_mmio_list;
+ mmio = dev_priv->gvt->engine_mmio_list;
while (i915_mmio_reg_offset((mmio++)->reg)) {
if (mmio->ring_id != ring_id)
continue;
-
- vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg);
-
- if (mmio->mask) {
- vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
- v = mmio->value | (mmio->mask << 16);
+ // save
+ if (pre) {
+ vgpu_vreg(pre, mmio->reg) = I915_READ_FW(mmio->reg);
+ if (mmio->mask)
+ vgpu_vreg(pre, mmio->reg) &=
+ ~(mmio->mask << 16);
+ old_v = vgpu_vreg(pre, mmio->reg);
} else
- v = mmio->value;
-
- if (mmio->in_context)
- continue;
+ old_v = mmio->value = I915_READ_FW(mmio->reg);
+
+ // restore
+ if (next) {
+ s = &next->submission;
+ reg_state =
+ s->shadow_ctx->engine[ring_id].lrc_reg_state;
+ ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
+ /*
+ * if it is an inhibit context, load in_context mmio
+ * into HW by mmio write. If it is not, skip this mmio
+ * write.
+ */
+ if (mmio->in_context &&
+ (ctx_ctrl & inhibit_mask) != inhibit_mask)
+ continue;
+
+ if (mmio->mask)
+ new_v = vgpu_vreg(next, mmio->reg) |
+ (mmio->mask << 16);
+ else
+ new_v = vgpu_vreg(next, mmio->reg);
+ } else {
+ if (mmio->in_context)
+ continue;
+ if (mmio->mask)
+ new_v = mmio->value | (mmio->mask << 16);
+ else
+ new_v = mmio->value;
+ }
- I915_WRITE_FW(mmio->reg, v);
+ I915_WRITE_FW(mmio->reg, new_v);
- trace_render_mmio(vgpu->id, 0, "switch",
+ trace_render_mmio(pre ? pre->id : 0,
+ next ? next->id : 0,
+ "switch",
i915_mmio_reg_offset(mmio->reg),
- mmio->value, v);
+ old_v, new_v);
}
+
+ if (next)
+ handle_tlb_pending_event(next, ring_id);
}
/**
@@ -374,17 +358,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
* handle forcewake mannually.
*/
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
-
- /**
- * TODO: Optimize for vGPU to vGPU switch by merging
- * switch_mmio_to_host() and switch_mmio_to_vgpu().
- */
- if (pre)
- switch_mmio_to_host(pre, ring_id);
-
- if (next)
- switch_mmio_to_vgpu(next, ring_id);
-
+ switch_mmio(pre, next, ring_id);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/4] drm/i915/gvt: refine mocs save restore policy
2017-12-12 2:09 [PATCH v2 0/4] mmio save restore refine in vgpu switch Weinan Li
2017-12-12 2:09 ` [PATCH v2 1/4] drm/i915/gvt: refine trace_render_mmio Weinan Li
2017-12-12 2:09 ` [PATCH v2 2/4] drm/i915/gvt: optimize for vGPU mmio switch Weinan Li
@ 2017-12-12 2:09 ` Weinan Li
2017-12-12 2:09 ` [PATCH v2 4/4] drm/i915/gvt: load host render mocs once in mocs switch Weinan Li
2017-12-12 10:06 ` [PATCH v2 0/4] mmio save restore refine in vgpu switch Joonas Lahtinen
4 siblings, 0 replies; 6+ messages in thread
From: Weinan Li @ 2017-12-12 2:09 UTC (permalink / raw)
To: intel-gfx
Save and restore the mocs regs of one VM in GVT-g burning too much CPU
utilization. Add LRI command scan to monitor the change of mocs registers,
save the state in vreg, and use delta update policy to restore them.
It can obviously reduce the MMIO r/w count, and improve the performance
of context switch.
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/gvt/mmio_context.c | 33 ++++++++++++++++++---------------
2 files changed, 37 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 18c4573..be5c519b 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
return 0;
}
+static inline bool is_mocs_mmio(unsigned int offset)
+{
+ return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
+ ((offset >= 0xb020) && (offset <= 0xb0a0));
+}
+
+static int mocs_cmd_reg_handler(struct parser_exec_state *s,
+ unsigned int offset, unsigned int index)
+{
+ if (!is_mocs_mmio(offset))
+ return -EINVAL;
+ vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
+ return 0;
+}
+
static int cmd_reg_handler(struct parser_exec_state *s,
unsigned int offset, unsigned int index, char *cmd)
{
@@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
return 0;
}
+ if (is_mocs_mmio(offset) &&
+ mocs_cmd_reg_handler(s, offset, index))
+ return -EINVAL;
+
if (is_force_nonpriv_mmio(offset) &&
force_nonpriv_reg_handler(s, offset, index))
return -EPERM;
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 5ad72fc..06ea3d2 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -203,6 +203,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
{
struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
+ u32 old_v, new_v;
+
u32 regs[] = {
[RCS] = 0xc800,
[VCS] = 0xc900,
@@ -220,16 +222,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
for (i = 0; i < 64; i++) {
if (pre)
- vgpu_vreg(pre, offset) =
- I915_READ_FW(offset);
+ old_v = vgpu_vreg(pre, offset);
else
- gen9_render_mocs[ring_id][i] =
- I915_READ_FW(offset);
-
+ old_v = gen9_render_mocs[ring_id][i]
+ = I915_READ_FW(offset);
if (next)
- I915_WRITE_FW(offset, vgpu_vreg(next, offset));
+ new_v = vgpu_vreg(next, offset);
else
- I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
+ new_v = gen9_render_mocs[ring_id][i];
+
+ if (old_v != new_v)
+ I915_WRITE_FW(offset, new_v);
offset.reg += 4;
}
@@ -238,17 +241,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
if (pre)
- vgpu_vreg(pre, l3_offset) =
- I915_READ_FW(l3_offset);
+ old_v = vgpu_vreg(pre, l3_offset);
else
- gen9_render_mocs_L3[i] =
- I915_READ_FW(l3_offset);
+ old_v = gen9_render_mocs_L3[i]
+ = I915_READ_FW(offset);
if (next)
- I915_WRITE_FW(l3_offset,
- vgpu_vreg(next, l3_offset));
+ new_v = vgpu_vreg(next, l3_offset);
else
- I915_WRITE_FW(l3_offset,
- gen9_render_mocs_L3[i]);
+ new_v = gen9_render_mocs_L3[i];
+
+ if (old_v != new_v)
+ I915_WRITE_FW(l3_offset, new_v);
l3_offset.reg += 4;
}
--
1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 4/4] drm/i915/gvt: load host render mocs once in mocs switch
2017-12-12 2:09 [PATCH v2 0/4] mmio save restore refine in vgpu switch Weinan Li
` (2 preceding siblings ...)
2017-12-12 2:09 ` [PATCH v2 3/4] drm/i915/gvt: refine mocs save restore policy Weinan Li
@ 2017-12-12 2:09 ` Weinan Li
2017-12-12 10:06 ` [PATCH v2 0/4] mmio save restore refine in vgpu switch Joonas Lahtinen
4 siblings, 0 replies; 6+ messages in thread
From: Weinan Li @ 2017-12-12 2:09 UTC (permalink / raw)
To: intel-gfx
Load host render mocs registers once for delta update of mocs switch, it
reduces mmio read times obviously, then brings performance improvement
during multi-vms switch.
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 51 +++++++++++++++++++++++++++------
1 file changed, 42 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 06ea3d2..94ac939 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -149,8 +149,41 @@
{ /* Terminated */ }
};
-static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
-static u32 gen9_render_mocs_L3[32];
+static struct {
+ bool initialized;
+ u32 control_table[I915_NUM_ENGINES][64];
+ u32 l3cc_table[32];
+} gen9_render_mocs;
+
+static void load_render_mocs(struct drm_i915_private *dev_priv)
+{
+ i915_reg_t offset;
+ u32 regs[] = {
+ [RCS] = 0xc800,
+ [VCS] = 0xc900,
+ [VCS2] = 0xca00,
+ [BCS] = 0xcc00,
+ [VECS] = 0xcb00,
+ };
+ int ring_id, i;
+
+ for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
+ offset.reg = regs[ring_id];
+ for (i = 0; i < 64; i++) {
+ gen9_render_mocs.control_table[ring_id][i] =
+ I915_READ_FW(offset);
+ offset.reg += 4;
+ }
+ }
+
+ offset.reg = 0xb020;
+ for (i = 0; i < 32; i++) {
+ gen9_render_mocs.l3cc_table[i] =
+ I915_READ_FW(offset);
+ offset.reg += 4;
+ }
+ gen9_render_mocs.initialized = true;
+}
static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
@@ -218,18 +251,19 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
return;
- offset.reg = regs[ring_id];
+ if (!pre && !gen9_render_mocs.initialized)
+ load_render_mocs(dev_priv);
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
if (pre)
old_v = vgpu_vreg(pre, offset);
else
- old_v = gen9_render_mocs[ring_id][i]
- = I915_READ_FW(offset);
+ old_v = gen9_render_mocs.control_table[ring_id][i];
if (next)
new_v = vgpu_vreg(next, offset);
else
- new_v = gen9_render_mocs[ring_id][i];
+ new_v = gen9_render_mocs.control_table[ring_id][i];
if (old_v != new_v)
I915_WRITE_FW(offset, new_v);
@@ -243,12 +277,11 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
if (pre)
old_v = vgpu_vreg(pre, l3_offset);
else
- old_v = gen9_render_mocs_L3[i]
- = I915_READ_FW(offset);
+ old_v = gen9_render_mocs.l3cc_table[i];
if (next)
new_v = vgpu_vreg(next, l3_offset);
else
- new_v = gen9_render_mocs_L3[i];
+ new_v = gen9_render_mocs.l3cc_table[i];
if (old_v != new_v)
I915_WRITE_FW(l3_offset, new_v);
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/4] mmio save restore refine in vgpu switch
2017-12-12 2:09 [PATCH v2 0/4] mmio save restore refine in vgpu switch Weinan Li
` (3 preceding siblings ...)
2017-12-12 2:09 ` [PATCH v2 4/4] drm/i915/gvt: load host render mocs once in mocs switch Weinan Li
@ 2017-12-12 10:06 ` Joonas Lahtinen
4 siblings, 0 replies; 6+ messages in thread
From: Joonas Lahtinen @ 2017-12-12 10:06 UTC (permalink / raw)
To: Weinan Li, intel-gfx
Hi Li,
I guess this is still on the wrong mailing list :)
You have a better chance of getting review input in the gvt list.
Regards, Joonas
On Tue, 2017-12-12 at 10:09 +0800, Weinan Li wrote:
> Merge switch_mmio_to_vgpu and switch_mmio_to_host, use delta update for
> mocs save restore, deal host mocs value as fixed, it won't be changed after
> initialization. These can save vgpu switch time to reduce CPU utilization
> and improve GPU performance in GVT-g with multi-VMs.
>
> v2: code rebase
>
> Weinan Li (4):
> drm/i915/gvt: refine trace_render_mmio
> drm/i915/gvt: optimize for vGPU mmio switch
> drm/i915/gvt: refine mocs save restore policy
> drm/i915/gvt: load host render mocs once in mocs switch
>
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++
> drivers/gpu/drm/i915/gvt/mmio_context.c | 236 +++++++++++++++++---------------
> drivers/gpu/drm/i915/gvt/trace.h | 15 +-
> 3 files changed, 151 insertions(+), 119 deletions(-)
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 6+ messages in thread