From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH] clk: meson: mpll: use 64-bit maths in params_from_rate
Date: Sat, 23 Dec 2017 23:28:51 +0100 [thread overview]
Message-ID: <1514068131.4333.1.camel@baylibre.com> (raw)
In-Reply-To: <20171223213832.16552-1-martin.blumenstingl@googlemail.com>
On Sat, 2017-12-23 at 22:38 +0100, Martin Blumenstingl wrote:
> "rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b
> SoCs if the "remainder" (after the division operation) is greater than
> 262143Hz. This is likely to happen since the input clock for the MPLLs
> on Meson8 and Meson8b is "fixed_pll", which is running at a rate of
> 2550MHz.
>
> One example where this was observed to be problematic was the Ethernet
> clock calculation (which takes MPLL2 as input). When requesting a rate
> of 125MHz there is a remainder of 2500000Hz.
> The resulting MPLL2 rate before this patch was 127488329Hz.
> The resulting MPLL2 rate after this patch is 124999103Hz.
>
> Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in
> rate_from_params") already fixed a similar issue in rate_from_params.
>
> Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Good catch !
Applied to next/drivers
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
narmstrong@baylibre.com, linux-amlogic@lists.infradead.org
Cc: khilman@baylibre.com, carlo@caione.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH] clk: meson: mpll: use 64-bit maths in params_from_rate
Date: Sat, 23 Dec 2017 23:28:51 +0100 [thread overview]
Message-ID: <1514068131.4333.1.camel@baylibre.com> (raw)
In-Reply-To: <20171223213832.16552-1-martin.blumenstingl@googlemail.com>
On Sat, 2017-12-23 at 22:38 +0100, Martin Blumenstingl wrote:
> "rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b
> SoCs if the "remainder" (after the division operation) is greater than
> 262143Hz. This is likely to happen since the input clock for the MPLLs
> on Meson8 and Meson8b is "fixed_pll", which is running at a rate of
> 2550MHz.
>
> One example where this was observed to be problematic was the Ethernet
> clock calculation (which takes MPLL2 as input). When requesting a rate
> of 125MHz there is a remainder of 2500000Hz.
> The resulting MPLL2 rate before this patch was 127488329Hz.
> The resulting MPLL2 rate after this patch is 124999103Hz.
>
> Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in
> rate_from_params") already fixed a similar issue in rate_from_params.
>
> Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Good catch !
Applied to next/drivers
next prev parent reply other threads:[~2017-12-23 22:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-23 21:38 [PATCH] clk: meson: mpll: use 64-bit maths in params_from_rate Martin Blumenstingl
2017-12-23 21:38 ` Martin Blumenstingl
2017-12-23 22:28 ` Jerome Brunet [this message]
2017-12-23 22:28 ` Jerome Brunet
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