* [PATCH v2 1/2] drm/amd/pp: Expose set/get_power_limit for DGPU
@ 2018-01-30 3:07 Rex Zhu
[not found] ` <1517281663-10684-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2018-01-30 3:07 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
User can change power limit between
[0, 1] * max power limit.
Set power limit to 0, restore to max power limit.
Change-Id: I177415e2ded23118764219dd24d9028d7ffb4283
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 61 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 1 +
.../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 8 +--
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 1 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 7 +--
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 ++
7 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 1fc995b..0572949 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -283,6 +283,8 @@ struct amd_pm_funcs {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+ int (*set_power_limit)(void *handle, uint32_t n);
+ int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
/* export to DC */
u32 (*get_sclk)(void *handle, bool low);
u32 (*get_mclk)(void *handle, bool low);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 86c5e28..ac148d4 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1231,6 +1231,65 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
return ret;
}
+static int pp_set_power_limit(void *handle, uint32_t limit)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ int ret = 0;
+
+ ret = pp_check(pp_handle);
+
+ if (ret)
+ return ret;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->set_power_limit == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ if (limit == 0)
+ limit = hwmgr->default_power_limit;
+
+ if (limit > hwmgr->default_power_limit)
+ return -EINVAL;
+
+ mutex_lock(&pp_handle->pp_lock);
+ hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
+ hwmgr->power_limit = limit;
+ mutex_unlock(&pp_handle->pp_lock);
+ return ret;
+}
+
+static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ int ret = 0;
+
+ ret = pp_check(pp_handle);
+
+ if (ret)
+ return ret;
+
+ if (limit == NULL)
+ return -EINVAL;
+
+ hwmgr = pp_handle->hwmgr;
+
+ mutex_lock(&pp_handle->pp_lock);
+
+ if (default_limit)
+ *limit = hwmgr->default_power_limit;
+ else
+ *limit = hwmgr->power_limit;
+
+ mutex_unlock(&pp_handle->pp_lock);
+
+ return ret;
+}
+
static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
@@ -1503,6 +1562,8 @@ static int pp_get_display_mode_validation_clocks(void *handle,
.get_power_profile_mode = pp_get_power_profile_mode,
.set_power_profile_mode = pp_set_power_profile_mode,
.odn_edit_dpm_table = pp_odn_edit_dpm_table,
+ .set_power_limit = pp_set_power_limit,
+ .get_power_limit = pp_get_power_limit,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 8b8de2f..c83296f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5140,6 +5140,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
.get_power_profile_mode = smu7_get_power_profile_mode,
.set_power_profile_mode = smu7_set_power_profile_mode,
+ .set_power_limit = smu7_set_power_limit,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 85ca16a..a93829d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -857,6 +857,8 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ n = (n & 0xff) << 8;
+
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
return smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -903,12 +905,12 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable PkgPwrTracking in SMC.", result = -1;);
if (0 == smc_result) {
- uint32_t default_limit =
- (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
+ hwmgr->default_power_limit = hwmgr->power_limit =
+ cac_table->usMaximumPowerDeliveryLimit;
data->power_containment_features |=
POWERCONTAINMENT_FEATURE_PkgPwrLimit;
- if (smu7_set_power_limit(hwmgr, default_limit))
+ if (smu7_set_power_limit(hwmgr, hwmgr->power_limit))
pr_err("Failed to set Default Power Limit in SMC!");
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 47b8583..5a08f33 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5152,6 +5152,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui
.start_thermal_controller = vega10_start_thermal_controller,
.get_power_profile_mode = vega10_get_power_profile_mode,
.set_power_profile_mode = vega10_set_power_profile_mode,
+ .set_power_limit = vega10_set_power_limit,
};
int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 598a194..981c9e5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -1357,10 +1357,11 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_tdp_table *tdp_table = table_info->tdp_table;
- uint32_t default_pwr_limit =
- (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
int result = 0;
+ hwmgr->default_power_limit = hwmgr->power_limit =
+ (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
+
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -1374,7 +1375,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
- result = vega10_set_power_limit(hwmgr, default_pwr_limit);
+ result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
PP_ASSERT_WITH_CODE(!result,
"Failed to set Default Power Limit in SMC!",
return result);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index e79c2cf..376af67 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -348,6 +348,7 @@ struct pp_hwmgr_func {
int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
+ int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
};
struct pp_table_func {
@@ -760,6 +761,8 @@ struct pp_hwmgr {
uint32_t pstate_sclk;
uint32_t pstate_mclk;
bool od_enabled;
+ uint32_t power_limit;
+ uint32_t default_power_limit;
};
struct cgs_irq_src_funcs {
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <1517281663-10684-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH v2 2/2] drm/amdgpu/pm: Get/set dgpu power cap via hwmon API [not found] ` <1517281663-10684-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-01-30 3:07 ` Rex Zhu [not found] ` <1517281663-10684-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 3+ messages in thread From: Rex Zhu @ 2018-01-30 3:07 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu v2: change power unit to microWatt Adust power limit through power1_cap Get min/max power limit through power1_cap_min/power1_cap_max Change-Id: I4d678e887229deff07c7a99498244a4f5e5c896e Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 75 ++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index b0cdb14..0a2babb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1207,6 +1207,69 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, return snprintf(buf, PAGE_SIZE, "%u\n", uw); } +static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%i\n", 0); +} + +static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + uint32_t limit = 0; + + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { + adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); + return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); + } else { + return snprintf(buf, PAGE_SIZE, "\n"); + } +} + +static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + uint32_t limit = 0; + + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { + adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); + return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); + } else { + return snprintf(buf, PAGE_SIZE, "\n"); + } +} + + +static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 value; + + err = kstrtou32(buf, 10, &value); + if (err) + return err; + + value = value / 1000000; /* convert to Watt */ + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) { + err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); + if (err) + return err; + } else { + return -EINVAL; + } + + return count; +} + static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); @@ -1220,6 +1283,9 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); +static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); +static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); +static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_temp1_input.dev_attr.attr, @@ -1235,6 +1301,9 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, &sensor_dev_attr_in1_input.dev_attr.attr, &sensor_dev_attr_in1_label.dev_attr.attr, &sensor_dev_attr_power1_average.dev_attr.attr, + &sensor_dev_attr_power1_cap_max.dev_attr.attr, + &sensor_dev_attr_power1_cap_min.dev_attr.attr, + &sensor_dev_attr_power1_cap.dev_attr.attr, NULL }; @@ -1282,6 +1351,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ effective_mode &= ~S_IWUSR; + if ((adev->flags & AMD_IS_APU) && + (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || + attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| + attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) + return 0; + /* hide max/min values if we can't both query and manage the fan */ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && !adev->powerplay.pp_funcs->get_fan_speed_percent) && -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <1517281663-10684-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH v2 2/2] drm/amdgpu/pm: Get/set dgpu power cap via hwmon API [not found] ` <1517281663-10684-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-01-30 4:42 ` Alex Deucher 0 siblings, 0 replies; 3+ messages in thread From: Alex Deucher @ 2018-01-30 4:42 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Mon, Jan 29, 2018 at 10:07 PM, Rex Zhu <Rex.Zhu@amd.com> wrote: > v2: change power unit to microWatt > > Adust power limit through power1_cap > Get min/max power limit through power1_cap_min/power1_cap_max > > Change-Id: I4d678e887229deff07c7a99498244a4f5e5c896e > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> For the series: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 75 ++++++++++++++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > index b0cdb14..0a2babb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > @@ -1207,6 +1207,69 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, > return snprintf(buf, PAGE_SIZE, "%u\n", uw); > } > > +static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + return sprintf(buf, "%i\n", 0); > +} > + > +static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct amdgpu_device *adev = dev_get_drvdata(dev); > + uint32_t limit = 0; > + > + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { > + adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); > + return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); > + } else { > + return snprintf(buf, PAGE_SIZE, "\n"); > + } > +} > + > +static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct amdgpu_device *adev = dev_get_drvdata(dev); > + uint32_t limit = 0; > + > + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { > + adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); > + return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); > + } else { > + return snprintf(buf, PAGE_SIZE, "\n"); > + } > +} > + > + > +static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t count) > +{ > + struct amdgpu_device *adev = dev_get_drvdata(dev); > + int err; > + u32 value; > + > + err = kstrtou32(buf, 10, &value); > + if (err) > + return err; > + > + value = value / 1000000; /* convert to Watt */ > + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) { > + err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); > + if (err) > + return err; > + } else { > + return -EINVAL; > + } > + > + return count; > +} > + > static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); > static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); > static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); > @@ -1220,6 +1283,9 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, > static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); > static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); > static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); > +static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); > +static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); > +static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); > > static struct attribute *hwmon_attributes[] = { > &sensor_dev_attr_temp1_input.dev_attr.attr, > @@ -1235,6 +1301,9 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, > &sensor_dev_attr_in1_input.dev_attr.attr, > &sensor_dev_attr_in1_label.dev_attr.attr, > &sensor_dev_attr_power1_average.dev_attr.attr, > + &sensor_dev_attr_power1_cap_max.dev_attr.attr, > + &sensor_dev_attr_power1_cap_min.dev_attr.attr, > + &sensor_dev_attr_power1_cap.dev_attr.attr, > NULL > }; > > @@ -1282,6 +1351,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, > attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ > effective_mode &= ~S_IWUSR; > > + if ((adev->flags & AMD_IS_APU) && > + (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || > + attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| > + attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) > + return 0; > + > /* hide max/min values if we can't both query and manage the fan */ > if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && > !adev->powerplay.pp_funcs->get_fan_speed_percent) && > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-01-30 3:07 [PATCH v2 1/2] drm/amd/pp: Expose set/get_power_limit for DGPU Rex Zhu
[not found] ` <1517281663-10684-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-30 3:07 ` [PATCH v2 2/2] drm/amdgpu/pm: Get/set dgpu power cap via hwmon API Rex Zhu
[not found] ` <1517281663-10684-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-30 4:42 ` Alex Deucher
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