From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs
Date: Wed, 05 Jan 2011 23:31:29 -0800 [thread overview]
Message-ID: <15216cd202530798c9d4c5beeb45c6ba@localhost> (raw)
In-Reply-To: <8eec0c63f92528c501c0e6a0c8396359@localhost>
BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/kernel/irq_cpu.c | 14 ++++++--------
1 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe..70d4736 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- /*
- * Only MT is using the software interrupts currently, so we just
- * leave them uninitialized for other processors.
- */
- if (cpu_has_mipsmt)
- for (i = irq_base; i < irq_base + 2; i++)
- set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
- handle_percpu_irq);
+ /* Software interrupts are used for MT/CMT IPI */
+ for (i = irq_base; i < irq_base + 2; i++)
+ set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+ &mips_mt_cpu_irq_controller :
+ &mips_cpu_irq_controller,
+ handle_percpu_irq);
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
--
1.7.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs
Date: Wed, 05 Jan 2011 23:31:29 -0800 [thread overview]
Message-ID: <15216cd202530798c9d4c5beeb45c6ba@localhost> (raw)
Message-ID: <20110106073129.eCEAuHkZjgQudpK_6_QC6KLt4UY5uiv_f85govHsHTA@z> (raw)
In-Reply-To: <8eec0c63f92528c501c0e6a0c8396359@localhost>
BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/kernel/irq_cpu.c | 14 ++++++--------
1 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe..70d4736 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- /*
- * Only MT is using the software interrupts currently, so we just
- * leave them uninitialized for other processors.
- */
- if (cpu_has_mipsmt)
- for (i = irq_base; i < irq_base + 2; i++)
- set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
- handle_percpu_irq);
+ /* Software interrupts are used for MT/CMT IPI */
+ for (i = irq_base; i < irq_base + 2; i++)
+ set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+ &mips_mt_cpu_irq_controller :
+ &mips_cpu_irq_controller,
+ handle_percpu_irq);
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
--
1.7.0.4
next prev parent reply other threads:[~2011-01-06 7:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-06 7:31 [PATCH RESEND 1/6] MIPS: sync after cacheflush Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee
2011-01-06 7:31 ` [PATCH RESEND 2/6] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee
2011-01-06 17:36 ` David Daney
2011-01-06 7:31 ` [PATCH v2 RESEND 3/6] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee
2011-01-06 7:31 ` [PATCH v4 RESEND 4/6] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee [this message]
2011-01-06 7:31 ` [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee
2011-01-06 7:31 ` [PATCH 6/6] MIPS: Limit fixrange_init() to the FIXMAP region Kevin Cernekee
2011-01-06 7:31 ` Kevin Cernekee
2011-05-19 13:03 ` Ralf Baechle
2011-01-06 16:17 ` [PATCH RESEND 1/6] MIPS: sync after cacheflush Shinya Kuribayashi
-- strict thread matches above, loose matches on Subject: below --
2011-01-14 1:52 [PATCH v2 1/6] MIPS: Sync after cacheflush on BMIPS processors Kevin Cernekee
2011-01-14 1:52 ` [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee
2011-01-14 1:52 ` Kevin Cernekee
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