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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 00/17] ICL PLLs, DP/HDMI and misc display
Date: Thu, 22 Mar 2018 17:05:02 -0700	[thread overview]
Message-ID: <1521763502.26921.59.camel@intel.com> (raw)
In-Reply-To: <20180222035519.13486-1-paulo.r.zanoni@intel.com>

Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> Hello
> 
> Here are some more ICL patches, now with the Combo & MG PLLs, some
> DP/HDMI
> initialization code and a few misc fixes.
> 
> Again, the R-B tags already present in some of the patches (including
> those form
> me) were given a long time ago, so they need to be re-issued due to
> the
> rebasing.

The following patches have my Reviewed-by: 6, 7, 9, 10, 13 and 15.

I'll send updated patches soon.

> 
> Thanks,
> Paulo
> 
> Arkadiusz Hiler (1):
>   drm/i915/icl: Calculate link clock using the new registers
> 
> Dhinakaran Pandiyan (1):
>   drm/i915/icl: HPD pin for port F
> 
> James Ausmus (1):
>   drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
> 
> Manasi Navare (7):
>   drm/i915/icl: Add register definitions for Combo PHY vswing
> sequences.
>   drm/i915/icl: Add Combo PHY DDI Buffer translation tables for
> Icelake.
>   drm/i915/icl: Implement voltage swing programming sequence for
> Combo
>     PHY DDI
>   drm/i915/icl: Add register defs for voltage swing sequences for MG
> PHY
>     DDI
>   drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
>   drm/i915/icl: Implement voltage swing programming sequence for MG
> PHY
>     DDI
>   drm/i915/icl: Fix the DP Max Voltage for ICL
> 
> Nabendu Maiti (1):
>   drm/i915/icl: Added 5k source scaling support for Gen11 platform
> 
> Paulo Zanoni (6):
>   drm/i915/icl: add definitions for the ICL PLL registers
>   drm/i915/icl: add basic support for the ICL clocks
>   drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
>   drm/i915/icl: compute the combo PHY (DPLL) DP registers
>   drm/i915/icl: compute the MG PLL registers
>   drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes
> 
>  drivers/gpu/drm/i915/i915_debugfs.c   |  22 ++
>  drivers/gpu/drm/i915/i915_drv.h       |   1 +
>  drivers/gpu/drm/i915/i915_reg.h       | 313 ++++++++++++++++-
>  drivers/gpu/drm/i915/intel_ddi.c      | 529
> +++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_display.c  |  33 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 642
> +++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +++
>  drivers/gpu/drm/i915/intel_drv.h      |  10 +
>  drivers/gpu/drm/i915/intel_hotplug.c  |   3 +
>  9 files changed, 1569 insertions(+), 25 deletions(-)
> 
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  parent reply	other threads:[~2018-03-23  0:05 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-22  3:55 [PATCH 00/17] ICL PLLs, DP/HDMI and misc display Paulo Zanoni
2018-02-22  3:55 ` [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers Paulo Zanoni
2018-02-27 22:22   ` James Ausmus
2018-03-21 21:34     ` Paulo Zanoni
2018-03-23  0:07   ` Paulo Zanoni
2018-03-23  0:08   ` [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks Paulo Zanoni
2018-02-22  3:55 ` Paulo Zanoni
2018-02-28  0:40   ` James Ausmus
2018-02-22  3:55 ` [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers Paulo Zanoni
2018-02-28 19:59   ` James Ausmus
2018-02-22  3:55 ` [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers Paulo Zanoni
2018-02-28 20:12   ` James Ausmus
2018-02-22  3:55 ` [PATCH 05/17] drm/i915/icl: compute the MG PLL registers Paulo Zanoni
2018-03-01 23:35   ` Manasi Navare
2018-02-22  3:55 ` [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
2018-02-22  3:55 ` [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
2018-02-22  3:55 ` [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI Paulo Zanoni
2018-03-22 22:23   ` Paulo Zanoni
2018-03-23  0:10   ` Paulo Zanoni
2018-04-28  0:28     ` Rodrigo Vivi
2018-04-06  0:20   ` Rodrigo Vivi
2018-04-25  0:34     ` Paulo Zanoni
2018-04-25 18:01       ` Rodrigo Vivi
2018-04-25 23:33         ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG " Paulo Zanoni
2018-02-22  3:55 ` [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
2018-02-22  3:55 ` [PATCH 11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI Paulo Zanoni
2018-03-22 22:58   ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 12/17] drm/i915/icl: HPD pin for port F Paulo Zanoni
2018-02-22 20:16   ` Rodrigo Vivi
2018-02-22  3:55 ` [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
2018-02-22  3:55 ` [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
2018-03-22 23:20   ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
2018-02-22  3:55 ` [PATCH 16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes Paulo Zanoni
2018-02-22  3:55 ` [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL Paulo Zanoni
2018-03-23  0:03   ` Rodrigo Vivi
2018-02-22  4:09 ` ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display Patchwork
2018-02-22  4:24 ` ✗ Fi.CI.BAT: " Patchwork
2018-03-23  0:05 ` Paulo Zanoni [this message]
2018-03-23  1:00 ` ✗ Fi.CI.BAT: failure for ICL PLLs, DP/HDMI and misc display (rev4) Patchwork

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