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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL
Date: Thu, 22 Mar 2018 17:03:48 -0700	[thread overview]
Message-ID: <20180323000347.GT2557@intel.com> (raw)
In-Reply-To: <20180222035519.13486-18-paulo.r.zanoni@intel.com>

On Thu, Feb 22, 2018 at 12:55:19AM -0300, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. ICL uses different set of tables for eDP
> and DP for both Combo and MG PHY ports. This patch adds the hook
> for ICL for getting this information from appropriate buf trans tables.
> 
> v5 (from Paulo):
> * New rebase after changes to earlier patches.
> v4:
> * Rebase.
> v3:
> * Follow the coding conventions here
> (https://cgit.freedesktop.org/drm-intel/tree/Documentation/process/codin
> g-style.rst#n191) (Paulo)
> v2:
> * Rebase after patch that adds voltage check inside buf trans
> function (Rodrigo)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

seems a lot change since my first review, but everything looks
correct to me still on this newer version. So

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ad82ef91263e..fbdd2340c8aa 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2085,7 +2085,13 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  	int n_entries;
>  
> -	if (IS_CANNONLAKE(dev_priv)) {
> +	if (IS_ICELAKE(dev_priv)) {
> +		if (port == PORT_A || port == PORT_B)
> +			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> +						&n_entries);
> +		else
> +			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
>  		if (encoder->type == INTEL_OUTPUT_EDP)
>  			cnl_get_buf_trans_edp(dev_priv, &n_entries);
>  		else
> -- 
> 2.14.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2018-03-23  0:03 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-22  3:55 [PATCH 00/17] ICL PLLs, DP/HDMI and misc display Paulo Zanoni
2018-02-22  3:55 ` [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers Paulo Zanoni
2018-02-27 22:22   ` James Ausmus
2018-03-21 21:34     ` Paulo Zanoni
2018-03-23  0:07   ` Paulo Zanoni
2018-03-23  0:08   ` [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks Paulo Zanoni
2018-02-22  3:55 ` Paulo Zanoni
2018-02-28  0:40   ` James Ausmus
2018-02-22  3:55 ` [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers Paulo Zanoni
2018-02-28 19:59   ` James Ausmus
2018-02-22  3:55 ` [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers Paulo Zanoni
2018-02-28 20:12   ` James Ausmus
2018-02-22  3:55 ` [PATCH 05/17] drm/i915/icl: compute the MG PLL registers Paulo Zanoni
2018-03-01 23:35   ` Manasi Navare
2018-02-22  3:55 ` [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
2018-02-22  3:55 ` [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
2018-02-22  3:55 ` [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI Paulo Zanoni
2018-03-22 22:23   ` Paulo Zanoni
2018-03-23  0:10   ` Paulo Zanoni
2018-04-28  0:28     ` Rodrigo Vivi
2018-04-06  0:20   ` Rodrigo Vivi
2018-04-25  0:34     ` Paulo Zanoni
2018-04-25 18:01       ` Rodrigo Vivi
2018-04-25 23:33         ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG " Paulo Zanoni
2018-02-22  3:55 ` [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
2018-02-22  3:55 ` [PATCH 11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI Paulo Zanoni
2018-03-22 22:58   ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 12/17] drm/i915/icl: HPD pin for port F Paulo Zanoni
2018-02-22 20:16   ` Rodrigo Vivi
2018-02-22  3:55 ` [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
2018-02-22  3:55 ` [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
2018-03-22 23:20   ` Paulo Zanoni
2018-02-22  3:55 ` [PATCH 15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
2018-02-22  3:55 ` [PATCH 16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes Paulo Zanoni
2018-02-22  3:55 ` [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL Paulo Zanoni
2018-03-23  0:03   ` Rodrigo Vivi [this message]
2018-02-22  4:09 ` ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display Patchwork
2018-02-22  4:24 ` ✗ Fi.CI.BAT: " Patchwork
2018-03-23  0:05 ` [PATCH 00/17] " Paulo Zanoni
2018-03-23  1:00 ` ✗ Fi.CI.BAT: failure for ICL PLLs, DP/HDMI and misc display (rev4) Patchwork

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