Patch "x86/microcode/intel: Writeback and invalidate caches before updating microcode" has been added to the 4.15-stable tree

Patch "x86/microcode/intel: Writeback and invalidate caches before updating microcode" has been added to the 4.15-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    x86/microcode/intel: Writeback and invalidate caches before updating microcode

to the 4.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
and it can be found in the queue-4.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From 91df9fdf51492aec9fed6b4cbd33160886740f47 Mon Sep 17 00:00:00 2001
From: Ashok Raj <ashok.raj@intel.com>
Date: Wed, 28 Feb 2018 11:28:42 +0100
Subject: x86/microcode/intel: Writeback and invalidate caches before updating microcode

From: Ashok Raj <ashok.raj@intel.com>

commit 91df9fdf51492aec9fed6b4cbd33160886740f47 upstream.

Updating microcode is less error prone when caches have been flushed and
depending on what exactly the microcode is updating. For example, some
of the issues around certain Broadwell parts can be addressed by doing a
full cache flush.

[ Borislav: Massage it and use native_wbinvd() in both cases. ]

Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Tested-by: Ashok Raj <ashok.raj@intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
Link: http://lkml.kernel.org/r/1519352533-15992-3-git-send-email-ashok.raj@intel.com
Link: https://lkml.kernel.org/r/20180228102846.13447-4-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 arch/x86/kernel/cpu/microcode/intel.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -600,6 +600,12 @@ static int apply_microcode_early(struct
 		return UCODE_OK;
 	}
 
+	/*
+	 * Writeback and invalidate caches before updating microcode to avoid
+	 * internal issues depending on what the microcode is updating.
+	 */
+	native_wbinvd();
+
 	/* write microcode via MSR 0x79 */
 	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -816,6 +822,12 @@ static enum ucode_state apply_microcode_
 		return UCODE_OK;
 	}
 
+	/*
+	 * Writeback and invalidate caches before updating microcode to avoid
+	 * internal issues depending on what the microcode is updating.
+	 */
+	native_wbinvd();
+
 	/* write microcode via MSR 0x79 */
 	wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 


Patches currently in stable-queue which might be from ashok.raj@intel.com are

queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch