From: Rishabh Bhatnagar <rishabhb@codeaurora.org>
To: linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Cc: linux-arm@lists.infradead.org, linux-kernel@vger.kernel.org,
tsoni@codeaurora.org, kyan@codeaurora.org,
ckadabi@codeaurora.org, stanimir.varbanov@linaro.org,
evgreen@chromium.org, Rishabh Bhatnagar <rishabhb@codeaurora.org>
Subject: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc
Date: Tue, 10 Apr 2018 13:08:12 -0700 [thread overview]
Message-ID: <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> (raw)
In-Reply-To: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org>
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..497cf0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,58 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: must be addresses and sizes of the LLCC registers
+
+- #cache-cells:
+ Usage: required
+ Value Type: <u32>
+ Definition: Number of cache cells, must be 1
+
+- max-slices:
+ usage: required
+ Value Type: <u32>
+ Definition: Number of cache slices supported by hardware
+
+Example:
+
+ llcc: qcom,llcc@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ #cache-cells = <1>;
+ max-slices = <32>;
+ };
+
+== Client ==
+
+Properties:
+- cache-slice-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: A set of names that identify the usecase names of a
+ client that uses cache slice. These strings are
+ used to look up the cache slice entries by name.
+
+- cache-slices:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: The tuple has phandle to llcc device as the first
+ argument and the second argument is the usecase
+ id of the client.
+For Example:
+ venus {
+ cache-slice-names = "vidsc0", "vidsc1";
+ cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: rishabhb@codeaurora.org (Rishabh Bhatnagar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc
Date: Tue, 10 Apr 2018 13:08:12 -0700 [thread overview]
Message-ID: <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> (raw)
In-Reply-To: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org>
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..497cf0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,58 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: must be addresses and sizes of the LLCC registers
+
+- #cache-cells:
+ Usage: required
+ Value Type: <u32>
+ Definition: Number of cache cells, must be 1
+
+- max-slices:
+ usage: required
+ Value Type: <u32>
+ Definition: Number of cache slices supported by hardware
+
+Example:
+
+ llcc: qcom,llcc at 1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ #cache-cells = <1>;
+ max-slices = <32>;
+ };
+
+== Client ==
+
+Properties:
+- cache-slice-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: A set of names that identify the usecase names of a
+ client that uses cache slice. These strings are
+ used to look up the cache slice entries by name.
+
+- cache-slices:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: The tuple has phandle to llcc device as the first
+ argument and the second argument is the usecase
+ id of the client.
+For Example:
+ venus {
+ cache-slice-names = "vidsc0", "vidsc1";
+ cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2018-04-10 20:08 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-10 20:08 [PATCH v4 0/2] SDM845 System Cache Driver Rishabh Bhatnagar
2018-04-10 20:08 ` Rishabh Bhatnagar
2018-04-10 20:08 ` Rishabh Bhatnagar [this message]
2018-04-10 20:08 ` [PATCH v4 1/2] Documentation: Documentation for qcom, llcc Rishabh Bhatnagar
2018-04-12 22:07 ` Evan Green
2018-04-12 22:07 ` Evan Green
2018-04-16 14:59 ` Rob Herring
2018-04-16 14:59 ` Rob Herring
2018-04-17 17:43 ` rishabhb
2018-04-17 17:43 ` rishabhb at codeaurora.org
2018-04-17 22:12 ` rishabhb
2018-04-17 22:12 ` rishabhb at codeaurora.org
2018-04-18 14:52 ` Rob Herring
2018-04-18 14:52 ` Rob Herring
2018-04-18 18:11 ` Channa
2018-04-18 18:11 ` Channa
2018-04-20 18:51 ` Channa
2018-04-20 18:51 ` Channa
2018-04-10 20:08 ` [PATCH v4 2/2] drivers: soc: Add LLCC driver Rishabh Bhatnagar
2018-04-10 20:08 ` Rishabh Bhatnagar
2018-04-10 20:31 ` Jordan Crouse
2018-04-10 20:31 ` Jordan Crouse
2018-04-12 22:02 ` Evan Green
2018-04-12 22:02 ` Evan Green
2018-04-13 23:08 ` rishabhb
2018-04-13 23:08 ` rishabhb at codeaurora.org
2018-04-16 17:14 ` Evan Green
2018-04-16 17:14 ` Evan Green
2018-04-16 20:50 ` rishabhb
2018-04-16 20:50 ` rishabhb at codeaurora.org
2018-04-16 17:20 ` saiprakash.ranjan
2018-04-16 17:20 ` saiprakash.ranjan at codeaurora.org
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