* [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers
@ 2018-05-10 21:23 Oscar Mateo
2018-05-10 21:33 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Oscar Mateo @ 2018-05-10 21:23 UTC (permalink / raw)
To: intel-gfx
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.
Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for leaving
them out. See gen11_service_one_iir() for more info.
v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
- Rebased
- Renamed patch
- Improved the ordering of GENs
- Improved the printing of per-GEN info
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 ++++++++++++++++++----------
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d663a9e0..8a7030a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1170,19 +1170,22 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
- pm_ier = I915_READ(GEN6_PMIER);
- pm_imr = I915_READ(GEN6_PMIMR);
- pm_isr = I915_READ(GEN6_PMISR);
- pm_iir = I915_READ(GEN6_PMIIR);
- pm_mask = I915_READ(GEN6_PMINTRMSK);
- } else {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+ pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+ } else if (INTEL_GEN(dev_priv) >= 8) {
pm_ier = I915_READ(GEN8_GT_IER(2));
pm_imr = I915_READ(GEN8_GT_IMR(2));
pm_isr = I915_READ(GEN8_GT_ISR(2));
pm_iir = I915_READ(GEN8_GT_IIR(2));
- pm_mask = I915_READ(GEN6_PMINTRMSK);
+ } else {
+ pm_ier = I915_READ(GEN6_PMIER);
+ pm_imr = I915_READ(GEN6_PMIMR);
+ pm_isr = I915_READ(GEN6_PMISR);
+ pm_iir = I915_READ(GEN6_PMIIR);
}
+ pm_mask = I915_READ(GEN6_PMINTRMSK);
+
seq_printf(m, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
seq_printf(m, "HW control enabled: %s\n",
@@ -1190,8 +1193,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "SW control enabled: %s\n",
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
- seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
- pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+
+ seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
+ pm_ier, pm_imr, pm_mask);
+ if (INTEL_GEN(dev_priv) < 11) {
+ seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+ pm_isr, pm_iir);
+ }
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b98cd44..d9f2f69 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1675,7 +1675,16 @@ static void capture_reg_state(struct i915_gpu_state *error)
}
/* 4: Everything else */
- if (INTEL_GEN(dev_priv) >= 8) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ error->ier = I915_READ(GEN8_DE_MISC_IER);
+ error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+ error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+ error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
+ error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+ error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
+ error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
+ error->ngtier = 6;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
error->ier = I915_READ(GEN8_DE_MISC_IER);
for (i = 0; i < 4; i++)
error->gtier[i] = I915_READ(GEN8_GT_IER(i));
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index dac0f8c..58910f1 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -58,7 +58,7 @@ struct i915_gpu_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
- u32 gtier[4], ngtier;
+ u32 gtier[6], ngtier;
u32 ccid;
u32 derrmr;
u32 forcewake;
--
1.9.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-10 21:23 [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers Oscar Mateo @ 2018-05-10 21:33 ` Patchwork 2018-05-10 21:59 ` [PATCH] " Oscar Mateo ` (2 subsequent siblings) 3 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2018-05-10 21:33 UTC (permalink / raw) To: Oscar Mateo; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Read the correct Gen11 interrupt registers URL : https://patchwork.freedesktop.org/series/43027/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALL scripts/checksyscalls.sh DESCEND objtool CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/i915_debugfs.o drivers/gpu/drm/i915/i915_debugfs.c: In function ‘i915_frequency_info’: drivers/gpu/drm/i915/i915_debugfs.c:1192:4: error: ‘pm_iir’ may be used uninitialized in this function [-Werror=maybe-uninitialized] seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ pm_isr, pm_iir); ~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/i915_debugfs.c:1192:4: error: ‘pm_isr’ may be used uninitialized in this function [-Werror=maybe-uninitialized] cc1: all warnings being treated as errors scripts/Makefile.build:312: recipe for target 'drivers/gpu/drm/i915/i915_debugfs.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_debugfs.o] Error 1 scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1060: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-10 21:23 [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers Oscar Mateo 2018-05-10 21:33 ` ✗ Fi.CI.BAT: failure for " Patchwork @ 2018-05-10 21:59 ` Oscar Mateo 2018-05-11 17:06 ` Vinay Belgaumkar 2018-05-16 23:39 ` Paulo Zanoni 2018-05-10 22:42 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) Patchwork 2018-05-10 23:49 ` ✓ Fi.CI.IGT: " Patchwork 3 siblings, 2 replies; 11+ messages in thread From: Oscar Mateo @ 2018-05-10 21:59 UTC (permalink / raw) To: intel-gfx Stop reading some now deprecated interrupt registers in both debugfs and error state. Instead, read the new equivalents in the Gen11 interrupt repartitioning scheme. Note that the equivalent to the PM ISR & IIR cannot be read without affecting the current state of the system, so I've opted for leaving them out. See gen11_service_one_iir() for more info. v2: else if !!! (Paulo) v3: another else if (Vinay) v4: - Rebased - Renamed patch - Improved the ordering of GENs - Improved the printing of per-GEN info v5: Avoid maybe-unitialized & add comment explaining the lack of PM ISR & IIR Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- 3 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d663a9e0..d992dd2 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { - pm_ier = I915_READ(GEN6_PMIER); - pm_imr = I915_READ(GEN6_PMIMR); - pm_isr = I915_READ(GEN6_PMISR); - pm_iir = I915_READ(GEN6_PMIIR); - pm_mask = I915_READ(GEN6_PMINTRMSK); - } else { + if (INTEL_GEN(dev_priv) >= 11) { + pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); + pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); + /* + * The equivalent to the PM ISR & IIR cannot be read + * without affecting the current state of the system + */ + pm_isr = 0; + pm_iir = 0; + } else if (INTEL_GEN(dev_priv) >= 8) { pm_ier = I915_READ(GEN8_GT_IER(2)); pm_imr = I915_READ(GEN8_GT_IMR(2)); pm_isr = I915_READ(GEN8_GT_ISR(2)); pm_iir = I915_READ(GEN8_GT_IIR(2)); - pm_mask = I915_READ(GEN6_PMINTRMSK); + } else { + pm_ier = I915_READ(GEN6_PMIER); + pm_imr = I915_READ(GEN6_PMIMR); + pm_isr = I915_READ(GEN6_PMISR); + pm_iir = I915_READ(GEN6_PMIIR); } + pm_mask = I915_READ(GEN6_PMINTRMSK); + seq_printf(m, "Video Turbo Mode: %s\n", yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); seq_printf(m, "HW control enabled: %s\n", @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "SW control enabled: %s\n", yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); + + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", + pm_ier, pm_imr, pm_mask); + if (INTEL_GEN(dev_priv) < 11) { + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", + pm_isr, pm_iir); + } seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", rps->pm_intrmsk_mbz); seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index b98cd44..d9f2f69 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct i915_gpu_state *error) } /* 4: Everything else */ - if (INTEL_GEN(dev_priv) >= 8) { + if (INTEL_GEN(dev_priv) >= 11) { + error->ier = I915_READ(GEN8_DE_MISC_IER); + error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); + error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); + error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE); + error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); + error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); + error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); + error->ngtier = 6; + } else if (INTEL_GEN(dev_priv) >= 8) { error->ier = I915_READ(GEN8_DE_MISC_IER); for (i = 0; i < 4; i++) error->gtier[i] = I915_READ(GEN8_GT_IER(i)); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index dac0f8c..58910f1 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -58,7 +58,7 @@ struct i915_gpu_state { u32 eir; u32 pgtbl_er; u32 ier; - u32 gtier[4], ngtier; + u32 gtier[6], ngtier; u32 ccid; u32 derrmr; u32 forcewake; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-10 21:59 ` [PATCH] " Oscar Mateo @ 2018-05-11 17:06 ` Vinay Belgaumkar 2018-05-16 23:39 ` Paulo Zanoni 1 sibling, 0 replies; 11+ messages in thread From: Vinay Belgaumkar @ 2018-05-11 17:06 UTC (permalink / raw) To: Oscar Mateo, intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 5094 bytes --] On 05/10/2018 02:59 PM, Oscar Mateo wrote: > Stop reading some now deprecated interrupt registers in both > debugfs and error state. Instead, read the new equivalents in the > Gen11 interrupt repartitioning scheme. > > Note that the equivalent to the PM ISR & IIR cannot be read without > affecting the current state of the system, so I've opted for leaving > them out. See gen11_service_one_iir() for more info. > > v2: else if !!! (Paulo) > v3: another else if (Vinay) > v4: > - Rebased > - Renamed patch > - Improved the ordering of GENs > - Improved the printing of per-GEN info > v5: Avoid maybe-unitialized & add comment explaining the lack > of PM ISR & IIR > > Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > --- Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++---------- > drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- > drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- > 3 files changed, 35 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index d663a9e0..d992dd2 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { > - pm_ier = I915_READ(GEN6_PMIER); > - pm_imr = I915_READ(GEN6_PMIMR); > - pm_isr = I915_READ(GEN6_PMISR); > - pm_iir = I915_READ(GEN6_PMIIR); > - pm_mask = I915_READ(GEN6_PMINTRMSK); > - } else { > + if (INTEL_GEN(dev_priv) >= 11) { > + pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > + pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); > + /* > + * The equivalent to the PM ISR & IIR cannot be read > + * without affecting the current state of the system > + */ > + pm_isr = 0; > + pm_iir = 0; > + } else if (INTEL_GEN(dev_priv) >= 8) { > pm_ier = I915_READ(GEN8_GT_IER(2)); > pm_imr = I915_READ(GEN8_GT_IMR(2)); > pm_isr = I915_READ(GEN8_GT_ISR(2)); > pm_iir = I915_READ(GEN8_GT_IIR(2)); > - pm_mask = I915_READ(GEN6_PMINTRMSK); > + } else { > + pm_ier = I915_READ(GEN6_PMIER); > + pm_imr = I915_READ(GEN6_PMIMR); > + pm_isr = I915_READ(GEN6_PMISR); > + pm_iir = I915_READ(GEN6_PMIIR); > } > + pm_mask = I915_READ(GEN6_PMINTRMSK); > + > seq_printf(m, "Video Turbo Mode: %s\n", > yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > seq_printf(m, "HW control enabled: %s\n", > @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > seq_printf(m, "SW control enabled: %s\n", > yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > GEN6_RP_MEDIA_SW_MODE)); > - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", > - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); > + > + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", > + pm_ier, pm_imr, pm_mask); > + if (INTEL_GEN(dev_priv) < 11) { > + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", > + pm_isr, pm_iir); > + } > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index b98cd44..d9f2f69 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct i915_gpu_state *error) > } > > /* 4: Everything else */ > - if (INTEL_GEN(dev_priv) >= 8) { > + if (INTEL_GEN(dev_priv) >= 11) { > + error->ier = I915_READ(GEN8_DE_MISC_IER); > + error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); > + error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); > + error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE); > + error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > + error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); > + error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); > + error->ngtier = 6; > + } else if (INTEL_GEN(dev_priv) >= 8) { > error->ier = I915_READ(GEN8_DE_MISC_IER); > for (i = 0; i < 4; i++) > error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h > index dac0f8c..58910f1 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.h > +++ b/drivers/gpu/drm/i915/i915_gpu_error.h > @@ -58,7 +58,7 @@ struct i915_gpu_state { > u32 eir; > u32 pgtbl_er; > u32 ier; > - u32 gtier[4], ngtier; > + u32 gtier[6], ngtier; > u32 ccid; > u32 derrmr; > u32 forcewake; [-- Attachment #1.2: Type: text/html, Size: 6100 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-10 21:59 ` [PATCH] " Oscar Mateo 2018-05-11 17:06 ` Vinay Belgaumkar @ 2018-05-16 23:39 ` Paulo Zanoni 2018-05-17 16:55 ` Michel Thierry 1 sibling, 1 reply; 11+ messages in thread From: Paulo Zanoni @ 2018-05-16 23:39 UTC (permalink / raw) To: Oscar Mateo, intel-gfx Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: > Stop reading some now deprecated interrupt registers in both > debugfs and error state. Instead, read the new equivalents in the > Gen11 interrupt repartitioning scheme. > > Note that the equivalent to the PM ISR & IIR cannot be read without > affecting the current state of the system, so I've opted for leaving > them out. See gen11_service_one_iir() for more info. I can't find this function. Did you mean something else? > > v2: else if !!! (Paulo) > v3: another else if (Vinay) > v4: > - Rebased > - Renamed patch > - Improved the ordering of GENs > - Improved the printing of per-GEN info > v5: Avoid maybe-unitialized & add comment explaining the lack > of PM ISR & IIR > > Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++- > --------- > drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- > drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- > 3 files changed, 35 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index d663a9e0..d992dd2 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct > seq_file *m, void *unused) > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { > - pm_ier = I915_READ(GEN6_PMIER); > - pm_imr = I915_READ(GEN6_PMIMR); > - pm_isr = I915_READ(GEN6_PMISR); > - pm_iir = I915_READ(GEN6_PMIIR); > - pm_mask = I915_READ(GEN6_PMINTRMSK); > - } else { > + if (INTEL_GEN(dev_priv) >= 11) { > + pm_ier = > I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > + pm_imr = > I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); > + /* > + * The equivalent to the PM ISR & IIR cannot > be read > + * without affecting the current state of > the system > + */ > + pm_isr = 0; > + pm_iir = 0; > + } else if (INTEL_GEN(dev_priv) >= 8) { > pm_ier = I915_READ(GEN8_GT_IER(2)); > pm_imr = I915_READ(GEN8_GT_IMR(2)); > pm_isr = I915_READ(GEN8_GT_ISR(2)); > pm_iir = I915_READ(GEN8_GT_IIR(2)); > - pm_mask = I915_READ(GEN6_PMINTRMSK); > + } else { > + pm_ier = I915_READ(GEN6_PMIER); > + pm_imr = I915_READ(GEN6_PMIMR); > + pm_isr = I915_READ(GEN6_PMISR); > + pm_iir = I915_READ(GEN6_PMIIR); > } > + pm_mask = I915_READ(GEN6_PMINTRMSK); > + > seq_printf(m, "Video Turbo Mode: %s\n", > yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > seq_printf(m, "HW control enabled: %s\n", > @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file > *m, void *unused) > seq_printf(m, "SW control enabled: %s\n", > yesno((rpmodectl & > GEN6_RP_MEDIA_MODE_MASK) == > GEN6_RP_MEDIA_SW_MODE)); > - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x > IIR=0x%08x, MASK=0x%08x\n", > - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); > + > + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, > MASK=0x%08x\n", > + pm_ier, pm_imr, pm_mask); > + if (INTEL_GEN(dev_priv) < 11) { > + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", > + pm_isr, pm_iir); > + } > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", > gt_perf_status); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > b/drivers/gpu/drm/i915/i915_gpu_error.c > index b98cd44..d9f2f69 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct > i915_gpu_state *error) > } > > /* 4: Everything else */ > - if (INTEL_GEN(dev_priv) >= 8) { > + if (INTEL_GEN(dev_priv) >= 11) { > + error->ier = I915_READ(GEN8_DE_MISC_IER); > + error->gtier[0] = > I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); > + error->gtier[1] = > I915_READ(GEN11_VCS_VECS_INTR_ENABLE); > + error->gtier[2] = > I915_READ(GEN11_GUC_SG_INTR_ENABLE); > + error->gtier[3] = > I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > + error->gtier[4] = > I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); > + error->gtier[5] = > I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); > + error->ngtier = 6; > + } else if (INTEL_GEN(dev_priv) >= 8) { > error->ier = I915_READ(GEN8_DE_MISC_IER); > for (i = 0; i < 4; i++) > error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h > b/drivers/gpu/drm/i915/i915_gpu_error.h > index dac0f8c..58910f1 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.h > +++ b/drivers/gpu/drm/i915/i915_gpu_error.h > @@ -58,7 +58,7 @@ struct i915_gpu_state { > u32 eir; > u32 pgtbl_er; > u32 ier; > - u32 gtier[4], ngtier; > + u32 gtier[6], ngtier; > u32 ccid; > u32 derrmr; > u32 forcewake; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-16 23:39 ` Paulo Zanoni @ 2018-05-17 16:55 ` Michel Thierry 2018-05-17 17:04 ` Oscar Mateo Lozano 0 siblings, 1 reply; 11+ messages in thread From: Michel Thierry @ 2018-05-17 16:55 UTC (permalink / raw) To: Paulo Zanoni, Mateo Lozano, Oscar, intel-gfx@lists.freedesktop.org On 5/16/2018 4:39 PM, Paulo Zanoni wrote: > Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: >> Stop reading some now deprecated interrupt registers in both >> debugfs and error state. Instead, read the new equivalents in the >> Gen11 interrupt repartitioning scheme. >> >> Note that the equivalent to the PM ISR & IIR cannot be read without >> affecting the current state of the system, so I've opted for leaving >> them out. See gen11_service_one_iir() for more info. > > I can't find this function. Did you mean something else? > s/gen11_service_one_iir/gen11_reset_one_iir/ > > >> >> v2: else if !!! (Paulo) >> v3: another else if (Vinay) >> v4: >> - Rebased >> - Renamed patch >> - Improved the ordering of GENs >> - Improved the printing of per-GEN info >> v5: Avoid maybe-unitialized & add comment explaining the lack >> of PM ISR & IIR >> >> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> >> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >> --- >> drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++- >> --------- >> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- >> drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- >> 3 files changed, 35 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >> b/drivers/gpu/drm/i915/i915_debugfs.c >> index d663a9e0..d992dd2 100644 >> --- a/drivers/gpu/drm/i915/i915_debugfs.c >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct >> seq_file *m, void *unused) >> >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >> >> - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { >> - pm_ier = I915_READ(GEN6_PMIER); >> - pm_imr = I915_READ(GEN6_PMIMR); >> - pm_isr = I915_READ(GEN6_PMISR); >> - pm_iir = I915_READ(GEN6_PMIIR); >> - pm_mask = I915_READ(GEN6_PMINTRMSK); >> - } else { >> + if (INTEL_GEN(dev_priv) >= 11) { >> + pm_ier = >> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >> + pm_imr = >> I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); >> + /* >> + * The equivalent to the PM ISR & IIR cannot >> be read >> + * without affecting the current state of >> the system >> + */ >> + pm_isr = 0; >> + pm_iir = 0; >> + } else if (INTEL_GEN(dev_priv) >= 8) { >> pm_ier = I915_READ(GEN8_GT_IER(2)); >> pm_imr = I915_READ(GEN8_GT_IMR(2)); >> pm_isr = I915_READ(GEN8_GT_ISR(2)); >> pm_iir = I915_READ(GEN8_GT_IIR(2)); >> - pm_mask = I915_READ(GEN6_PMINTRMSK); >> + } else { >> + pm_ier = I915_READ(GEN6_PMIER); >> + pm_imr = I915_READ(GEN6_PMIMR); >> + pm_isr = I915_READ(GEN6_PMISR); >> + pm_iir = I915_READ(GEN6_PMIIR); >> } >> + pm_mask = I915_READ(GEN6_PMINTRMSK); >> + >> seq_printf(m, "Video Turbo Mode: %s\n", >> yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); >> seq_printf(m, "HW control enabled: %s\n", >> @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file >> *m, void *unused) >> seq_printf(m, "SW control enabled: %s\n", >> yesno((rpmodectl & >> GEN6_RP_MEDIA_MODE_MASK) == >> GEN6_RP_MEDIA_SW_MODE)); >> - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x >> IIR=0x%08x, MASK=0x%08x\n", >> - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); >> + >> + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, >> MASK=0x%08x\n", >> + pm_ier, pm_imr, pm_mask); >> + if (INTEL_GEN(dev_priv) < 11) { >> + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", >> + pm_isr, pm_iir); >> + } >> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", >> rps->pm_intrmsk_mbz); >> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", >> gt_perf_status); >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c >> b/drivers/gpu/drm/i915/i915_gpu_error.c >> index b98cd44..d9f2f69 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >> @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct >> i915_gpu_state *error) >> } >> >> /* 4: Everything else */ >> - if (INTEL_GEN(dev_priv) >= 8) { >> + if (INTEL_GEN(dev_priv) >= 11) { >> + error->ier = I915_READ(GEN8_DE_MISC_IER); >> + error->gtier[0] = >> I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); >> + error->gtier[1] = >> I915_READ(GEN11_VCS_VECS_INTR_ENABLE); >> + error->gtier[2] = >> I915_READ(GEN11_GUC_SG_INTR_ENABLE); >> + error->gtier[3] = >> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >> + error->gtier[4] = >> I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); >> + error->gtier[5] = >> I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); >> + error->ngtier = 6; >> + } else if (INTEL_GEN(dev_priv) >= 8) { >> error->ier = I915_READ(GEN8_DE_MISC_IER); >> for (i = 0; i < 4; i++) >> error->gtier[i] = I915_READ(GEN8_GT_IER(i)); >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h >> b/drivers/gpu/drm/i915/i915_gpu_error.h >> index dac0f8c..58910f1 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.h >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h >> @@ -58,7 +58,7 @@ struct i915_gpu_state { >> u32 eir; >> u32 pgtbl_er; >> u32 ier; >> - u32 gtier[4], ngtier; >> + u32 gtier[6], ngtier; >> u32 ccid; >> u32 derrmr; >> u32 forcewake; > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-17 16:55 ` Michel Thierry @ 2018-05-17 17:04 ` Oscar Mateo Lozano 2018-05-17 22:59 ` Paulo Zanoni 0 siblings, 1 reply; 11+ messages in thread From: Oscar Mateo Lozano @ 2018-05-17 17:04 UTC (permalink / raw) To: Michel Thierry, Paulo Zanoni, intel-gfx@lists.freedesktop.org On 5/17/2018 9:55 AM, Michel Thierry wrote: > On 5/16/2018 4:39 PM, Paulo Zanoni wrote: >> Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: >>> Stop reading some now deprecated interrupt registers in both >>> debugfs and error state. Instead, read the new equivalents in the >>> Gen11 interrupt repartitioning scheme. >>> >>> Note that the equivalent to the PM ISR & IIR cannot be read without >>> affecting the current state of the system, so I've opted for leaving >>> them out. See gen11_service_one_iir() for more info. >> >> I can't find this function. Did you mean something else? >> > > s/gen11_service_one_iir/gen11_reset_one_iir/ > Yup, that's right. Thanks Michel, I didn't realize this had been renamed in upstream. >> >> >>> >>> v2: else if !!! (Paulo) >>> v3: another else if (Vinay) >>> v4: >>> - Rebased >>> - Renamed patch >>> - Improved the ordering of GENs >>> - Improved the printing of per-GEN info >>> v5: Avoid maybe-unitialized & add comment explaining the lack >>> of PM ISR & IIR >>> >>> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> >>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++- >>> --------- >>> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- >>> drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- >>> 3 files changed, 35 insertions(+), 12 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >>> b/drivers/gpu/drm/i915/i915_debugfs.c >>> index d663a9e0..d992dd2 100644 >>> --- a/drivers/gpu/drm/i915/i915_debugfs.c >>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >>> @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct >>> seq_file *m, void *unused) >>> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >>> - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { >>> - pm_ier = I915_READ(GEN6_PMIER); >>> - pm_imr = I915_READ(GEN6_PMIMR); >>> - pm_isr = I915_READ(GEN6_PMISR); >>> - pm_iir = I915_READ(GEN6_PMIIR); >>> - pm_mask = I915_READ(GEN6_PMINTRMSK); >>> - } else { >>> + if (INTEL_GEN(dev_priv) >= 11) { >>> + pm_ier = >>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >>> + pm_imr = >>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); >>> + /* >>> + * The equivalent to the PM ISR & IIR cannot >>> be read >>> + * without affecting the current state of >>> the system >>> + */ >>> + pm_isr = 0; >>> + pm_iir = 0; >>> + } else if (INTEL_GEN(dev_priv) >= 8) { >>> pm_ier = I915_READ(GEN8_GT_IER(2)); >>> pm_imr = I915_READ(GEN8_GT_IMR(2)); >>> pm_isr = I915_READ(GEN8_GT_ISR(2)); >>> pm_iir = I915_READ(GEN8_GT_IIR(2)); >>> - pm_mask = I915_READ(GEN6_PMINTRMSK); >>> + } else { >>> + pm_ier = I915_READ(GEN6_PMIER); >>> + pm_imr = I915_READ(GEN6_PMIMR); >>> + pm_isr = I915_READ(GEN6_PMISR); >>> + pm_iir = I915_READ(GEN6_PMIIR); >>> } >>> + pm_mask = I915_READ(GEN6_PMINTRMSK); >>> + >>> seq_printf(m, "Video Turbo Mode: %s\n", >>> yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); >>> seq_printf(m, "HW control enabled: %s\n", >>> @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file >>> *m, void *unused) >>> seq_printf(m, "SW control enabled: %s\n", >>> yesno((rpmodectl & >>> GEN6_RP_MEDIA_MODE_MASK) == >>> GEN6_RP_MEDIA_SW_MODE)); >>> - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x >>> IIR=0x%08x, MASK=0x%08x\n", >>> - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); >>> + >>> + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, >>> MASK=0x%08x\n", >>> + pm_ier, pm_imr, pm_mask); >>> + if (INTEL_GEN(dev_priv) < 11) { >>> + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", >>> + pm_isr, pm_iir); >>> + } >>> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", >>> rps->pm_intrmsk_mbz); >>> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", >>> gt_perf_status); >>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c >>> b/drivers/gpu/drm/i915/i915_gpu_error.c >>> index b98cd44..d9f2f69 100644 >>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >>> @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct >>> i915_gpu_state *error) >>> } >>> /* 4: Everything else */ >>> - if (INTEL_GEN(dev_priv) >= 8) { >>> + if (INTEL_GEN(dev_priv) >= 11) { >>> + error->ier = I915_READ(GEN8_DE_MISC_IER); >>> + error->gtier[0] = >>> I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); >>> + error->gtier[1] = >>> I915_READ(GEN11_VCS_VECS_INTR_ENABLE); >>> + error->gtier[2] = >>> I915_READ(GEN11_GUC_SG_INTR_ENABLE); >>> + error->gtier[3] = >>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >>> + error->gtier[4] = >>> I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); >>> + error->gtier[5] = >>> I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); >>> + error->ngtier = 6; >>> + } else if (INTEL_GEN(dev_priv) >= 8) { >>> error->ier = I915_READ(GEN8_DE_MISC_IER); >>> for (i = 0; i < 4; i++) >>> error->gtier[i] = I915_READ(GEN8_GT_IER(i)); >>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h >>> b/drivers/gpu/drm/i915/i915_gpu_error.h >>> index dac0f8c..58910f1 100644 >>> --- a/drivers/gpu/drm/i915/i915_gpu_error.h >>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h >>> @@ -58,7 +58,7 @@ struct i915_gpu_state { >>> u32 eir; >>> u32 pgtbl_er; >>> u32 ier; >>> - u32 gtier[4], ngtier; >>> + u32 gtier[6], ngtier; >>> u32 ccid; >>> u32 derrmr; >>> u32 forcewake; >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-17 17:04 ` Oscar Mateo Lozano @ 2018-05-17 22:59 ` Paulo Zanoni 2018-05-18 22:05 ` Oscar Mateo Lozano 0 siblings, 1 reply; 11+ messages in thread From: Paulo Zanoni @ 2018-05-17 22:59 UTC (permalink / raw) To: Oscar Mateo Lozano, Michel Thierry, intel-gfx@lists.freedesktop.org Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu: > > On 5/17/2018 9:55 AM, Michel Thierry wrote: > > On 5/16/2018 4:39 PM, Paulo Zanoni wrote: > > > Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: > > > > Stop reading some now deprecated interrupt registers in both > > > > debugfs and error state. Instead, read the new equivalents in > > > > the > > > > Gen11 interrupt repartitioning scheme. > > > > > > > > Note that the equivalent to the PM ISR & IIR cannot be read > > > > without > > > > affecting the current state of the system, so I've opted for > > > > leaving > > > > them out. See gen11_service_one_iir() for more info. > > > > > > I can't find this function. Did you mean something else? > > > > > > > s/gen11_service_one_iir/gen11_reset_one_iir/ > > > > Yup, that's right. Thanks Michel, I didn't realize this had been > renamed > in upstream. I fixed this in the commit message, did a small bikeshed on the single- if-with-braces and merged the patch. I downloaded your patch through patchwork and it changed your name (patch author) from "Oscar Mateo" to "Oscar Mateo Lozano" (then dim push-queued complained the patch was missing author Signed-off-by due to the name difference, which made me notice it). You may want to either fix your name in patchwork so it appears as "Oscar Mateo" or change your git configuration to add the missing name. Thanks for the patch and reviews. Thanks, Paulo > > > > > > > > > > > > > > > v2: else if !!! (Paulo) > > > > v3: another else if (Vinay) > > > > v4: > > > > - Rebased > > > > - Renamed patch > > > > - Improved the ordering of GENs > > > > - Improved the printing of per-GEN info > > > > v5: Avoid maybe-unitialized & add comment explaining the lack > > > > of PM ISR & IIR > > > > > > > > Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > > > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> > > > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_debugfs.c | 34 > > > > ++++++++++++++++++++++++- > > > > --------- > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- > > > > drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- > > > > 3 files changed, 35 insertions(+), 12 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > > > b/drivers/gpu/drm/i915/i915_debugfs.c > > > > index d663a9e0..d992dd2 100644 > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > > @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct > > > > seq_file *m, void *unused) > > > > intel_uncore_forcewake_put(dev_priv, > > > > FORCEWAKE_ALL); > > > > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { > > > > - pm_ier = I915_READ(GEN6_PMIER); > > > > - pm_imr = I915_READ(GEN6_PMIMR); > > > > - pm_isr = I915_READ(GEN6_PMISR); > > > > - pm_iir = I915_READ(GEN6_PMIIR); > > > > - pm_mask = I915_READ(GEN6_PMINTRMSK); > > > > - } else { > > > > + if (INTEL_GEN(dev_priv) >= 11) { > > > > + pm_ier = > > > > I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > > > > + pm_imr = > > > > I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); > > > > + /* > > > > + * The equivalent to the PM ISR & IIR cannot > > > > be read > > > > + * without affecting the current state of > > > > the system > > > > + */ > > > > + pm_isr = 0; > > > > + pm_iir = 0; > > > > + } else if (INTEL_GEN(dev_priv) >= 8) { > > > > pm_ier = I915_READ(GEN8_GT_IER(2)); > > > > pm_imr = I915_READ(GEN8_GT_IMR(2)); > > > > pm_isr = I915_READ(GEN8_GT_ISR(2)); > > > > pm_iir = I915_READ(GEN8_GT_IIR(2)); > > > > - pm_mask = I915_READ(GEN6_PMINTRMSK); > > > > + } else { > > > > + pm_ier = I915_READ(GEN6_PMIER); > > > > + pm_imr = I915_READ(GEN6_PMIMR); > > > > + pm_isr = I915_READ(GEN6_PMISR); > > > > + pm_iir = I915_READ(GEN6_PMIIR); > > > > } > > > > + pm_mask = I915_READ(GEN6_PMINTRMSK); > > > > + > > > > seq_printf(m, "Video Turbo Mode: %s\n", > > > > yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > > > > seq_printf(m, "HW control enabled: %s\n", > > > > @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct > > > > seq_file > > > > *m, void *unused) > > > > seq_printf(m, "SW control enabled: %s\n", > > > > yesno((rpmodectl & > > > > GEN6_RP_MEDIA_MODE_MASK) == > > > > GEN6_RP_MEDIA_SW_MODE)); > > > > - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x > > > > IIR=0x%08x, MASK=0x%08x\n", > > > > - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); > > > > + > > > > + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, > > > > MASK=0x%08x\n", > > > > + pm_ier, pm_imr, pm_mask); > > > > + if (INTEL_GEN(dev_priv) < 11) { > > > > + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", > > > > + pm_isr, pm_iir); > > > > + } > > > > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", > > > > rps->pm_intrmsk_mbz); > > > > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", > > > > gt_perf_status); > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > index b98cd44..d9f2f69 100644 > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct > > > > i915_gpu_state *error) > > > > } > > > > /* 4: Everything else */ > > > > - if (INTEL_GEN(dev_priv) >= 8) { > > > > + if (INTEL_GEN(dev_priv) >= 11) { > > > > + error->ier = I915_READ(GEN8_DE_MISC_IER); > > > > + error->gtier[0] = > > > > I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); > > > > + error->gtier[1] = > > > > I915_READ(GEN11_VCS_VECS_INTR_ENABLE); > > > > + error->gtier[2] = > > > > I915_READ(GEN11_GUC_SG_INTR_ENABLE); > > > > + error->gtier[3] = > > > > I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); > > > > + error->gtier[4] = > > > > I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); > > > > + error->gtier[5] = > > > > I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); > > > > + error->ngtier = 6; > > > > + } else if (INTEL_GEN(dev_priv) >= 8) { > > > > error->ier = I915_READ(GEN8_DE_MISC_IER); > > > > for (i = 0; i < 4; i++) > > > > error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h > > > > b/drivers/gpu/drm/i915/i915_gpu_error.h > > > > index dac0f8c..58910f1 100644 > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.h > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.h > > > > @@ -58,7 +58,7 @@ struct i915_gpu_state { > > > > u32 eir; > > > > u32 pgtbl_er; > > > > u32 ier; > > > > - u32 gtier[4], ngtier; > > > > + u32 gtier[6], ngtier; > > > > u32 ccid; > > > > u32 derrmr; > > > > u32 forcewake; > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers 2018-05-17 22:59 ` Paulo Zanoni @ 2018-05-18 22:05 ` Oscar Mateo Lozano 0 siblings, 0 replies; 11+ messages in thread From: Oscar Mateo Lozano @ 2018-05-18 22:05 UTC (permalink / raw) To: Paulo Zanoni, Michel Thierry, intel-gfx@lists.freedesktop.org On 5/17/2018 3:59 PM, Paulo Zanoni wrote: > Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu: >> On 5/17/2018 9:55 AM, Michel Thierry wrote: >>> On 5/16/2018 4:39 PM, Paulo Zanoni wrote: >>>> Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: >>>>> Stop reading some now deprecated interrupt registers in both >>>>> debugfs and error state. Instead, read the new equivalents in >>>>> the >>>>> Gen11 interrupt repartitioning scheme. >>>>> >>>>> Note that the equivalent to the PM ISR & IIR cannot be read >>>>> without >>>>> affecting the current state of the system, so I've opted for >>>>> leaving >>>>> them out. See gen11_service_one_iir() for more info. >>>> I can't find this function. Did you mean something else? >>>> >>> s/gen11_service_one_iir/gen11_reset_one_iir/ >>> >> Yup, that's right. Thanks Michel, I didn't realize this had been >> renamed >> in upstream. > I fixed this in the commit message, did a small bikeshed on the single- > if-with-braces and merged the patch. Thanks Paulo. > I downloaded your patch through patchwork and it changed your name > (patch author) from "Oscar Mateo" to "Oscar Mateo Lozano" (then dim > push-queued complained the patch was missing author Signed-off-by due > to the name difference, which made me notice it). You may want to > either fix your name in patchwork so it appears as "Oscar Mateo" or > change your git configuration to add the missing name. Sorry about that, it seems I registered with my two surnames instead of the first one that I usually employ. Is it possible to change the name in patchwork? I don't see a way. Do you know if anybody has direct access to the database? > Thanks for the patch and reviews. > > Thanks, > Paulo > >>>> >>>>> v2: else if !!! (Paulo) >>>>> v3: another else if (Vinay) >>>>> v4: >>>>> - Rebased >>>>> - Renamed patch >>>>> - Improved the ordering of GENs >>>>> - Improved the printing of per-GEN info >>>>> v5: Avoid maybe-unitialized & add comment explaining the lack >>>>> of PM ISR & IIR >>>>> >>>>> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >>>>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> >>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >>>>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> >>>>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >>>>> --- >>>>> drivers/gpu/drm/i915/i915_debugfs.c | 34 >>>>> ++++++++++++++++++++++++- >>>>> --------- >>>>> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++++++++- >>>>> drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- >>>>> 3 files changed, 35 insertions(+), 12 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >>>>> b/drivers/gpu/drm/i915/i915_debugfs.c >>>>> index d663a9e0..d992dd2 100644 >>>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c >>>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >>>>> @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct >>>>> seq_file *m, void *unused) >>>>> intel_uncore_forcewake_put(dev_priv, >>>>> FORCEWAKE_ALL); >>>>> - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { >>>>> - pm_ier = I915_READ(GEN6_PMIER); >>>>> - pm_imr = I915_READ(GEN6_PMIMR); >>>>> - pm_isr = I915_READ(GEN6_PMISR); >>>>> - pm_iir = I915_READ(GEN6_PMIIR); >>>>> - pm_mask = I915_READ(GEN6_PMINTRMSK); >>>>> - } else { >>>>> + if (INTEL_GEN(dev_priv) >= 11) { >>>>> + pm_ier = >>>>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >>>>> + pm_imr = >>>>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); >>>>> + /* >>>>> + * The equivalent to the PM ISR & IIR cannot >>>>> be read >>>>> + * without affecting the current state of >>>>> the system >>>>> + */ >>>>> + pm_isr = 0; >>>>> + pm_iir = 0; >>>>> + } else if (INTEL_GEN(dev_priv) >= 8) { >>>>> pm_ier = I915_READ(GEN8_GT_IER(2)); >>>>> pm_imr = I915_READ(GEN8_GT_IMR(2)); >>>>> pm_isr = I915_READ(GEN8_GT_ISR(2)); >>>>> pm_iir = I915_READ(GEN8_GT_IIR(2)); >>>>> - pm_mask = I915_READ(GEN6_PMINTRMSK); >>>>> + } else { >>>>> + pm_ier = I915_READ(GEN6_PMIER); >>>>> + pm_imr = I915_READ(GEN6_PMIMR); >>>>> + pm_isr = I915_READ(GEN6_PMISR); >>>>> + pm_iir = I915_READ(GEN6_PMIIR); >>>>> } >>>>> + pm_mask = I915_READ(GEN6_PMINTRMSK); >>>>> + >>>>> seq_printf(m, "Video Turbo Mode: %s\n", >>>>> yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); >>>>> seq_printf(m, "HW control enabled: %s\n", >>>>> @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct >>>>> seq_file >>>>> *m, void *unused) >>>>> seq_printf(m, "SW control enabled: %s\n", >>>>> yesno((rpmodectl & >>>>> GEN6_RP_MEDIA_MODE_MASK) == >>>>> GEN6_RP_MEDIA_SW_MODE)); >>>>> - seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x >>>>> IIR=0x%08x, MASK=0x%08x\n", >>>>> - pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); >>>>> + >>>>> + seq_printf(m, "PM IER=0x%08x IMR=0x%08x, >>>>> MASK=0x%08x\n", >>>>> + pm_ier, pm_imr, pm_mask); >>>>> + if (INTEL_GEN(dev_priv) < 11) { >>>>> + seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", >>>>> + pm_isr, pm_iir); >>>>> + } >>>>> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", >>>>> rps->pm_intrmsk_mbz); >>>>> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", >>>>> gt_perf_status); >>>>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c >>>>> b/drivers/gpu/drm/i915/i915_gpu_error.c >>>>> index b98cd44..d9f2f69 100644 >>>>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >>>>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >>>>> @@ -1675,7 +1675,16 @@ static void capture_reg_state(struct >>>>> i915_gpu_state *error) >>>>> } >>>>> /* 4: Everything else */ >>>>> - if (INTEL_GEN(dev_priv) >= 8) { >>>>> + if (INTEL_GEN(dev_priv) >= 11) { >>>>> + error->ier = I915_READ(GEN8_DE_MISC_IER); >>>>> + error->gtier[0] = >>>>> I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); >>>>> + error->gtier[1] = >>>>> I915_READ(GEN11_VCS_VECS_INTR_ENABLE); >>>>> + error->gtier[2] = >>>>> I915_READ(GEN11_GUC_SG_INTR_ENABLE); >>>>> + error->gtier[3] = >>>>> I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); >>>>> + error->gtier[4] = >>>>> I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); >>>>> + error->gtier[5] = >>>>> I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); >>>>> + error->ngtier = 6; >>>>> + } else if (INTEL_GEN(dev_priv) >= 8) { >>>>> error->ier = I915_READ(GEN8_DE_MISC_IER); >>>>> for (i = 0; i < 4; i++) >>>>> error->gtier[i] = I915_READ(GEN8_GT_IER(i)); >>>>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h >>>>> b/drivers/gpu/drm/i915/i915_gpu_error.h >>>>> index dac0f8c..58910f1 100644 >>>>> --- a/drivers/gpu/drm/i915/i915_gpu_error.h >>>>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h >>>>> @@ -58,7 +58,7 @@ struct i915_gpu_state { >>>>> u32 eir; >>>>> u32 pgtbl_er; >>>>> u32 ier; >>>>> - u32 gtier[4], ngtier; >>>>> + u32 gtier[6], ngtier; >>>>> u32 ccid; >>>>> u32 derrmr; >>>>> u32 forcewake; >>>> _______________________________________________ >>>> Intel-gfx mailing list >>>> Intel-gfx@lists.freedesktop.org >>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >>>> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) 2018-05-10 21:23 [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers Oscar Mateo 2018-05-10 21:33 ` ✗ Fi.CI.BAT: failure for " Patchwork 2018-05-10 21:59 ` [PATCH] " Oscar Mateo @ 2018-05-10 22:42 ` Patchwork 2018-05-10 23:49 ` ✓ Fi.CI.IGT: " Patchwork 3 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2018-05-10 22:42 UTC (permalink / raw) To: Oscar Mateo; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) URL : https://patchwork.freedesktop.org/series/43027/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4164 -> Patchwork_8977 = == Summary - WARNING == Minor unknown changes coming with Patchwork_8977 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_8977, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/43027/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_8977: === IGT changes === ==== Warnings ==== igt@gem_exec_gttfill@basic: fi-pnv-d510: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_8977 that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: PASS -> FAIL (fdo#103841) ==== Possible fixes ==== igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 == Participating hosts (40 -> 37) == Additional (1): fi-byt-j1900 Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4164 -> Patchwork_8977 CI_DRM_4164: a44969bdb6d69244a063eac7f76ea46353960409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4475: 35f08c12aa216d5b62a5b9984b575cee6905098f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_8977: fe3ca93631ddf6a4be3cd9753bb083ace33dbf26 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4475: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit == Linux commits == fe3ca93631dd drm/i915/icl: Read the correct Gen11 interrupt registers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8977/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) 2018-05-10 21:23 [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers Oscar Mateo ` (2 preceding siblings ...) 2018-05-10 22:42 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) Patchwork @ 2018-05-10 23:49 ` Patchwork 3 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2018-05-10 23:49 UTC (permalink / raw) To: Oscar Mateo; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) URL : https://patchwork.freedesktop.org/series/43027/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4164_full -> Patchwork_8977_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8977_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_8977_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/43027/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_8977_full: === IGT changes === ==== Warnings ==== igt@gem_exec_schedule@deep-bsd1: shard-kbl: PASS -> SKIP igt@gem_pwrite@big-cpu-random: shard-apl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_8977_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105707) igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render: shard-apl: PASS -> FAIL (fdo#104724, fdo#103167) igt@kms_plane@plane-panning-top-left-pipe-c-planes: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +9 ==== Possible fixes ==== igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt: shard-hsw: DMESG-FAIL (fdo#104724, fdo#103167) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707 == Participating hosts (9 -> 9) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4164 -> Patchwork_8977 CI_DRM_4164: a44969bdb6d69244a063eac7f76ea46353960409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4475: 35f08c12aa216d5b62a5b9984b575cee6905098f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_8977: fe3ca93631ddf6a4be3cd9753bb083ace33dbf26 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4475: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8977/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-05-18 22:05 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-05-10 21:23 [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers Oscar Mateo 2018-05-10 21:33 ` ✗ Fi.CI.BAT: failure for " Patchwork 2018-05-10 21:59 ` [PATCH] " Oscar Mateo 2018-05-11 17:06 ` Vinay Belgaumkar 2018-05-16 23:39 ` Paulo Zanoni 2018-05-17 16:55 ` Michel Thierry 2018-05-17 17:04 ` Oscar Mateo Lozano 2018-05-17 22:59 ` Paulo Zanoni 2018-05-18 22:05 ` Oscar Mateo Lozano 2018-05-10 22:42 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Read the correct Gen11 interrupt registers (rev2) Patchwork 2018-05-10 23:49 ` ✓ Fi.CI.IGT: " Patchwork
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