* [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-16 10:13 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs Marek Vasut
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
Sort the Makefile entries, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/dts/Makefile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f94940a7dd..b29ecb0060 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -182,20 +182,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
- socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
- socfpga_cyclone5_de0_nano_soc.dtb \
+ socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_de10_nano.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
- socfpga_stratix10_socdk.dtb \
- socfpga_cyclone5_vining_fpga.dtb
+ socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile
2018-05-12 20:30 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Marek Vasut
@ 2018-05-16 10:13 ` Ley Foon Tan
0 siblings, 0 replies; 25+ messages in thread
From: Ley Foon Tan @ 2018-05-16 10:13 UTC (permalink / raw)
To: u-boot
On Sun, May 13, 2018 at 4:30 AM, Marek Vasut <marex@denx.de> wrote:
> Sort the Makefile entries, no functional change.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/dts/Makefile | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index f94940a7dd..b29ecb0060 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -182,20 +182,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
> dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
>
> dtb-$(CONFIG_ARCH_SOCFPGA) += \
> - socfpga_arria10_socdk_sdmmc.dtb \
> socfpga_arria5_socdk.dtb \
> + socfpga_arria10_socdk_sdmmc.dtb \
> socfpga_cyclone5_is1.dtb \
> socfpga_cyclone5_mcvevk.dtb \
> socfpga_cyclone5_socdk.dtb \
> socfpga_cyclone5_dbm_soc1.dtb \
> - socfpga_cyclone5_de0_nano_soc.dtb \
> + socfpga_cyclone5_de0_nano_soc.dtb \
> socfpga_cyclone5_de1_soc.dtb \
> socfpga_cyclone5_de10_nano.dtb \
> socfpga_cyclone5_sockit.dtb \
> socfpga_cyclone5_socrates.dtb \
> socfpga_cyclone5_sr1500.dtb \
> - socfpga_stratix10_socdk.dtb \
> - socfpga_cyclone5_vining_fpga.dtb
> + socfpga_cyclone5_vining_fpga.dtb \
> + socfpga_stratix10_socdk.dtb
>
> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
> --
> 2.16.2
>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff Marek Vasut
` (9 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit
ef8216d28a5920022cddcb694d2d75bd1f0035ca
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/dts/socfpga_arria10.dtsi | 594 +++++++++++++--------------
arch/arm/dts/socfpga_arria10_socdk.dtsi | 167 ++++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 45 +-
3 files changed, 482 insertions(+), 324 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk.dtsi
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index abfd0bc4f8..b51febda9c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
@@ -14,7 +14,6 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/altr,rst-mgr-a10.h>
@@ -22,29 +21,10 @@
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-a10-smp";
cpu at 0 {
compatible = "arm,cortex-a9";
@@ -102,321 +82,335 @@
};
};
- clkmgr at ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
- reg-names = "soc_clock_manager_OCP_SLV";
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- cb_intosc_ls_clk: cb_intosc_ls_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
- f2s_free_clk: f2s_free_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
- osc1: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ clkmgr at ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
- main_pll: main_pll {
+ clocks {
#address-cells = <1>;
#size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>;
- reg = <0x40>;
- main_mpu_base_clk: main_mpu_base_clk {
+ cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x140 0 11>;
+ compatible = "fixed-clock";
};
- main_noc_base_clk: main_noc_base_clk {
+ cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x144 0 11>;
+ compatible = "fixed-clock";
};
- main_emaca_clk: main_emaca_clk {
+ f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x68>;
+ compatible = "fixed-clock";
};
- main_emacb_clk: main_emacb_clk {
+ osc1: osc1 {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x6C>;
+ compatible = "fixed-clock";
};
- main_emac_ptp_clk: main_emac_ptp_clk {
+ main_pll: main_pll at 40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x70>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>;
+ reg = <0x40>;
+
+ main_mpu_base_clk: main_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x140 0 11>;
+ };
+
+ main_noc_base_clk: main_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x144 0 11>;
+ };
+
+ main_emaca_clk: main_emaca_clk at 68 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x68>;
+ };
+
+ main_emacb_clk: main_emacb_clk at 6c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x6C>;
+ };
+
+ main_emac_ptp_clk: main_emac_ptp_clk at 70 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x70>;
+ };
+
+ main_gpio_db_clk: main_gpio_db_clk at 74 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x74>;
+ };
+
+ main_sdmmc_clk: main_sdmmc_clk at 78 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk"
+;
+ clocks = <&main_pll>;
+ reg = <0x78>;
+ };
+
+ main_s2f_usr0_clk: main_s2f_usr0_clk at 7c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x7C>;
+ };
+
+ main_s2f_usr1_clk: main_s2f_usr1_clk at 80 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x80>;
+ };
+
+ main_hmc_pll_ref_clk: main_hmc_pll_ref_clk at 84 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x84>;
+ };
+
+ main_periph_ref_clk: main_periph_ref_clk at 9c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x9C>;
+ };
};
- main_gpio_db_clk: main_gpio_db_clk {
+ periph_pll: periph_pll at c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x74>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>, <&main_periph_ref_clk>;
+ reg = <0xC0>;
+
+ peri_mpu_base_clk: peri_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x140 16 11>;
+ };
+
+ peri_noc_base_clk: peri_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x144 16 11>;
+ };
+
+ peri_emaca_clk: peri_emaca_clk at e8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xE8>;
+ };
+
+ peri_emacb_clk: peri_emacb_clk at ec {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xEC>;
+ };
+
+ peri_emac_ptp_clk: peri_emac_ptp_clk at f0 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF0>;
+ };
+
+ peri_gpio_db_clk: peri_gpio_db_clk at f4 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF4>;
+ };
+
+ peri_sdmmc_clk: peri_sdmmc_clk at f8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF8>;
+ };
+
+ peri_s2f_usr0_clk: peri_s2f_usr0_clk at fc {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xFC>;
+ };
+
+ peri_s2f_usr1_clk: peri_s2f_usr1_clk at 100 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x100>;
+ };
+
+ peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk at 104 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x104>;
+ };
};
- main_sdmmc_clk: main_sdmmc_clk {
+ mpu_free_clk: mpu_free_clk at 60 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x78>;
+ clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x60>;
};
- main_s2f_usr0_clk: main_s2f_usr0_clk {
+ noc_free_clk: noc_free_clk at 64 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x7C>;
+ clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x64>;
};
- main_s2f_usr1_clk: main_s2f_usr1_clk {
+ s2f_user1_free_clk: s2f_user1_free_clk at 104 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x80>;
+ clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x104>;
};
- main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+ sdmmc_free_clk: sdmmc_free_clk at f8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x84>;
+ clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ fixed-divider = <4>;
+ reg = <0xF8>;
};
- main_periph_ref_clk: main_periph_ref_clk {
+ l4_sys_free_clk: l4_sys_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x9C>;
+ clocks = <&noc_free_clk>;
+ fixed-divider = <4>;
};
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>, <&main_periph_ref_clk>;
- reg = <0xC0>;
- peri_mpu_base_clk: peri_mpu_base_clk {
+ l4_main_clk: l4_main_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x140 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 0 2>;
+ clk-gate = <0x48 1>;
};
- peri_noc_base_clk: peri_noc_base_clk {
+ l4_mp_clk: l4_mp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x144 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 8 2>;
+ clk-gate = <0x48 2>;
};
- peri_emaca_clk: peri_emaca_clk {
+ l4_sp_clk: l4_sp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xE8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 16 2>;
+ clk-gate = <0x48 3>;
};
- peri_emacb_clk: peri_emacb_clk {
+ mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xEC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&mpu_free_clk>;
+ fixed-divider = <4>;
+ clk-gate = <0x48 0>;
};
- peri_emac_ptp_clk: peri_emac_ptp_clk {
+ sdmmc_clk: sdmmc_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&sdmmc_free_clk>;
+ clk-gate = <0xC8 5>;
+ clk-phase = <0 135>;
};
- peri_gpio_db_clk: peri_gpio_db_clk {
+ qspi_clk: qspi_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF4>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 11>;
};
- peri_sdmmc_clk: peri_sdmmc_clk {
+ nand_clk: nand_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 10>;
};
- peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+ spi_m_clk: spi_m_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xFC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 9>;
};
- peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+ usb_clk: usb_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x100>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 8>;
};
- peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+ s2f_usr1_clk: s2f_usr1_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x104>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&peri_s2f_usr1_clk>;
+ clk-gate = <0xC8 6>;
};
};
+ };
- mpu_free_clk: mpu_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x60>;
- };
-
- noc_free_clk: noc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x64>;
- };
-
- s2f_user1_free_clk: s2f_user1_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x104>;
- };
-
- sdmmc_free_clk: sdmmc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- fixed-divider = <4>;
- reg = <0xF8>;
- };
-
- l4_sys_free_clk: l4_sys_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&noc_free_clk>;
- fixed-divider = <4>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 0 2>;
- clk-gate = <0x48 1>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 8 2>;
- clk-gate = <0x48 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 16 2>;
- clk-gate = <0x48 3>;
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&mpu_free_clk>;
- fixed-divider = <4>;
- clk-gate = <0x48 0>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&sdmmc_free_clk>;
- clk-gate = <0xC8 5>;
- clk-phase = <0 135>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 11>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 10>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 9>;
- };
-
- usb_clk: usb_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 8>;
- };
-
- s2f_usr1_clk: s2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&peri_s2f_usr1_clk>;
- clk-gate = <0xC8 6>;
- };
- };
+ socfpga_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 0 0>;
};
gmac0: ethernet at ff800000 {
@@ -435,6 +429,7 @@
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -454,6 +449,7 @@
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -471,6 +467,7 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -483,6 +480,7 @@
porta: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -502,6 +500,7 @@
portb: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -521,6 +520,7 @@
portc: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
@@ -590,37 +590,24 @@
status = "disabled";
};
- sdr: sdr at 0xffcfb100 {
- compatible = "syscon";
- reg = <0xffcfb100 0x80>;
- };
-
- spi0: spi at ffda4000 {
+ spi1: spi at ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xffda4000 0x100>;
- interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xffda5000 0x100>;
+ interrupts = <0 102 4>;
num-chipselect = <4>;
bus-num = <0>;
+ /*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
clocks = <&spi_m_clk>;
status = "disabled";
};
- spi1: spi at ffda5000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xffda5000 0x100>;
- interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
- num-chipselect = <4>;
- bus-num = <0>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&spi_m_clk>;
- status = "disabled";
+ sdr: sdr at ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffcfb100 0x80>;
};
L2: l2-cache at fffff000 {
@@ -629,6 +616,9 @@
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0 at ff808000 {
@@ -638,18 +628,30 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
- bus-width = <4>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
status = "disabled";
};
+ nand: nand at ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 99 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ status = "disabled";
+ };
+
ocram: sram at ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
};
- eccmgr: eccmgr at ffd06000 {
+ eccmgr: eccmgr {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
@@ -681,16 +683,6 @@
<33 IRQ_TYPE_LEVEL_HIGH>;
};
- sdmmca-ecc at ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
emac0-rx-ecc at ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
@@ -724,19 +716,17 @@
};
};
- qspi: qspi at ff809000 {
+ qspi: spi at ff809000 {
+ compatible = "cdns,qspi-nor", "cadence,qspi";
#address-cells = <1>;
#size-cells = <0>;
- compatible = "cadence,qspi";
reg = <0xff809000 0x100>,
- <0xffa00000 0x100000>;
+ <0xffa00000 0x100000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&l4_main_clk>;
- ext-decoder = <0>; /* external decoder */
- num-chipselect = <4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
- bus-num = <2>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
@@ -818,7 +808,7 @@
status = "disabled";
};
- usbphy0: usbphy at 0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
new file mode 100644
index 0000000000..d7616dd1c5
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria 10";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ a10leds {
+ compatible = "gpio-leds";
+
+ a10sr_led0 {
+ label = "a10sr-led0";
+ gpios = <&a10sr_gpio 0 1>;
+ };
+
+ a10sr_led1 {
+ label = "a10sr-led1";
+ gpios = <&a10sr_gpio 1 1>;
+ };
+
+ a10sr_led2 {
+ label = "a10sr-led2";
+ gpios = <&a10sr_gpio 2 1>;
+ };
+
+ a10sr_led3 {
+ label = "a10sr-led3";
+ gpios = <&a10sr_gpio 3 1>;
+ };
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+
+ /*
+ * These skews assume the user's FPGA design is adding 600ps of delay
+ * for TX_CLK on Arria 10.
+ *
+ * All skews are offset since hardware skew values for the ksz9031
+ * range from a negative skew to a positive skew.
+ * See the micrel-ksz90x1.txt Documentation file for details.
+ */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ resource-manager at 0 {
+ compatible = "altr,a10sr";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ /* low-level active IRQ at GPIO1_5 */
+ interrupt-parent = <&portb>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ a10sr_gpio: gpio-controller {
+ compatible = "altr,a10sr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ a10sr_rst: reset-controller {
+ compatible = "altr,a10sr-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ clock-frequency = <100000>;
+ i2c-sda-falling-time-ns = <6000>;
+ i2c-scl-falling-time-ns = <6000>;
+
+ eeprom at 51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+
+ ltc at 5c {
+ compatible = "ltc2977";
+ reg = <0x5c>;
+ };
+};
+
+&uart1 {
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 06b61cb0af..9c6070ded9 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -1,33 +1,22 @@
/*
- * Copyright (C) 2015-2017 Altera Corporation. All rights reserved.
+ * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200";
- };
-};
-
-&uart1 {
- clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
- status = "okay";
-};
+#include "socfpga_arria10_socdk.dtsi"
&mmc {
u-boot,dm-pre-reloc;
@@ -37,3 +26,15 @@
broken-cd;
bus-width = <4>;
};
+
+&eccmgr {
+ sdmmca-ecc at ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
` (8 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest
Quartus to get the new set of clock bindings in.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
.../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 734 +++++++++------------
1 file changed, 302 insertions(+), 432 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index b6939b011a..39009654d9 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -14,467 +14,337 @@
#include "socfpga_arria10.dtsi"
/ {
- model = "Altera SOCFPGA Arria 10";
- compatible = "altr,socfpga-arria10", "altr,socfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
- /* Bootloader setting: uboot.rbf_filename */
- cff-file = "ghrd_10as066n2.periph.rbf";
- early-release-fpga-config;
+ cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
};
- soc {
+ /* Clock sources */
+ clocks {
u-boot,dm-pre-reloc;
- clkmgr at ffd04000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Clock source: altera_arria10_hps_eosc1 */
+ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "altera_arria10_hps_eosc1-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_cb_intosc_ls */
+ altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_f2h_free */
+ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "altera_arria10_hps_f2h_free-clk";
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_clk_mgr: clock_manager at 0xffd04000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-clk-init";
+ reg = <0xffd04000 0x00000200>;
+ reg-names = "soc_clock_manager_OCP_SLV";
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
+ mainpll {
u-boot,dm-pre-reloc;
- clocks {
- u-boot,dm-pre-reloc;
- osc1 {
- u-boot,dm-pre-reloc;
- clock-frequency = <25000000>;
- clock-output-names = "altera_arria10_hps_eosc1-clk";
- };
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <191>; /* Field: vco1.numer */
+ mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
+ mpuclk-src = <0>; /* Field: mpuclk.src */
+ nocclk-cnt = <0>; /* Field: nocclk.cnt */
+ nocclk-src = <0>; /* Field: nocclk.src */
+ cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
+ cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
+ cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr7clk-src = <0>; /* Field: cntr7clk.src */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ cntr9clk-src = <0>; /* Field: cntr9clk.src */
+ cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
+ nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
+ nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
+ nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
+ nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
+ nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
+ nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
+ };
- cb_intosc_ls_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <60000000>;
- clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
+ perpll {
+ u-boot,dm-pre-reloc;
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <159>; /* Field: vco1.numer */
+ cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
+ cntr2clk-src = <1>; /* Field: cntr2clk.src */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr3clk-src = <1>; /* Field: cntr3clk.src */
+ cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
+ cntr4clk-src = <1>; /* Field: cntr4clk.src */
+ cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
+ cntr5clk-src = <1>; /* Field: cntr5clk.src */
+ cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
+ cntr6clk-src = <1>; /* Field: cntr6clk.src */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr8clk-src = <0>; /* Field: cntr8clk.src */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
+ emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
+ emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
+ gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
+ };
- f2s_free_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <200000000>;
- clock-output-names = "altera_arria10_hps_f2h_free-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ nocclk = <0x0384000b>; /* Register: nocclk */
+ mpuclk = <0x03840001>; /* Register: mpuclk */
+ };
+ };
- main_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_mainpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 191 /* Field: vco1.numer */
- 0 /* Field: mpuclk */
- 0 /* Field: mpuclk.cnt */
- 0 /* Field: mpuclk.src */
- 0 /* Field: nocclk */
- 0 /* Field: nocclk.cnt */
- 0 /* Field: nocclk.src */
- 900 /* Field: cntr2clk.cnt */
- 900 /* Field: cntr3clk.cnt */
- 900 /* Field: cntr4clk.cnt */
- 900 /* Field: cntr5clk.cnt */
- 900 /* Field: cntr6clk.cnt */
- 900 /* Field: cntr7clk.cnt */
- 0 /* Field: cntr7clk.src */
- 900 /* Field: cntr8clk.cnt */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: cntr9clk.src */
- 900 /* Field: cntr15clk.cnt */
- 0 /* Field: nocdiv.l4mainclk */
- 0 /* Field: nocdiv.l4mpclk */
- 2 /* Field: nocdiv.l4spclk */
- 0 /* Field: nocdiv.csatclk */
- 1 /* Field: nocdiv.cstraceclk */
- 1 /* Field: nocdiv.cspdbgclk */
- >;
- };
+ /*
+ * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: pinmux
+ */
+ i_io48_pin_mux: pinmux at 0xffd07000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "pinctrl-single";
+ reg = <0xffd07000 0x00000800>;
+ reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
- periph_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_perpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 159 /* Field: vco1.numer */
- 7 /* Field: cntr2clk.cnt */
- 1 /* Field: cntr2clk.src */
- 900 /* Field: cntr3clk.cnt */
- 1 /* Field: cntr3clk.src */
- 19 /* Field: cntr4clk.cnt */
- 1 /* Field: cntr4clk.src */
- 499 /* Field: cntr5clk.cnt */
- 1 /* Field: cntr5clk.src */
- 9 /* Field: cntr6clk.cnt */
- 1 /* Field: cntr6clk.src */
- 900 /* Field: cntr7clk.cnt */
- 900 /* Field: cntr8clk.cnt */
- 0 /* Field: cntr8clk.src */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: emacctl.emac0sel */
- 0 /* Field: emacctl.emac1sel */
- 0 /* Field: emacctl.emac2sel */
- 32000 /* Field: gpiodiv.gpiodbclk */
- >;
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
+ shared {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07000 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
+ <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
+ <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
+ <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
+ <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
+ <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
+ <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
+ <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
+ <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
+ <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
+ <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
+ <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
+ <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
+ <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
+ <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
+ <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
+ <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
+ <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
+ <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
+ <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
+ <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
+ <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
+ <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
+ <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
+ <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
+ <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
+ <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
+ <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
+ <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
+ <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
+ <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
+ <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
+ <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
+ <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
+ <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
+ <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
+ <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
+ <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
+ <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
+ <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
+ <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
+ <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
+ <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
+ <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
+ <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
+ <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
+ <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
+ <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
+ <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
+ };
- altera {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_alteragrp
- */
- altr,of_reg_value = <
- 0x0384000b /* Register: nocclk */
- 0x03840001 /* Register: mpuclk */
- >;
- };
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x003f3f3f>;
+ pinctrl-single,pins =
+ <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
+ <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
+ <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
+ <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
+ <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
+ <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
+ <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
+ <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
+ <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
+ <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
+ <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
+ <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
+ <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
+ <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
+ <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
+ <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
+ <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
+ <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
};
- /*
- * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
- * Binding: pinmux
- */
- i_io48_pin_mux: pinmux at 0xffd07000 {
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
+ fpga {
u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "pinctrl-single";
- reg = <0xffd07000 0x00000800>;
- reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
+ reg = <0xffd07400 0x00000100>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000001>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
+ <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
+ <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
+ <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
+ <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
+ <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
+ <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
+ <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
+ <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
+ <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
+ <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
+ <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
+ <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
+ <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
+ <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
+ <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
+ <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_noc_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_noc: noc at 0xffd10000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-noc";
+ reg = <0xffd10000 0x00008000>;
+ reg-names = "mpu_m0";
+ firewall {
+ u-boot,dm-pre-reloc;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_shared_3v_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
*/
- shared {
- u-boot,dm-pre-reloc;
- reg = <0xffd07000 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_shared_io_q1_1 */
- <0x00000000 0x00000008>,
- /* Reg: pinmux_shared_io_q1_2 */
- <0x00000004 0x00000008>,
- /* Reg: pinmux_shared_io_q1_3 */
- <0x00000008 0x00000008>,
- /* Reg: pinmux_shared_io_q1_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_shared_io_q1_6 */
- <0x00000014 0x00000008>,
- /* Reg: pinmux_shared_io_q1_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_shared_io_q1_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_shared_io_q1_10 */
- <0x00000024 0x00000008>,
- /* Reg: pinmux_shared_io_q1_11 */
- <0x00000028 0x00000008>,
- /* Reg: pinmux_shared_io_q1_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_shared_io_q2_1 */
- <0x00000030 0x00000004>,
- /* Reg: pinmux_shared_io_q2_2 */
- <0x00000034 0x00000004>,
- /* Reg: pinmux_shared_io_q2_3 */
- <0x00000038 0x00000004>,
- /* Reg: pinmux_shared_io_q2_4 */
- <0x0000003c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_5 */
- <0x00000040 0x00000004>,
- /* Reg: pinmux_shared_io_q2_6 */
- <0x00000044 0x00000004>,
- /* Reg: pinmux_shared_io_q2_7 */
- <0x00000048 0x00000004>,
- /* Reg: pinmux_shared_io_q2_8 */
- <0x0000004c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_9 */
- <0x00000050 0x00000004>,
- /* Reg: pinmux_shared_io_q2_10 */
- <0x00000054 0x00000004>,
- /* Reg: pinmux_shared_io_q2_11 */
- <0x00000058 0x00000004>,
- /* Reg: pinmux_shared_io_q2_12 */
- <0x0000005c 0x00000004>,
- /* Reg: pinmux_shared_io_q3_1 */
- <0x00000060 0x00000003>,
- /* Reg: pinmux_shared_io_q3_2 */
- <0x00000064 0x00000003>,
- /* Reg: pinmux_shared_io_q3_3 */
- <0x00000068 0x00000003>,
- /* Reg: pinmux_shared_io_q3_4 */
- <0x0000006c 0x00000003>,
- /* Reg: pinmux_shared_io_q3_5 */
- <0x00000070 0x00000003>,
- /* Reg: pinmux_shared_io_q3_6 */
- <0x00000074 0x0000000f>,
- /* Reg: pinmux_shared_io_q3_7 */
- <0x00000078 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_8 */
- <0x0000007c 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_9 */
- <0x00000080 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_10 */
- <0x00000084 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_11 */
- <0x00000088 0x00000001>,
- /* Reg: pinmux_shared_io_q3_12 */
- <0x0000008c 0x00000001>,
- /* Reg: pinmux_shared_io_q4_1 */
- <0x00000090 0x00000000>,
- /* Reg: pinmux_shared_io_q4_2 */
- <0x00000094 0x00000000>,
- /* Reg: pinmux_shared_io_q4_3 */
- <0x00000098 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_4 */
- <0x0000009c 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_5 */
- <0x000000a0 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_6 */
- <0x000000a4 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_7 */
- <0x000000a8 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_8 */
- <0x000000ac 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_9 */
- <0x000000b0 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_10 */
- <0x000000b4 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_11 */
- <0x000000b8 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_12 */
- <0x000000bc 0x0000000c>;
- };
-
+ mpu0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
*/
- dedicated {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_dedicated_io_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_dedicated_io_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_dedicated_io_6 */
- <0x00000014 0x00000008>,
- /* Regi: pinmux_dedicated_io_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_dedicated_io_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_dedicated_io_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_dedicated_io_10 */
- <0x00000024 0x0000000a>,
- /* Reg: pinmux_dedicated_io_11 */
- <0x00000028 0x0000000a>,
- /* Reg: pinmux_dedicated_io_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_dedicated_io_13 */
- <0x00000030 0x00000008>,
- /* Reg: pinmux_dedicated_io_14 */
- <0x00000034 0x00000008>,
- /* Reg: pinmux_dedicated_io_15 */
- <0x00000038 0x00000008>,
- /* Reg: pinmux_dedicated_io_16 */
- <0x0000003c 0x0000000d>,
- /* Reg: pinmux_dedicated_io_17 */
- <0x00000040 0x0000000d>;
- };
-
+ l3-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
*/
- dedicated_cfg {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x003f3f3f>;
- pinctrl-single,pins =
- /* Reg: cfg_dedicated_io_bank */
- <0x00000100 0x00000101>,
- /* Reg: cfg_dedicated_io_1 */
- <0x00000104 0x000b080a>,
- /* Reg: cfg_dedicated_io_2 */
- <0x00000108 0x000b080a>,
- /* Reg: cfg_dedicated_io_3 */
- <0x0000010c 0x000b080a>,
- /* Reg: cfg_dedicated_io_4 */
- <0x00000110 0x000a282a>,
- /* Reg: cfg_dedicated_io_5 */
- <0x00000114 0x000a282a>,
- /* Reg: cfg_dedicated_io_6 */
- <0x00000118 0x0008282a>,
- /* Reg: cfg_dedicated_io_7 */
- <0x0000011c 0x000a282a>,
- /* Reg: cfg_dedicated_io_8 */
- <0x00000120 0x000a282a>,
- /* Reg: cfg_dedicated_io_9 */
- <0x00000124 0x000a282a>,
- /* Reg: cfg_dedicated_io_10 */
- <0x00000128 0x00090000>,
- /* Reg: cfg_dedicated_io_11 */
- <0x0000012c 0x00090000>,
- /* Reg: cfg_dedicated_io_12 */
- <0x00000130 0x000b282a>,
- /* Reg: cfg_dedicated_io_13 */
- <0x00000134 0x000b282a>,
- /* Reg: cfg_dedicated_io_14 */
- <0x00000138 0x000b282a>,
- /* Reg: cfg_dedicated_io_15 */
- <0x0000013c 0x000b282a>,
- /* Reg: cfg_dedicated_io_16 */
- <0x00000140 0x0008282a>,
- /* Reg: cfg_dedicated_io_17 */
- <0x00000144 0x000a282a>;
- };
-
+ fpga2sdram0-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_fpga_interface_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
*/
- fpga {
- u-boot,dm-pre-reloc;
- reg = <0xffd07400 0x00000100>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000001>;
- pinctrl-single,pins =
- /* Reg: pinmux_emac0_usefpga */
- <0x00000000 0x00000000>,
- /* Reg: pinmux_emac1_usefpga */
- <0x00000004 0x00000000>,
- /* Reg: pinmux_emac2_usefpga */
- <0x00000008 0x00000000>,
- /* Reg: pinmux_i2c0_usefpga */
- <0x0000000c 0x00000000>,
- /* Reg: pinmux_i2c1_usefpga */
- <0x00000010 0x00000000>,
- /* Reg: pinmux_i2c_emac0_usefpga */
- <0x00000014 0x00000000>,
- /* Reg: pinmux_i2c_emac1_usefpga */
- <0x00000018 0x00000000>,
- /* Reg: pinmux_i2c_emac2_usefpga */
- <0x0000001c 0x00000000>,
- /* Reg: pinmux_nand_usefpga */
- <0x00000020 0x00000000>,
- /* Reg: pinmux_qspi_usefpga */
- <0x00000024 0x00000000>,
- /* Reg: pinmux_sdmmc_usefpga */
- <0x00000028 0x00000000>,
- /* Reg: pinmux_spim0_usefpga */
- <0x0000002c 0x00000000>,
- /* Reg: pinmux_spim1_usefpga */
- <0x00000030 0x00000000>,
- /* Reg: pinmux_spis0_usefpga */
- <0x00000034 0x00000000>,
- /* Reg: pinmux_spis1_usefpga */
- <0x00000038 0x00000000>,
- /* Reg: pinmux_uart0_usefpga */
- <0x0000003c 0x00000000>,
- /* Reg: pinmux_uart1_usefpga */
- <0x00000040 0x00000000>;
- };
- };
-
- i_noc: noc at 0xffd10000 {
- u-boot,dm-pre-reloc;
- compatible = "altr,socfpga-a10-noc";
- reg = <0xffd10000 0x00008000>;
- reg-names = "mpu_m0";
-
- firewall {
- u-boot,dm-pre-reloc;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.limit
- */
- altr,mpu0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.limit
- */
- altr,l3-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.limit
- */
- altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.limit
- */
- altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.limit
- */
- altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
- };
+ fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
+ */
+ fpga2sdram2-0 = <0x00000000 0x0000ffff>;
};
+ };
- hps_fpgabridge0: fpgabridge at 0 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge0: fpgabridge at 0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge1: fpgabridge at 1 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge1: fpgabridge at 1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge2: fpgabridge at 2 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge2: fpgabridge at 2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge3: fpgabridge at 3 {
- compatible = "altr,socfpga-fpga2sdram0-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge3: fpgabridge at 3 {
+ compatible = "altr,socfpga-fpga2sdram0-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge4: fpgabridge at 4 {
- compatible = "altr,socfpga-fpga2sdram1-bridge";
- altr,init-val = <0>;
- };
+ hps_fpgabridge4: fpgabridge at 4 {
+ compatible = "altr,socfpga-fpga2sdram1-bridge";
+ init-val = <0>;
+ };
- hps_fpgabridge5: fpgabridge at 5 {
- compatible = "altr,socfpga-fpga2sdram2-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge5: fpgabridge at 5 {
+ compatible = "altr,socfpga-fpga2sdram2-bridge";
+ init-val = <1>;
};
};
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (2 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-16 10:24 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name Marek Vasut
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
NOTE: This should be converted to reset framework.
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
arch/arm/mach-socfpga/misc.c | 65 +++++++++++++++++++++
arch/arm/mach-socfpga/misc_arria10.c | 19 +++++-
arch/arm/mach-socfpga/misc_gen5.c | 67 ++--------------------
4 files changed, 87 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index d3ae80bc27..8ee801c635 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -10,6 +10,8 @@ void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+ const u8 phymode));
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5c27f1984e..7bedcb36f4 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -135,3 +135,68 @@ int arch_cpu_init(void)
return 0;
}
+
+#ifdef CONFIG_ETH_DESIGNWARE
+static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+ if (!phymode)
+ return -EINVAL;
+
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rgmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+ const u8 phymode))
+{
+ const void *fdt = gd->fdt_blob;
+ struct fdtdec_phandle_args args;
+ const char *phy_mode;
+ u32 phy_modereg;
+ int nodes[2]; /* Max. two GMACs */
+ int ret, count;
+ int i, node;
+
+ count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+ COMPAT_ALTERA_SOCFPGA_DWMAC,
+ nodes, ARRAY_SIZE(nodes));
+ for (i = 0; i < count; i++) {
+ node = nodes[i];
+ if (node <= 0)
+ continue;
+
+ ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+ "#reset-cells", 1, 0,
+ &args);
+ if (ret || (args.args_count != 1)) {
+ debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+ continue;
+ }
+
+ phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+ ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+ if (ret) {
+ debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+ continue;
+ }
+
+ resetfn(args.args[0], phy_modereg);
+ }
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f909568312..e1d80a5a76 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -41,8 +41,7 @@ static struct socfpga_system_manager *sysmgr_regs =
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
+static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
{
u32 reset;
@@ -64,6 +63,20 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
+
+static int socfpga_eth_reset(void)
+{
+ /* Put all GMACs into RESET state. */
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
+ return socfpga_eth_reset_common(arria10_dwmac_reset);
+};
+#else
+static int socfpga_eth_reset(void)
+{
+ return 0;
+};
#endif
#if defined(CONFIG_SPL_BUILD)
@@ -251,6 +264,6 @@ int print_cpuinfo(void)
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
- return 0;
+ return socfpga_eth_reset();
}
#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index efec58d555..434373404e 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -38,8 +38,7 @@ static struct scu_registers *scu_regs =
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
+static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
{
u32 physhift, reset;
@@ -63,71 +62,13 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
socfpga_per_reset(reset, 0);
}
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- return 0;
- }
-
- if (!strcmp(phymode, "rgmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- return 0;
- }
-
- if (!strcmp(phymode, "rmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- return 0;
- }
-
- return -EINVAL;
-}
-
static int socfpga_eth_reset(void)
{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 phy_modereg;
- int nodes[2]; /* Max. two GMACs */
- int ret, count;
- int i, node;
-
- /* Put both GMACs into RESET state. */
+ /* Put all GMACs into RESET state. */
socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
- "#reset-cells", 1, 0,
- &args);
- if (ret || (args.args_count != 1)) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
-
- dwmac_deassert_reset(args.args[0], phy_modereg);
- }
-
- return 0;
-}
+ return socfpga_eth_reset_common(gen5_dwmac_reset);
+};
#else
static int socfpga_eth_reset(void)
{
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
@ 2018-05-16 10:24 ` Ley Foon Tan
0 siblings, 0 replies; 25+ messages in thread
From: Ley Foon Tan @ 2018-05-16 10:24 UTC (permalink / raw)
To: u-boot
On Sun, May 13, 2018 at 4:30 AM, Marek Vasut <marex@denx.de> wrote:
> The EMAC reset and PHY mode configuration was never working on the
> Arria10 SoC, fix this. This patch pulls out the common code into
> misc.c and passes the SoC-specific function call in as a function
> pointer.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
> NOTE: This should be converted to reset framework.
Yes, I have converted this to use reset framework for S10. It should
can be use for A10 and Gen5 as well.
> ---
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
> arch/arm/mach-socfpga/misc.c | 65 +++++++++++++++++++++
> arch/arm/mach-socfpga/misc_arria10.c | 19 +++++-
> arch/arm/mach-socfpga/misc_gen5.c | 67 ++--------------------
> 4 files changed, 87 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index d3ae80bc27..8ee801c635 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -10,6 +10,8 @@ void reset_cpu(ulong addr);
>
> void socfpga_per_reset(u32 reset, int set);
> void socfpga_per_reset_all(void);
> +int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
> + const u8 phymode));
>
> #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 5c27f1984e..7bedcb36f4 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -135,3 +135,68 @@ int arch_cpu_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_ETH_DESIGNWARE
> +static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
> +{
> + if (!phymode)
> + return -EINVAL;
> +
> + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
> + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
> + return 0;
> + }
> +
> + if (!strcmp(phymode, "rgmii")) {
> + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
> + return 0;
> + }
> +
> + if (!strcmp(phymode, "rmii")) {
> + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> +int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
> + const u8 phymode))
> +{
> + const void *fdt = gd->fdt_blob;
> + struct fdtdec_phandle_args args;
> + const char *phy_mode;
> + u32 phy_modereg;
> + int nodes[2]; /* Max. two GMACs */
> + int ret, count;
> + int i, node;
> +
> + count = fdtdec_find_aliases_for_id(fdt, "ethernet",
> + COMPAT_ALTERA_SOCFPGA_DWMAC,
> + nodes, ARRAY_SIZE(nodes));
> + for (i = 0; i < count; i++) {
> + node = nodes[i];
> + if (node <= 0)
> + continue;
> +
> + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
> + "#reset-cells", 1, 0,
> + &args);
> + if (ret || (args.args_count != 1)) {
> + debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
> + continue;
> + }
> +
> + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
> + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
> + if (ret) {
> + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
> + continue;
> + }
> +
> + resetfn(args.args[0], phy_modereg);
> + }
> +
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
> index f909568312..e1d80a5a76 100644
> --- a/arch/arm/mach-socfpga/misc_arria10.c
> +++ b/arch/arm/mach-socfpga/misc_arria10.c
> @@ -41,8 +41,7 @@ static struct socfpga_system_manager *sysmgr_regs =
> * DesignWare Ethernet initialization
> */
> #ifdef CONFIG_ETH_DESIGNWARE
> -void dwmac_deassert_reset(const unsigned int of_reset_id,
> - const u32 phymode)
> +static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
> {
> u32 reset;
>
> @@ -64,6 +63,20 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
> /* Release the EMAC controller from reset */
> socfpga_per_reset(reset, 0);
> }
> +
> +static int socfpga_eth_reset(void)
> +{
> + /* Put all GMACs into RESET state. */
> + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
> + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
> + socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
> + return socfpga_eth_reset_common(arria10_dwmac_reset);
> +};
> +#else
> +static int socfpga_eth_reset(void)
> +{
> + return 0;
> +};
> #endif
>
> #if defined(CONFIG_SPL_BUILD)
> @@ -251,6 +264,6 @@ int print_cpuinfo(void)
> #ifdef CONFIG_ARCH_MISC_INIT
> int arch_misc_init(void)
> {
> - return 0;
> + return socfpga_eth_reset();
> }
> #endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index efec58d555..434373404e 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -38,8 +38,7 @@ static struct scu_registers *scu_regs =
> * DesignWare Ethernet initialization
> */
> #ifdef CONFIG_ETH_DESIGNWARE
> -void dwmac_deassert_reset(const unsigned int of_reset_id,
> - const u32 phymode)
> +static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
> {
> u32 physhift, reset;
>
> @@ -63,71 +62,13 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
> socfpga_per_reset(reset, 0);
> }
>
> -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
> -{
> - if (!phymode)
> - return -EINVAL;
> -
> - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
> - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
> - return 0;
> - }
> -
> - if (!strcmp(phymode, "rgmii")) {
> - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
> - return 0;
> - }
> -
> - if (!strcmp(phymode, "rmii")) {
> - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
> - return 0;
> - }
> -
> - return -EINVAL;
> -}
> -
> static int socfpga_eth_reset(void)
> {
> - const void *fdt = gd->fdt_blob;
> - struct fdtdec_phandle_args args;
> - const char *phy_mode;
> - u32 phy_modereg;
> - int nodes[2]; /* Max. two GMACs */
> - int ret, count;
> - int i, node;
> -
> - /* Put both GMACs into RESET state. */
> + /* Put all GMACs into RESET state. */
> socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
> socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
> -
> - count = fdtdec_find_aliases_for_id(fdt, "ethernet",
> - COMPAT_ALTERA_SOCFPGA_DWMAC,
> - nodes, ARRAY_SIZE(nodes));
> - for (i = 0; i < count; i++) {
> - node = nodes[i];
> - if (node <= 0)
> - continue;
> -
> - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
> - "#reset-cells", 1, 0,
> - &args);
> - if (ret || (args.args_count != 1)) {
> - debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
> - continue;
> - }
> -
> - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
> - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
> - if (ret) {
> - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
> - continue;
> - }
> -
> - dwmac_deassert_reset(args.args[0], phy_modereg);
> - }
> -
> - return 0;
> -}
> + return socfpga_eth_reset_common(gen5_dwmac_reset);
> +};
> #else
> static int socfpga_eth_reset(void)
> {
> --
> 2.16.2
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (3 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function Marek Vasut
` (6 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 432 +----------------------
arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 442 ++++++++++++++++++++++++
drivers/ddr/altera/Makefile | 2 +-
drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0
4 files changed, 446 insertions(+), 430 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_gen5.h
rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index a58872c3d9..1a4b22accd 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -7,435 +7,9 @@
#ifndef __ASSEMBLY__
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4; /* 0x10 */
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 __padding0[3];
- u32 dram_addrw; /* 0x2c */
- u32 dram_if_width; /* 0x30 */
- u32 dram_dev_width;
- u32 dram_sts;
- u32 dram_intr;
- u32 sbe_count; /* 0x40 */
- u32 dbe_count;
- u32 err_addr;
- u32 drop_count;
- u32 drop_addr; /* 0x50 */
- u32 lowpwr_eq;
- u32 lowpwr_ack;
- u32 static_cfg;
- u32 ctrl_width; /* 0x60 */
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap; /* 0x70 */
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst; /* 0x80 */
- u32 __padding1;
- u32 fifo_cfg;
- u32 protport_default;
- u32 prot_rule_addr; /* 0x90 */
- u32 prot_rule_id;
- u32 prot_rule_data;
- u32 prot_rule_rdwr;
- u32 __padding2[3];
- u32 mp_priority; /* 0xac */
- u32 mp_weight0; /* 0xb0 */
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0; /* 0xc0 */
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0; /* 0xd0 */
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 __padding3[29];
- u32 phy_ctrl0; /* 0x150 */
- u32 phy_ctrl1;
- u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4;
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 dram_addrw;
- u32 dram_if_width;
- u32 dram_dev_width;
- u32 dram_intr;
- u32 lowpwr_eq;
- u32 static_cfg;
- u32 ctrl_width;
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap;
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst;
- u32 fifo_cfg;
- u32 mp_priority;
- u32 mp_weight0;
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0;
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0;
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
- u8 activate_0_and_1;
- u8 activate_0_and_1_wait1;
- u8 activate_0_and_1_wait2;
- u8 activate_1;
- u8 clear_dqs_enable;
- u8 guaranteed_read;
- u8 guaranteed_read_cont;
- u8 guaranteed_write;
- u8 guaranteed_write_wait0;
- u8 guaranteed_write_wait1;
- u8 guaranteed_write_wait2;
- u8 guaranteed_write_wait3;
- u8 idle;
- u8 idle_loop1;
- u8 idle_loop2;
- u8 init_reset_0_cke_0;
- u8 init_reset_1_cke_0;
- u8 lfsr_wr_rd_bank_0;
- u8 lfsr_wr_rd_bank_0_data;
- u8 lfsr_wr_rd_bank_0_dqs;
- u8 lfsr_wr_rd_bank_0_nop;
- u8 lfsr_wr_rd_bank_0_wait;
- u8 lfsr_wr_rd_bank_0_wl_1;
- u8 lfsr_wr_rd_dm_bank_0;
- u8 lfsr_wr_rd_dm_bank_0_data;
- u8 lfsr_wr_rd_dm_bank_0_dqs;
- u8 lfsr_wr_rd_dm_bank_0_nop;
- u8 lfsr_wr_rd_dm_bank_0_wait;
- u8 lfsr_wr_rd_dm_bank_0_wl_1;
- u8 mrs0_dll_reset;
- u8 mrs0_dll_reset_mirr;
- u8 mrs0_user;
- u8 mrs0_user_mirr;
- u8 mrs1;
- u8 mrs1_mirr;
- u8 mrs2;
- u8 mrs2_mirr;
- u8 mrs3;
- u8 mrs3_mirr;
- u8 precharge_all;
- u8 read_b2b;
- u8 read_b2b_wait1;
- u8 read_b2b_wait2;
- u8 refresh_all;
- u8 rreturn;
- u8 sgle_read;
- u8 zqcl;
-
- u8 true_mem_data_mask_width;
- u8 mem_address_mirroring;
- u8 mem_data_mask_width;
- u8 mem_data_width;
- u8 mem_dq_per_read_dqs;
- u8 mem_dq_per_write_dqs;
- u8 mem_if_read_dqs_width;
- u8 mem_if_write_dqs_width;
- u8 mem_number_of_cs_per_dimm;
- u8 mem_number_of_ranks;
- u8 mem_virtual_groups_per_read_dqs;
- u8 mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
- u16 delay_per_opa_tap;
- u8 delay_per_dchain_tap;
- u8 delay_per_dqs_en_dchain_tap;
- u8 dll_chain_length;
- u8 dqdqs_out_phase_max;
- u8 dqs_en_delay_max;
- u8 dqs_en_delay_offset;
- u8 dqs_en_phase_max;
- u8 dqs_in_delay_max;
- u8 dqs_in_reserve;
- u8 dqs_out_reserve;
- u8 io_in_delay_max;
- u8 io_out1_delay_max;
- u8 io_out2_delay_max;
- u8 shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
- u32 reg_file_init_seq_signature;
- u8 afi_rate_ratio;
- u8 calib_lfifo_offset;
- u8 calib_vfifo_offset;
- u8 enable_super_quick_calibration;
- u8 max_latency_count_width;
- u8 read_valid_fifo_size;
- u8 tinit_cntr0_val;
- u8 tinit_cntr1_val;
- u8 tinit_cntr2_val;
- u8 treset_cntr0_val;
- u8 treset_cntr1_val;
- u8 treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1 */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2 */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3 */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4 */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1 */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC 40
-#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#endif
#endif
#endif /* _SDRAM_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
new file mode 100644
index 0000000000..b16d77668f
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -0,0 +1,442 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _SOCFPGA_SDRAM_GEN5_H_
+#define _SOCFPGA_SDRAM_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
+
+#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
+
+struct socfpga_sdr_ctrl {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4; /* 0x10 */
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 __padding0[3];
+ u32 dram_addrw; /* 0x2c */
+ u32 dram_if_width; /* 0x30 */
+ u32 dram_dev_width;
+ u32 dram_sts;
+ u32 dram_intr;
+ u32 sbe_count; /* 0x40 */
+ u32 dbe_count;
+ u32 err_addr;
+ u32 drop_count;
+ u32 drop_addr; /* 0x50 */
+ u32 lowpwr_eq;
+ u32 lowpwr_ack;
+ u32 static_cfg;
+ u32 ctrl_width; /* 0x60 */
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap; /* 0x70 */
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst; /* 0x80 */
+ u32 __padding1;
+ u32 fifo_cfg;
+ u32 protport_default;
+ u32 prot_rule_addr; /* 0x90 */
+ u32 prot_rule_id;
+ u32 prot_rule_data;
+ u32 prot_rule_rdwr;
+ u32 __padding2[3];
+ u32 mp_priority; /* 0xac */
+ u32 mp_weight0; /* 0xb0 */
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0; /* 0xc0 */
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0; /* 0xd0 */
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 __padding3[29];
+ u32 phy_ctrl0; /* 0x150 */
+ u32 phy_ctrl1;
+ u32 phy_ctrl2;
+};
+
+/* SDRAM configuration structure for the SPL. */
+struct socfpga_sdram_config {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4;
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 dram_addrw;
+ u32 dram_if_width;
+ u32 dram_dev_width;
+ u32 dram_intr;
+ u32 lowpwr_eq;
+ u32 static_cfg;
+ u32 ctrl_width;
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap;
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst;
+ u32 fifo_cfg;
+ u32 mp_priority;
+ u32 mp_weight0;
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0;
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0;
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 phy_ctrl0;
+};
+
+struct socfpga_sdram_rw_mgr_config {
+ u8 activate_0_and_1;
+ u8 activate_0_and_1_wait1;
+ u8 activate_0_and_1_wait2;
+ u8 activate_1;
+ u8 clear_dqs_enable;
+ u8 guaranteed_read;
+ u8 guaranteed_read_cont;
+ u8 guaranteed_write;
+ u8 guaranteed_write_wait0;
+ u8 guaranteed_write_wait1;
+ u8 guaranteed_write_wait2;
+ u8 guaranteed_write_wait3;
+ u8 idle;
+ u8 idle_loop1;
+ u8 idle_loop2;
+ u8 init_reset_0_cke_0;
+ u8 init_reset_1_cke_0;
+ u8 lfsr_wr_rd_bank_0;
+ u8 lfsr_wr_rd_bank_0_data;
+ u8 lfsr_wr_rd_bank_0_dqs;
+ u8 lfsr_wr_rd_bank_0_nop;
+ u8 lfsr_wr_rd_bank_0_wait;
+ u8 lfsr_wr_rd_bank_0_wl_1;
+ u8 lfsr_wr_rd_dm_bank_0;
+ u8 lfsr_wr_rd_dm_bank_0_data;
+ u8 lfsr_wr_rd_dm_bank_0_dqs;
+ u8 lfsr_wr_rd_dm_bank_0_nop;
+ u8 lfsr_wr_rd_dm_bank_0_wait;
+ u8 lfsr_wr_rd_dm_bank_0_wl_1;
+ u8 mrs0_dll_reset;
+ u8 mrs0_dll_reset_mirr;
+ u8 mrs0_user;
+ u8 mrs0_user_mirr;
+ u8 mrs1;
+ u8 mrs1_mirr;
+ u8 mrs2;
+ u8 mrs2_mirr;
+ u8 mrs3;
+ u8 mrs3_mirr;
+ u8 precharge_all;
+ u8 read_b2b;
+ u8 read_b2b_wait1;
+ u8 read_b2b_wait2;
+ u8 refresh_all;
+ u8 rreturn;
+ u8 sgle_read;
+ u8 zqcl;
+
+ u8 true_mem_data_mask_width;
+ u8 mem_address_mirroring;
+ u8 mem_data_mask_width;
+ u8 mem_data_width;
+ u8 mem_dq_per_read_dqs;
+ u8 mem_dq_per_write_dqs;
+ u8 mem_if_read_dqs_width;
+ u8 mem_if_write_dqs_width;
+ u8 mem_number_of_cs_per_dimm;
+ u8 mem_number_of_ranks;
+ u8 mem_virtual_groups_per_read_dqs;
+ u8 mem_virtual_groups_per_write_dqs;
+};
+
+struct socfpga_sdram_io_config {
+ u16 delay_per_opa_tap;
+ u8 delay_per_dchain_tap;
+ u8 delay_per_dqs_en_dchain_tap;
+ u8 dll_chain_length;
+ u8 dqdqs_out_phase_max;
+ u8 dqs_en_delay_max;
+ u8 dqs_en_delay_offset;
+ u8 dqs_en_phase_max;
+ u8 dqs_in_delay_max;
+ u8 dqs_in_reserve;
+ u8 dqs_out_reserve;
+ u8 io_in_delay_max;
+ u8 io_out1_delay_max;
+ u8 io_out2_delay_max;
+ u8 shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+ u32 reg_file_init_seq_signature;
+ u8 afi_rate_ratio;
+ u8 calib_lfifo_offset;
+ u8 calib_vfifo_offset;
+ u8 enable_super_quick_calibration;
+ u8 max_latency_count_width;
+ u8 read_valid_fifo_size;
+ u8 tinit_cntr0_val;
+ u8 tinit_cntr1_val;
+ u8 tinit_cntr2_val;
+ u8 treset_cntr0_val;
+ u8 treset_cntr1_val;
+ u8 treset_cntr2_val;
+};
+
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1 */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2 */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3 */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4 */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
+
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC 40
+#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+
+#endif
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index d42fd4451d..ec1cb0b6e4 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -7,5 +7,5 @@
# Copyright (C) 2014 Altera Corporation <www.altera.com>
ifdef CONFIG_ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
endif
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram_gen5.c
similarity index 100%
rename from drivers/ddr/altera/sdram.c
rename to drivers/ddr/altera/sdram_gen5.c
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (4 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10 Marek Vasut
` (5 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/board.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index c23ac4ead3..38e12a41a3 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -28,6 +28,13 @@ int board_init(void)
return 0;
}
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.usb_gusbcfg = 0x1417,
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (5 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support " Marek Vasut
` (4 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add DDR driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 +
drivers/ddr/altera/Makefile | 1 +
drivers/ddr/altera/sdram_arria10.c | 741 +++++++++++++++++++++
4 files changed, 746 insertions(+)
create mode 100644 drivers/ddr/altera/sdram_arria10.c
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 1a4b22accd..79cb9e6064 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -9,6 +9,8 @@
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
#endif
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 8ae8d1bc96..25b82fb285 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -7,6 +7,7 @@
#define _SOCFPGA_SDRAM_ARRIA10_H_
#ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
struct socfpga_ecc_hmc {
u32 ip_rev_id;
@@ -203,6 +204,7 @@ struct socfpga_io48_mmr {
u32 niosreserve1;
u32 niosreserve2;
};
+
#endif /*__ASSEMBLY__*/
#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ec1cb0b6e4..f05314a373 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -8,4 +8,5 @@
ifdef CONFIG_ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
endif
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 0000000000..d953c376b8
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,741 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/sdram.h>
+#include <linux/kernel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static u64 sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+ (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE 0xFFD0507C
+#define DDR_REG_CORE2SEQ 0xFFD05078
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_SIZE_2GB_HEX 0x80000000
+#define DDR_MAX_TRIES 0x00100000
+
+#define IO48_MMR_DRAMSTS 0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
+
+#define SEQ2CORE_MASK 0xF
+#define CORE2SEQ_INT_REQ 0xF
+#define SEQ2CORE_INT_RESP_BIT 3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+ (void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+ (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+ *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+ (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+ (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+ (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The following are the supported configurations */
+static u32 ddr_config[] = {
+ /* Chip - Row - Bank - Column Style */
+ /* All Types */
+ ARRIA_DDR_CONFIG(0, 3, 10, 12),
+ ARRIA_DDR_CONFIG(0, 3, 10, 13),
+ ARRIA_DDR_CONFIG(0, 3, 10, 14),
+ ARRIA_DDR_CONFIG(0, 3, 10, 15),
+ ARRIA_DDR_CONFIG(0, 3, 10, 16),
+ ARRIA_DDR_CONFIG(0, 3, 10, 17),
+ /* LPDDR x16 */
+ ARRIA_DDR_CONFIG(0, 3, 11, 14),
+ ARRIA_DDR_CONFIG(0, 3, 11, 15),
+ ARRIA_DDR_CONFIG(0, 3, 11, 16),
+ ARRIA_DDR_CONFIG(0, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(0, 4, 10, 14),
+ ARRIA_DDR_CONFIG(0, 4, 10, 15),
+ ARRIA_DDR_CONFIG(0, 4, 10, 16),
+ ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+ /* Chip - Bank - Row - Column Style */
+ ARRIA_DDR_CONFIG(1, 3, 10, 12),
+ ARRIA_DDR_CONFIG(1, 3, 10, 13),
+ ARRIA_DDR_CONFIG(1, 3, 10, 14),
+ ARRIA_DDR_CONFIG(1, 3, 10, 15),
+ ARRIA_DDR_CONFIG(1, 3, 10, 16),
+ ARRIA_DDR_CONFIG(1, 3, 10, 17),
+ ARRIA_DDR_CONFIG(1, 3, 11, 14),
+ ARRIA_DDR_CONFIG(1, 3, 11, 15),
+ ARRIA_DDR_CONFIG(1, 3, 11, 16),
+ ARRIA_DDR_CONFIG(1, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(1, 4, 10, 14),
+ ARRIA_DDR_CONFIG(1, 4, 10, 15),
+ ARRIA_DDR_CONFIG(1, 4, 10, 16),
+ ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(u32 ddr_conf)
+{
+ int i;
+
+ for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+ if (ddr_conf == ddr_config[i])
+ return i;
+ }
+ return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+ return readl(&socfpga_ecc_hmc_base->ddrcalstat);
+}
+
+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
+{
+ u32 reg = readl(ereg);
+
+ return (reg & BIT(bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
+ u32 expected, u32 timeout_usec)
+{
+ u32 tmr;
+
+ for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+ udelay(100);
+ WATCHDOG_RESET();
+ if (ddr_get_bit(ereg, bit) == expected)
+ return 0;
+ }
+
+ return 1;
+}
+
+static int emif_clear(void)
+{
+ u32 i = DDR_MAX_TRIES;
+ u8 ret = 0;
+
+ writel(0, DDR_REG_CORE2SEQ);
+
+ do {
+ ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+ SEQ2CORE_MASK, 1, 50, 0);
+ } while (ret && (--i > 0));
+
+ return !i;
+}
+
+static int emif_reset(void)
+{
+ u32 c2s, s2c;
+
+ c2s = readl(DDR_REG_CORE2SEQ);
+ s2c = readl(DDR_REG_SEQ2CORE);
+
+ debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+ c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2),
+ readl(IO48_MMR_DRAMSTS));
+
+ if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+ debug("failed emif_clear()\n");
+ return -EPERM;
+ }
+
+ writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+ if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+ debug("emif_reset failed to see interrupt acknowledge\n");
+ return -EPERM;
+ } else {
+ debug("emif_reset interrupt acknowledged\n");
+ }
+
+ if (emif_clear()) {
+ debug("emif_clear() failed\n");
+ return -EPERM;
+ }
+ debug("emif_reset interrupt cleared\n");
+
+ debug("nr0=%08x nr1=%08x nr2=%08x\n",
+ readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2));
+
+ return 0;
+}
+
+static int ddr_setup(void)
+{
+ int i, j, ddr_setup_complete = 0;
+
+ /* Try 3 times to do a calibration */
+ for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+ WATCHDOG_RESET();
+
+ /* A delay to wait for calibration bit to set */
+ for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+ mdelay(500);
+ ddr_setup_complete = is_sdram_cal_success();
+ }
+
+ if (!ddr_setup_complete)
+ if (emif_reset())
+ puts("Error: Failed to reset EMIF\n");
+ }
+
+ /* After 3 times trying calibration */
+ if (!ddr_setup_complete) {
+ puts("Error: Could Not Calibrate SDRAM\n");
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int sdram_startup(void)
+{
+ /* Release NOC ddr scheduler from reset */
+ socfpga_reset_deassert_noc_ddr_scheduler();
+
+ /* Bringup the DDR (calibration and configuration) */
+ return ddr_setup();
+}
+
+static u64 sdram_size_calc(void)
+{
+ u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+
+ u64 size = BIT(((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
+ (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
+
+ size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+ ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
+
+ debug("SDRAM size=%llu", size);
+
+ return size;
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void sdram_mmr_init(void)
+{
+ u32 update_value, io48_value;
+ u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
+ u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
+ u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+ u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
+ u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
+ u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
+ u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
+ u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
+ u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
+ u32 ddrioctl;
+
+ /*
+ * Configure the DDR IO size [0xFFCFB008]
+ * niosreserve0: Used to indicate DDR width &
+ * bit[7:0] = Number of data bits (0x20 for 32bit)
+ * bit[8] = 1 if user-mode OCT is present
+ * bit[9] = 1 if warm reset compiled into EMIF Cal Code
+ * bit[10] = 1 if warm reset is on during generation in EMIF Cal
+ * niosreserve1: IP ADCDS version encoded as 16 bit value
+ * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+ * 3=EAP, 4-6 are reserved)
+ * bit[5:3] = Service Pack # (e.g. 1)
+ * bit[9:6] = Minor Release #
+ * bit[14:10] = Major Release #
+ */
+ if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+ update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+ writel(((update_value & 0xFF) >> 5),
+ &socfpga_ecc_hmc_base->ddrioctrl);
+ }
+
+ ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+ /* Set the DDR Configuration [0xFFD12400] */
+ io48_value = ARRIA_DDR_CONFIG(
+ ((ctrlcfg1 &
+ IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
+ IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
+ (dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
+
+ update_value = match_ddr_conf(io48_value);
+ if (update_value)
+ writel(update_value,
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
+
+ /*
+ * Configure DDR timing [0xFFD1240C]
+ * RDTOMISS = tRTP + tRP + tRCD - BL/2
+ * WRTOMISS = WL + tWR + tRP + tRCD and
+ * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
+ * First part of equation is in memory clock units so divide by 2
+ * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+ * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+ */
+ u32 ctrlcfg0_cfg_ctrl_burst_len =
+ (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
+ IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
+
+ u32 caltim0_cfg_act_to_rdwr = caltim0 &
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
+
+ u32 caltim0_cfg_act_to_act =
+ (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
+
+ u32 caltim0_cfg_act_to_act_db =
+ (caltim0 &
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
+
+ u32 caltim1_cfg_rd_to_wr =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
+
+ u32 caltim1_cfg_rd_to_rd_dc =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
+
+ u32 caltim1_cfg_rd_to_wr_dc =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
+
+ u32 caltim2_cfg_rd_to_pch =
+ (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
+ IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
+
+ u32 caltim3_cfg_wr_to_rd =
+ (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
+ IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
+
+ u32 caltim3_cfg_wr_to_rd_dc =
+ (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
+ IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
+
+ u32 caltim4_cfg_pch_to_valid =
+ (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
+ IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
+
+ u32 caltim9_cfg_4_act_to_act = caltim9 &
+ IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
+
+ update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
+ caltim0_cfg_act_to_rdwr -
+ (ctrlcfg0_cfg_ctrl_burst_len >> 2));
+
+ io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+ ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
+ (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
+ /* Up to here was in memory cycles so divide by 2 */
+ caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
+ caltim4_cfg_pch_to_valid);
+
+ writel(((caltim0_cfg_act_to_act <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+ (update_value <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+ (io48_value <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+ ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+ (caltim1_cfg_rd_to_wr <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+ (caltim3_cfg_wr_to_rd <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+ (((ddrioctl == 1) ? 1 : 0) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+ &socfpga_noc_ddr_scheduler_base->
+ ddr_t_main_scheduler_ddrtiming);
+
+ /* Configure DDR mode [0xFFD12410] [precharge = 0] */
+ writel(((ddrioctl ? 0 : 1) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
+
+ /* Configure the read latency [0xFFD12414] */
+ writel(((socfpga_io48_mmr_base->dramtiming0 &
+ ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
+ DDR_READ_LATENCY_DELAY,
+ &socfpga_noc_ddr_scheduler_base->
+ ddr_t_main_scheduler_readlatency);
+
+ /*
+ * Configuring timing values concerning activate commands
+ * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+ */
+ writel(((caltim0_cfg_act_to_act_db <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+ (caltim9_cfg_4_act_to_act <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+ (ARRIA10_SDR_ACTIVATE_FAWBANK <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
+
+ /*
+ * Configuring timing values concerning device to device data bus
+ * ownership change [0xFFD1243C]
+ */
+ writel(((caltim1_cfg_rd_to_rd_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+ (caltim1_cfg_rd_to_wr_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+ (caltim3_cfg_wr_to_rd_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
+
+ /* Enable or disable the SDRAM ECC */
+ if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
+ setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
+ setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+ (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+ } else {
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+ (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+ }
+}
+
+struct firewall_entry {
+ const char *prop_name;
+ const u32 cfg_addr;
+ const u32 en_addr;
+ const u32 en_bit;
+};
+#define FW_MPU_FPGA_ADDRESS \
+ ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
+
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
+ (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
+ offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
+
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
+ (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
+ offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
+
+const struct firewall_entry firewall_table[] = {
+ {
+ "mpu0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
+ },
+ {
+ "mpu1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
+ },
+ {
+ "mpu2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
+ },
+ {
+ "mpu3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
+ },
+ {
+ "l3-0",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
+ },
+ {
+ "l3-1",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
+ },
+ {
+ "l3-2",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
+ },
+ {
+ "l3-3",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
+ },
+ {
+ "l3-4",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
+ },
+ {
+ "l3-5",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
+ },
+ {
+ "l3-6",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
+ },
+ {
+ "l3-7",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
+ },
+
+};
+
+static int of_sdram_firewall_setup(const void *blob)
+{
+ int child, i, node, ret;
+ u32 start_end[2];
+ char name[32];
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
+ if (node < 0)
+ return -ENXIO;
+
+ child = fdt_first_subnode(blob, node);
+ if (child < 0)
+ return -ENXIO;
+
+ /* set to default state */
+ writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
+ writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
+
+
+ for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
+ sprintf(name, "%s", firewall_table[i].prop_name);
+ ret = fdtdec_get_int_array(blob, child, name,
+ start_end, 2);
+ if (ret) {
+ sprintf(name, "altr,%s", firewall_table[i].prop_name);
+ ret = fdtdec_get_int_array(blob, child, name,
+ start_end, 2);
+ if (ret)
+ continue;
+ }
+
+ writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
+ (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
+ firewall_table[i].cfg_addr);
+ setbits_le32(firewall_table[i].en_addr,
+ firewall_table[i].en_bit);
+ }
+
+ return 0;
+}
+
+int ddr_calibration_sequence(void)
+{
+ WATCHDOG_RESET();
+
+ /* Check to see if SDRAM cal was success */
+ if (sdram_startup()) {
+ puts("DDRCAL: Failed\n");
+ return -EPERM;
+ }
+
+ puts("DDRCAL: Success\n");
+
+ WATCHDOG_RESET();
+
+ /* initialize the MMR register */
+ sdram_mmr_init();
+
+ /* assigning the SDRAM size */
+ u64 size = sdram_size_calc();
+
+ /*
+ * If size is less than zero, this is invalid/weird value from
+ * calculation, use default Config size.
+ * Up to 2GB is supported, 2GB would be used if more than that.
+ */
+ if (size <= 0)
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ else if (DDR_SIZE_2GB_HEX <= size)
+ gd->ram_size = DDR_SIZE_2GB_HEX;
+ else
+ gd->ram_size = (u32)size;
+
+ /* setup the dram info within bd */
+ dram_init_banksize();
+
+ if (of_sdram_firewall_setup(gd->fdt_blob))
+ puts("FW: Error Configuring Firewall\n");
+
+ return 0;
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = bd->bi_dram[bank].start >> 20;
+ i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+ i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+ }
+
+ /* same as above but just that we would want cacheable for ocram too */
+ i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+}
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support for Arria 10
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (6 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10 Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
` (3 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/ddr/altera/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 824c9fc2ba..b8fc81b20c 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -10,6 +10,7 @@ config TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+ select ALTERA_SDRAM
config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d857..2b28a97f6e 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
- depends on TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (7 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support " Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-16 10:26 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot Marek Vasut
` (2 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a60da85499..acac4a7108 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/*
* SPL
*
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ...... Malloc area
* 0xFFFF_zzzz ...... Global Data
* 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
*/
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
+ CONFIG_SYS_SPL_MALLOC_SIZE + \
+ CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
+
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
@@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/*
* Stack setup
*/
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
+#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
@ 2018-05-16 10:26 ` Ley Foon Tan
0 siblings, 0 replies; 25+ messages in thread
From: Ley Foon Tan @ 2018-05-16 10:26 UTC (permalink / raw)
To: u-boot
On Sun, May 13, 2018 at 4:30 AM, Marek Vasut <marex@denx.de> wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Enable memory allocation in SPL for preparation to enable FAT
> in SPL. Memory allocation is needed by FAT to work properly.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index a60da85499..acac4a7108 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> /*
> * SPL
> *
> - * SRAM Memory layout:
> + * SRAM Memory layout for gen 5:
> *
> * 0xFFFF_0000 ...... Start of SRAM
> * 0xFFFF_xxxx ...... Top of stack (grows down)
> * 0xFFFF_yyyy ...... Malloc area
> * 0xFFFF_zzzz ...... Global Data
> * 0xFFFF_FF00 ...... End of SRAM
> + *
> + * SRAM Memory layout for Arria 10:
> + * 0xFFE0_0000 ...... Start of SRAM (bottom)
> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
> + * 0xFFEy_yyyy ...... Global Data
> + * 0xFFEz_zzzz ...... Malloc area (grows up to top)
> + * 0xFFE3_FFFF ...... End of SRAM (top)
> */
> #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
>
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +/* SPL memory allocation configuration, this is for FAT implementation */
> +#ifndef CONFIG_SYS_SPL_MALLOC_START
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
> + CONFIG_SYS_SPL_MALLOC_SIZE + \
> + CONFIG_SYS_INIT_RAM_ADDR)
> +#endif
> +#endif
> +
> /* SPL SDMMC boot support */
> #ifdef CONFIG_SPL_MMC_SUPPORT
> #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
> @@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> /*
> * Stack setup
> */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
> +#endif
>
> /* Extra Environment */
> #ifndef CONFIG_SPL_BUILD
> --
> 2.16.2
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (8 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot Marek Vasut
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/board.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 38e12a41a3..6e0b4b3c4e 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -7,7 +7,9 @@
#include <common.h>
#include <errno.h>
+#include <fdtdec.h>
#include <asm/arch/reset_manager.h>
+#include <asm/arch/clock_manager.h>
#include <asm/io.h>
#include <usb.h>
@@ -25,6 +27,11 @@ int board_init(void)
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+ /* configuring the clock based on handoff */
+ cm_basic_init(gd->fdt_blob);
+#endif
+
return 0;
}
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (9 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot Marek Vasut
@ 2018-05-12 20:30 ` Marek Vasut
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
11 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-12 20:30 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
SoC FPGA info is required in both SPL and U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/board.c | 4 ++++
arch/arm/mach-socfpga/misc_arria10.c | 5 -----
arch/arm/mach-socfpga/spl.c | 6 ++++++
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 6e0b4b3c4e..189e12a668 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -10,6 +10,7 @@
#include <fdtdec.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
#include <asm/io.h>
#include <usb.h>
@@ -30,6 +31,9 @@ int board_init(void)
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
#endif
return 0;
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index e1d80a5a76..47a9d50ef1 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -104,11 +104,6 @@ int arch_early_init_r(void)
/* assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
- /* configuring the clock based on handoff */
- /* TODO: Add call to cm_basic_init() */
-
- /* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
return 0;
}
#else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 515832031a..0c9d7388e6 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -14,6 +14,7 @@
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/scu.h>
@@ -191,6 +192,11 @@ void spl_board_init(void)
/* enable console uart printing */
preloader_console_init();
+
+ WATCHDOG_RESET();
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
}
void board_init_f(ulong dummy)
--
2.16.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
` (10 preceding siblings ...)
2018-05-12 20:30 ` [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot Marek Vasut
@ 2018-05-17 4:38 ` Chee, Tien Fong
2018-05-17 8:24 ` Marek Vasut
11 siblings, 1 reply; 25+ messages in thread
From: Chee, Tien Fong @ 2018-05-17 4:38 UTC (permalink / raw)
To: u-boot
On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> The A10 clock manager parsed DT bindings generated by Quartus the
> bsp-editor to configure the A10 clocks. Sadly, those DT bindings
> changed at some point. The clock manager patch used the old ones,
> this patch replaces the bindings parser with one for the new set.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/mach-socfpga/clock_manager_arria10.c | 158
> ++++++++++++++-------
> .../include/mach/clock_manager_arria10.h | 2 +-
> 2 files changed, 111 insertions(+), 49 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> b/arch/arm/mach-socfpga/clock_manager_arria10.c
> index 4ee6a82b5f..defa2f6261 100644
> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> @@ -9,6 +9,9 @@
> #include <dm.h>
> #include <asm/arch/clock_manager.h>
>
> +static const struct socfpga_clock_manager *clock_manager_base =
> + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> +
> static u32 eosc1_hz;
> static u32 cb_intosc_hz;
> static u32 f2s_free_hz;
> @@ -64,89 +67,150 @@ struct perpll_cfg {
> u32 cntr8clk_cnt;
> u32 cntr8clk_src;
> u32 cntr9clk_cnt;
> + u32 cntr9clk_src;
Why add this? I believe this is not exist.
> u32 emacctl_emac0sel;
> u32 emacctl_emac1sel;
> u32 emacctl_emac2sel;
> u32 gpiodiv_gpiodbclk;
> };
>
> -struct alteragrp_cfg {
> - u32 nocclk;
> - u32 mpuclk;
> +struct strtou32 {
> + const char *str;
> + const u32 val;
> };
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> +static const struct strtou32 mainpll_cfg_tab[] = {
> + { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
> + { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
> + { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
> + { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
> + { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
> + { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
> + { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
> + { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt)
> },
> + { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt)
> },
> + { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt)
> },
> + { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt)
> },
> + { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt)
> },
> + { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt)
> },
> + { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src)
> },
> + { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt)
> },
> + { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt)
> },
> + { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src)
> },
> + { "cntr15clk-cnt", offsetof(struct mainpll_cfg,
> cntr15clk_cnt) },
> + { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg,
> nocdiv_l4mainclk) },
> + { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg,
> nocdiv_l4mpclk) },
> + { "nocdiv-l4spclk", offsetof(struct mainpll_cfg,
> nocdiv_l4spclk) },
> + { "nocdiv-csatclk", offsetof(struct mainpll_cfg,
> nocdiv_csatclk) },
> + { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg,
> nocdiv_cstraceclk) },
> + { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg,
> nocdiv_cspdbclk) },
> +};
> +
> +static const struct strtou32 perpll_cfg_tab[] = {
> + { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
> + { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
> + { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
> + { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt)
> },
> + { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src)
> },
> + { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt)
> },
> + { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src)
> },
> + { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt)
> },
> + { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src)
> },
> + { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt)
> },
> + { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src)
> },
> + { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt)
> },
> + { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src)
> },
> + { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt)
> },
> + { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt)
> },
> + { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src)
> },
> + { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt)
> },
> + { "emacctl-emac0sel", offsetof(struct perpll_cfg,
> emacctl_emac0sel) },
> + { "emacctl-emac1sel", offsetof(struct perpll_cfg,
> emacctl_emac1sel) },
> + { "emacctl-emac2sel", offsetof(struct perpll_cfg,
> emacctl_emac2sel) },
> + { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg,
> gpiodiv_gpiodbclk) },
> +};
> +
> +static const struct strtou32 alteragrp_cfg_tab[] = {
> + { "nocclk", offsetof(struct mainpll_cfg, nocclk) },
> + { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
> +};
> +
> +struct strtopu32 {
> + const char *str;
> + u32 *p;
> +};
> +
> +const struct strtopu32 dt_to_val[] = {
> + { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
> + { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz},
> + { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
> +};
>
> -static int of_to_struct(const void *blob, int node, int cfg_len,
> void *cfg)
> +static int of_to_struct(const void *blob, int node, const struct
> strtou32 *cfg_tab,
> + int cfg_tab_len, void *cfg)
> {
> - if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
> - (u32 *)cfg, cfg_len)) {
> - /* could not find required property */
> - return -EINVAL;
> + int i;
> + u32 val;
> +
> + for (i = 0; i < cfg_tab_len; i++) {
> + if (fdtdec_get_int_array(blob, node, cfg_tab[i].str,
> &val, 1)) {
> + /* could not find required property */
> + return -EINVAL;
> + }
> + *(u32 *)(cfg + cfg_tab[i].val) = val;
> }
>
> return 0;
> }
>
> -static int of_get_input_clks(const void *blob, int node, u32 *val)
> +static void of_get_input_clks(const void *blob)
> {
> - *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
> - if (!*val)
> - return -EINVAL;
> + int node, i;
>
> - return 0;
> + for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
> + node = fdt_path_offset(blob, dt_to_val[i].str);
> +
> + if (node < 0)
> + continue;
> +
> + fdtdec_get_int_array(blob, node, "clock-frequency",
> + dt_to_val[i].p, 1);
> + }
> }
>
> static int of_get_clk_cfg(const void *blob, struct mainpll_cfg
> *main_cfg,
> - struct perpll_cfg *per_cfg,
> - struct alteragrp_cfg *altrgrp_cfg)
> + struct perpll_cfg *per_cfg)
> {
> int node, child, len;
> const char *node_name;
>
> - node = fdtdec_next_compatible(blob, 0,
> COMPAT_ALTERA_SOCFPGA_CLK);
> + of_get_input_clks(blob);
> +
> + node = fdtdec_next_compatible(blob, 0,
> COMPAT_ALTERA_SOCFPGA_CLK_INIT);
> +
> if (node < 0)
> return -EINVAL;
>
> child = fdt_first_subnode(blob, node);
> - if (child < 0)
> - return -EINVAL;
>
> - child = fdt_first_subnode(blob, child);
> if (child < 0)
> return -EINVAL;
>
> node_name = fdt_get_name(blob, child, &len);
>
> while (node_name) {
> - if (!strcmp(node_name, "osc1")) {
> - if (of_get_input_clks(blob, child,
> &eosc1_hz))
> + if (!strcmp(node_name, "mainpll")) {
> + if (of_to_struct(blob, child,
> mainpll_cfg_tab,
> + ARRAY_SIZE(mainpll_cfg_tab)
> , main_cfg))
> return -EINVAL;
> - } else if (!strcmp(node_name, "cb_intosc_ls_clk")) {
> - if (of_get_input_clks(blob, child,
> &cb_intosc_hz))
> + } else if (!strcmp(node_name, "perpll")) {
> + if (of_to_struct(blob, child,
> perpll_cfg_tab,
> + ARRAY_SIZE(perpll_cfg_tab),
> per_cfg))
> return -EINVAL;
> - } else if (!strcmp(node_name, "f2s_free_clk")) {
> - if (of_get_input_clks(blob, child,
> &f2s_free_hz))
> + } else if (!strcmp(node_name, "alteragrp")) {
> + if (of_to_struct(blob, child,
> alteragrp_cfg_tab,
> + ARRAY_SIZE(alteragrp_cfg_ta
> b), main_cfg))
> return -EINVAL;
> - } else if (!strcmp(node_name, "main_pll")) {
> - if (of_to_struct(blob, child,
> - sizeof(*main_cfg)/sizeof(u3
> 2),
> - main_cfg))
> - return -EINVAL;
> - } else if (!strcmp(node_name, "periph_pll")) {
> - if (of_to_struct(blob, child,
> - sizeof(*per_cfg)/sizeof(u32
> ),
> - per_cfg))
> - return -EINVAL;
> - } else if (!strcmp(node_name, "altera")) {
> - if (of_to_struct(blob, child,
> - sizeof(*altrgrp_cfg)/sizeof
> (u32),
> - altrgrp_cfg))
> - return -EINVAL;
> -
> - main_cfg->mpuclk = altrgrp_cfg->mpuclk;
> - main_cfg->nocclk = altrgrp_cfg->nocclk;
> }
> child = fdt_next_subnode(blob, child);
>
> @@ -878,15 +942,13 @@ int cm_basic_init(const void *blob)
> {
> struct mainpll_cfg main_cfg;
> struct perpll_cfg per_cfg;
> - struct alteragrp_cfg altrgrp_cfg;
> int rval;
>
> /* initialize to zero for use case of optional node */
> memset(&main_cfg, 0, sizeof(main_cfg));
> memset(&per_cfg, 0, sizeof(per_cfg));
> - memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg));
>
> - rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg,
> &altrgrp_cfg);
> + rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
> if (rval)
> return rval;
>
> diff --git a/arch/arm/mach-
> socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-
> socfpga/include/mach/clock_manager_arria10.h
> index a3289ee2da..cb2306e5bc 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> @@ -107,7 +107,7 @@ unsigned int cm_get_spi_controller_clk_hz(void);
>
> #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
> #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
> -#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK
> | \
> +#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK
> | \
> CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
>
> /* value */
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
@ 2018-05-17 8:24 ` Marek Vasut
2018-05-17 8:44 ` Chee, Tien Fong
0 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-17 8:24 UTC (permalink / raw)
To: u-boot
On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
>> The A10 clock manager parsed DT bindings generated by Quartus the
>> bsp-editor to configure the A10 clocks. Sadly, those DT bindings
>> changed at some point. The clock manager patch used the old ones,
>> this patch replaces the bindings parser with one for the new set.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Chin Liang See <chin.liang.see@intel.com>
>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> arch/arm/mach-socfpga/clock_manager_arria10.c | 158
>> ++++++++++++++-------
>> .../include/mach/clock_manager_arria10.h | 2 +-
>> 2 files changed, 111 insertions(+), 49 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>> index 4ee6a82b5f..defa2f6261 100644
>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>> @@ -9,6 +9,9 @@
>> #include <dm.h>
>> #include <asm/arch/clock_manager.h>
>>
>> +static const struct socfpga_clock_manager *clock_manager_base =
>> + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>> +
>> static u32 eosc1_hz;
>> static u32 cb_intosc_hz;
>> static u32 f2s_free_hz;
>> @@ -64,89 +67,150 @@ struct perpll_cfg {
>> u32 cntr8clk_cnt;
>> u32 cntr8clk_src;
>> u32 cntr9clk_cnt;
>> + u32 cntr9clk_src;
> Why add this? I believe this is not exist.
It exists in the altera sources and it matches the pattern. What do you
mean by "this is not exist" ?
>> u32 emacctl_emac0sel;
>> u32 emacctl_emac1sel;
>> u32 emacctl_emac2sel;
>> u32 gpiodiv_gpiodbclk;
>> };
>>
[...]
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-17 8:24 ` Marek Vasut
@ 2018-05-17 8:44 ` Chee, Tien Fong
2018-05-17 9:38 ` Marek Vasut
0 siblings, 1 reply; 25+ messages in thread
From: Chee, Tien Fong @ 2018-05-17 8:44 UTC (permalink / raw)
To: u-boot
On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
> On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> >
> > On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> > >
> > > The A10 clock manager parsed DT bindings generated by Quartus the
> > > bsp-editor to configure the A10 clocks. Sadly, those DT bindings
> > > changed at some point. The clock manager patch used the old ones,
> > > this patch replaces the bindings parser with one for the new set.
> > >
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > ---
> > > arch/arm/mach-socfpga/clock_manager_arria10.c | 158
> > > ++++++++++++++-------
> > > .../include/mach/clock_manager_arria10.h | 2 +-
> > > 2 files changed, 111 insertions(+), 49 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > index 4ee6a82b5f..defa2f6261 100644
> > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > @@ -9,6 +9,9 @@
> > > #include <dm.h>
> > > #include <asm/arch/clock_manager.h>
> > >
> > > +static const struct socfpga_clock_manager *clock_manager_base =
> > > + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > > +
> > > static u32 eosc1_hz;
> > > static u32 cb_intosc_hz;
> > > static u32 f2s_free_hz;
> > > @@ -64,89 +67,150 @@ struct perpll_cfg {
> > > u32 cntr8clk_cnt;
> > > u32 cntr8clk_src;
> > > u32 cntr9clk_cnt;
> > > + u32 cntr9clk_src;
> > Why add this? I believe this is not exist.
> It exists in the altera sources and it matches the pattern. What do
> you
> mean by "this is not exist" ?
>
we don't have cntr9clk_src in perpll.
> >
> > >
> > > u32 emacctl_emac0sel;
> > > u32 emacctl_emac1sel;
> > > u32 emacctl_emac2sel;
> > > u32 gpiodiv_gpiodbclk;
> > > };
> > >
> [...]
>
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-17 8:44 ` Chee, Tien Fong
@ 2018-05-17 9:38 ` Marek Vasut
2018-05-18 4:41 ` Chee, Tien Fong
0 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-17 9:38 UTC (permalink / raw)
To: u-boot
On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
> On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
>> On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
>>>
>>> On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
>>>>
>>>> The A10 clock manager parsed DT bindings generated by Quartus the
>>>> bsp-editor to configure the A10 clocks. Sadly, those DT bindings
>>>> changed at some point. The clock manager patch used the old ones,
>>>> this patch replaces the bindings parser with one for the new set.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>> ---
>>>> arch/arm/mach-socfpga/clock_manager_arria10.c | 158
>>>> ++++++++++++++-------
>>>> .../include/mach/clock_manager_arria10.h | 2 +-
>>>> 2 files changed, 111 insertions(+), 49 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> index 4ee6a82b5f..defa2f6261 100644
>>>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> @@ -9,6 +9,9 @@
>>>> #include <dm.h>
>>>> #include <asm/arch/clock_manager.h>
>>>>
>>>> +static const struct socfpga_clock_manager *clock_manager_base =
>>>> + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>>>> +
>>>> static u32 eosc1_hz;
>>>> static u32 cb_intosc_hz;
>>>> static u32 f2s_free_hz;
>>>> @@ -64,89 +67,150 @@ struct perpll_cfg {
>>>> u32 cntr8clk_cnt;
>>>> u32 cntr8clk_src;
>>>> u32 cntr9clk_cnt;
>>>> + u32 cntr9clk_src;
>>> Why add this? I believe this is not exist.
>> It exists in the altera sources and it matches the pattern. What do
>> you
>> mean by "this is not exist" ?
>>
> we don't have cntr9clk_src in perpll.
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_manager.c#L229
You do ...
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-17 9:38 ` Marek Vasut
@ 2018-05-18 4:41 ` Chee, Tien Fong
2018-05-18 7:50 ` Marek Vasut
0 siblings, 1 reply; 25+ messages in thread
From: Chee, Tien Fong @ 2018-05-18 4:41 UTC (permalink / raw)
To: u-boot
On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
> On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
> > >
> > > On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > The A10 clock manager parsed DT bindings generated by Quartus
> > > > > the
> > > > > bsp-editor to configure the A10 clocks. Sadly, those DT
> > > > > bindings
> > > > > changed at some point. The clock manager patch used the old
> > > > > ones,
> > > > > this patch replaces the bindings parser with one for the new
> > > > > set.
> > > > >
> > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > ---
> > > > > arch/arm/mach-socfpga/clock_manager_arria10.c | 158
> > > > > ++++++++++++++-------
> > > > > .../include/mach/clock_manager_arria10.h | 2 +-
> > > > > 2 files changed, 111 insertions(+), 49 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > index 4ee6a82b5f..defa2f6261 100644
> > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > @@ -9,6 +9,9 @@
> > > > > #include <dm.h>
> > > > > #include <asm/arch/clock_manager.h>
> > > > >
> > > > > +static const struct socfpga_clock_manager
> > > > > *clock_manager_base =
> > > > > + (struct socfpga_clock_manager
> > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > +
> > > > > static u32 eosc1_hz;
> > > > > static u32 cb_intosc_hz;
> > > > > static u32 f2s_free_hz;
> > > > > @@ -64,89 +67,150 @@ struct perpll_cfg {
> > > > > u32 cntr8clk_cnt;
> > > > > u32 cntr8clk_src;
> > > > > u32 cntr9clk_cnt;
> > > > > + u32 cntr9clk_src;
> > > > Why add this? I believe this is not exist.
> > > It exists in the altera sources and it matches the pattern. What
> > > do
> > > you
> > > mean by "this is not exist" ?
> > >
> > we don't have cntr9clk_src in perpll.
> https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v201
> 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_manager
> .c#L229
>
That is the bug, and i have already fixed it in mainstream
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga/clock_m
anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=HEAD#l11
4
> You do ...
>
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-18 4:41 ` Chee, Tien Fong
@ 2018-05-18 7:50 ` Marek Vasut
2018-05-18 8:39 ` Chee, Tien Fong
0 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-18 7:50 UTC (permalink / raw)
To: u-boot
On 05/18/2018 06:41 AM, Chee, Tien Fong wrote:
> On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
>> On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
>>>>
>>>> On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> The A10 clock manager parsed DT bindings generated by Quartus
>>>>>> the
>>>>>> bsp-editor to configure the A10 clocks. Sadly, those DT
>>>>>> bindings
>>>>>> changed at some point. The clock manager patch used the old
>>>>>> ones,
>>>>>> this patch replaces the bindings parser with one for the new
>>>>>> set.
>>>>>>
>>>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>> ---
>>>>>> arch/arm/mach-socfpga/clock_manager_arria10.c | 158
>>>>>> ++++++++++++++-------
>>>>>> .../include/mach/clock_manager_arria10.h | 2 +-
>>>>>> 2 files changed, 111 insertions(+), 49 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>> index 4ee6a82b5f..defa2f6261 100644
>>>>>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>> @@ -9,6 +9,9 @@
>>>>>> #include <dm.h>
>>>>>> #include <asm/arch/clock_manager.h>
>>>>>>
>>>>>> +static const struct socfpga_clock_manager
>>>>>> *clock_manager_base =
>>>>>> + (struct socfpga_clock_manager
>>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>> +
>>>>>> static u32 eosc1_hz;
>>>>>> static u32 cb_intosc_hz;
>>>>>> static u32 f2s_free_hz;
>>>>>> @@ -64,89 +67,150 @@ struct perpll_cfg {
>>>>>> u32 cntr8clk_cnt;
>>>>>> u32 cntr8clk_src;
>>>>>> u32 cntr9clk_cnt;
>>>>>> + u32 cntr9clk_src;
>>>>> Why add this? I believe this is not exist.
>>>> It exists in the altera sources and it matches the pattern. What
>>>> do
>>>> you
>>>> mean by "this is not exist" ?
>>>>
>>> we don't have cntr9clk_src in perpll.
>> https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v201
>> 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_manager
>> .c#L229
>>
> That is the bug, and i have already fixed it in mainstream
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga/clock_m
> anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=HEAD#l11
> 4
So the hardware really isn't symmetric in that way ? (why is this not
fixed in the old altera for of u-boot then?)
The a10_5v4 doesn't even list clock 9 at all. Why ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-18 7:50 ` Marek Vasut
@ 2018-05-18 8:39 ` Chee, Tien Fong
2018-05-18 8:42 ` Marek Vasut
0 siblings, 1 reply; 25+ messages in thread
From: Chee, Tien Fong @ 2018-05-18 8:39 UTC (permalink / raw)
To: u-boot
On Fri, 2018-05-18 at 09:50 +0200, Marek Vasut wrote:
> On 05/18/2018 06:41 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
> > >
> > > On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > The A10 clock manager parsed DT bindings generated by
> > > > > > > Quartus
> > > > > > > the
> > > > > > > bsp-editor to configure the A10 clocks. Sadly, those DT
> > > > > > > bindings
> > > > > > > changed at some point. The clock manager patch used the
> > > > > > > old
> > > > > > > ones,
> > > > > > > this patch replaces the bindings parser with one for the
> > > > > > > new
> > > > > > > set.
> > > > > > >
> > > > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > > ---
> > > > > > > arch/arm/mach-socfpga/clock_manager_arria10.c | 158
> > > > > > > ++++++++++++++-------
> > > > > > > .../include/mach/clock_manager_arria10.h | 2
> > > > > > > +-
> > > > > > > 2 files changed, 111 insertions(+), 49 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/arm/mach-
> > > > > > > socfpga/clock_manager_arria10.c
> > > > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > index 4ee6a82b5f..defa2f6261 100644
> > > > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > @@ -9,6 +9,9 @@
> > > > > > > #include <dm.h>
> > > > > > > #include <asm/arch/clock_manager.h>
> > > > > > >
> > > > > > > +static const struct socfpga_clock_manager
> > > > > > > *clock_manager_base =
> > > > > > > + (struct socfpga_clock_manager
> > > > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > > > +
> > > > > > > static u32 eosc1_hz;
> > > > > > > static u32 cb_intosc_hz;
> > > > > > > static u32 f2s_free_hz;
> > > > > > > @@ -64,89 +67,150 @@ struct perpll_cfg {
> > > > > > > u32 cntr8clk_cnt;
> > > > > > > u32 cntr8clk_src;
> > > > > > > u32 cntr9clk_cnt;
> > > > > > > + u32 cntr9clk_src;
> > > > > > Why add this? I believe this is not exist.
> > > > > It exists in the altera sources and it matches the pattern.
> > > > > What
> > > > > do
> > > > > you
> > > > > mean by "this is not exist" ?
> > > > >
> > > > we don't have cntr9clk_src in perpll.
> > > https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_
> > > v201
> > > 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_man
> > > ager
> > > .c#L229
> > >
> > That is the bug, and i have already fixed it in mainstream
> > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga/clo
> > ck_m
> > anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=HEAD
> > #l11
> > 4
> So the hardware really isn't symmetric in that way ? (why is this not
> fixed in the old altera for of u-boot then?)
>
I have no idea why the HW was designed in that way. But the latest
hps.xml handoff file which is generated from qsys and quartus tools
based on our golden system reference design, the
i_clk_mgr_perpllgrp.cntr9clk.cnt is listed inside the file.
Our priority is getting the things fixed in mainstream, unless the bugs
in old altera impacts the functionality and board booting up. In the
end, we will get everything upstream and encouraging user to use
mainstream.
> The a10_5v4 doesn't even list clock 9 at all. Why ?
>
This infomation is missing inside the document. Our internal register
mapping document has this listed.
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-18 8:39 ` Chee, Tien Fong
@ 2018-05-18 8:42 ` Marek Vasut
2018-05-18 8:53 ` Chee, Tien Fong
0 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2018-05-18 8:42 UTC (permalink / raw)
To: u-boot
On 05/18/2018 10:39 AM, Chee, Tien Fong wrote:
> On Fri, 2018-05-18 at 09:50 +0200, Marek Vasut wrote:
>> On 05/18/2018 06:41 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
>>>>
>>>> On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> The A10 clock manager parsed DT bindings generated by
>>>>>>>> Quartus
>>>>>>>> the
>>>>>>>> bsp-editor to configure the A10 clocks. Sadly, those DT
>>>>>>>> bindings
>>>>>>>> changed at some point. The clock manager patch used the
>>>>>>>> old
>>>>>>>> ones,
>>>>>>>> this patch replaces the bindings parser with one for the
>>>>>>>> new
>>>>>>>> set.
>>>>>>>>
>>>>>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>>>> ---
>>>>>>>> arch/arm/mach-socfpga/clock_manager_arria10.c | 158
>>>>>>>> ++++++++++++++-------
>>>>>>>> .../include/mach/clock_manager_arria10.h | 2
>>>>>>>> +-
>>>>>>>> 2 files changed, 111 insertions(+), 49 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/mach-
>>>>>>>> socfpga/clock_manager_arria10.c
>>>>>>>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>> index 4ee6a82b5f..defa2f6261 100644
>>>>>>>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>> @@ -9,6 +9,9 @@
>>>>>>>> #include <dm.h>
>>>>>>>> #include <asm/arch/clock_manager.h>
>>>>>>>>
>>>>>>>> +static const struct socfpga_clock_manager
>>>>>>>> *clock_manager_base =
>>>>>>>> + (struct socfpga_clock_manager
>>>>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>>>> +
>>>>>>>> static u32 eosc1_hz;
>>>>>>>> static u32 cb_intosc_hz;
>>>>>>>> static u32 f2s_free_hz;
>>>>>>>> @@ -64,89 +67,150 @@ struct perpll_cfg {
>>>>>>>> u32 cntr8clk_cnt;
>>>>>>>> u32 cntr8clk_src;
>>>>>>>> u32 cntr9clk_cnt;
>>>>>>>> + u32 cntr9clk_src;
>>>>>>> Why add this? I believe this is not exist.
>>>>>> It exists in the altera sources and it matches the pattern.
>>>>>> What
>>>>>> do
>>>>>> you
>>>>>> mean by "this is not exist" ?
>>>>>>
>>>>> we don't have cntr9clk_src in perpll.
>>>> https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_
>>>> v201
>>>> 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_man
>>>> ager
>>>> .c#L229
>>>>
>>> That is the bug, and i have already fixed it in mainstream
>>> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga/clo
>>> ck_m
>>> anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=HEAD
>>> #l11
>>> 4
>> So the hardware really isn't symmetric in that way ? (why is this not
>> fixed in the old altera for of u-boot then?)
>>
> I have no idea why the HW was designed in that way. But the latest
> hps.xml handoff file which is generated from qsys and quartus tools
> based on our golden system reference design, the
> i_clk_mgr_perpllgrp.cntr9clk.cnt is listed inside the file.
>
> Our priority is getting the things fixed in mainstream, unless the bugs
> in old altera impacts the functionality and board booting up. In the
> end, we will get everything upstream and encouraging user to use
> mainstream.
>> The a10_5v4 doesn't even list clock 9 at all. Why ?
>>
> This infomation is missing inside the document. Our internal register
> mapping document has this listed.
Er, since you say it is listed internally, then the cntr9clk_src exists?
I am confused here, really.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-18 8:42 ` Marek Vasut
@ 2018-05-18 8:53 ` Chee, Tien Fong
2018-05-18 8:58 ` Marek Vasut
0 siblings, 1 reply; 25+ messages in thread
From: Chee, Tien Fong @ 2018-05-18 8:53 UTC (permalink / raw)
To: u-boot
On Fri, 2018-05-18 at 10:42 +0200, Marek Vasut wrote:
> On 05/18/2018 10:39 AM, Chee, Tien Fong wrote:
> >
> > On Fri, 2018-05-18 at 09:50 +0200, Marek Vasut wrote:
> > >
> > > On 05/18/2018 06:41 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > The A10 clock manager parsed DT bindings generated by
> > > > > > > > > Quartus
> > > > > > > > > the
> > > > > > > > > bsp-editor to configure the A10 clocks. Sadly, those
> > > > > > > > > DT
> > > > > > > > > bindings
> > > > > > > > > changed at some point. The clock manager patch used
> > > > > > > > > the
> > > > > > > > > old
> > > > > > > > > ones,
> > > > > > > > > this patch replaces the bindings parser with one for
> > > > > > > > > the
> > > > > > > > > new
> > > > > > > > > set.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > > > > ---
> > > > > > > > > arch/arm/mach-socfpga/clock_manager_arria10.c |
> > > > > > > > > 158
> > > > > > > > > ++++++++++++++-------
> > > > > > > > > .../include/mach/clock_manager_arria10.h |
> > > > > > > > > 2
> > > > > > > > > +-
> > > > > > > > > 2 files changed, 111 insertions(+), 49 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/arch/arm/mach-
> > > > > > > > > socfpga/clock_manager_arria10.c
> > > > > > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > > > index 4ee6a82b5f..defa2f6261 100644
> > > > > > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > > > > > @@ -9,6 +9,9 @@
> > > > > > > > > #include <dm.h>
> > > > > > > > > #include <asm/arch/clock_manager.h>
> > > > > > > > >
> > > > > > > > > +static const struct socfpga_clock_manager
> > > > > > > > > *clock_manager_base =
> > > > > > > > > + (struct socfpga_clock_manager
> > > > > > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > > > > > +
> > > > > > > > > static u32 eosc1_hz;
> > > > > > > > > static u32 cb_intosc_hz;
> > > > > > > > > static u32 f2s_free_hz;
> > > > > > > > > @@ -64,89 +67,150 @@ struct perpll_cfg {
> > > > > > > > > u32 cntr8clk_cnt;
> > > > > > > > > u32 cntr8clk_src;
> > > > > > > > > u32 cntr9clk_cnt;
> > > > > > > > > + u32 cntr9clk_src;
> > > > > > > > Why add this? I believe this is not exist.
> > > > > > > It exists in the altera sources and it matches the
> > > > > > > pattern.
> > > > > > > What
> > > > > > > do
> > > > > > > you
> > > > > > > mean by "this is not exist" ?
> > > > > > >
> > > > > > we don't have cntr9clk_src in perpll.
> > > > > https://github.com/altera-opensource/u-boot-socfpga/blob/socf
> > > > > pga_
> > > > > v201
> > > > > 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock
> > > > > _man
> > > > > ager
> > > > > .c#L229
> > > > >
> > > > That is the bug, and i have already fixed it in mainstream
> > > > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga
> > > > /clo
> > > > ck_m
> > > > anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=
> > > > HEAD
> > > > #l11
> > > > 4
> > > So the hardware really isn't symmetric in that way ? (why is this
> > > not
> > > fixed in the old altera for of u-boot then?)
> > >
> > I have no idea why the HW was designed in that way. But the latest
> > hps.xml handoff file which is generated from qsys and quartus tools
> > based on our golden system reference design, the
> > i_clk_mgr_perpllgrp.cntr9clk.cnt is listed inside the file.
> >
> > Our priority is getting the things fixed in mainstream, unless the
> > bugs
> > in old altera impacts the functionality and board booting up. In
> > the
> > end, we will get everything upstream and encouraging user to use
> > mainstream.
> > >
> > > The a10_5v4 doesn't even list clock 9 at all. Why ?
> > >
> > This infomation is missing inside the document. Our internal
> > register
> > mapping document has this listed.
> Er, since you say it is listed internally, then the cntr9clk_src
> exists?
> I am confused here, really.
>
cntr9clk_src is not exists, but cntr9clk_cnt is exists.
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
2018-05-18 8:53 ` Chee, Tien Fong
@ 2018-05-18 8:58 ` Marek Vasut
0 siblings, 0 replies; 25+ messages in thread
From: Marek Vasut @ 2018-05-18 8:58 UTC (permalink / raw)
To: u-boot
On 05/18/2018 10:53 AM, Chee, Tien Fong wrote:
> On Fri, 2018-05-18 at 10:42 +0200, Marek Vasut wrote:
>> On 05/18/2018 10:39 AM, Chee, Tien Fong wrote:
>>>
>>> On Fri, 2018-05-18 at 09:50 +0200, Marek Vasut wrote:
>>>>
>>>> On 05/18/2018 06:41 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> The A10 clock manager parsed DT bindings generated by
>>>>>>>>>> Quartus
>>>>>>>>>> the
>>>>>>>>>> bsp-editor to configure the A10 clocks. Sadly, those
>>>>>>>>>> DT
>>>>>>>>>> bindings
>>>>>>>>>> changed at some point. The clock manager patch used
>>>>>>>>>> the
>>>>>>>>>> old
>>>>>>>>>> ones,
>>>>>>>>>> this patch replaces the bindings parser with one for
>>>>>>>>>> the
>>>>>>>>>> new
>>>>>>>>>> set.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>>>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>>>>>> ---
>>>>>>>>>> arch/arm/mach-socfpga/clock_manager_arria10.c |
>>>>>>>>>> 158
>>>>>>>>>> ++++++++++++++-------
>>>>>>>>>> .../include/mach/clock_manager_arria10.h |
>>>>>>>>>> 2
>>>>>>>>>> +-
>>>>>>>>>> 2 files changed, 111 insertions(+), 49 deletions(-)
>>>>>>>>>>
>>>>>>>>>> diff --git a/arch/arm/mach-
>>>>>>>>>> socfpga/clock_manager_arria10.c
>>>>>>>>>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>>>> index 4ee6a82b5f..defa2f6261 100644
>>>>>>>>>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>>>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>>>>>>>> @@ -9,6 +9,9 @@
>>>>>>>>>> #include <dm.h>
>>>>>>>>>> #include <asm/arch/clock_manager.h>
>>>>>>>>>>
>>>>>>>>>> +static const struct socfpga_clock_manager
>>>>>>>>>> *clock_manager_base =
>>>>>>>>>> + (struct socfpga_clock_manager
>>>>>>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>>>>>> +
>>>>>>>>>> static u32 eosc1_hz;
>>>>>>>>>> static u32 cb_intosc_hz;
>>>>>>>>>> static u32 f2s_free_hz;
>>>>>>>>>> @@ -64,89 +67,150 @@ struct perpll_cfg {
>>>>>>>>>> u32 cntr8clk_cnt;
>>>>>>>>>> u32 cntr8clk_src;
>>>>>>>>>> u32 cntr9clk_cnt;
>>>>>>>>>> + u32 cntr9clk_src;
>>>>>>>>> Why add this? I believe this is not exist.
>>>>>>>> It exists in the altera sources and it matches the
>>>>>>>> pattern.
>>>>>>>> What
>>>>>>>> do
>>>>>>>> you
>>>>>>>> mean by "this is not exist" ?
>>>>>>>>
>>>>>>> we don't have cntr9clk_src in perpll.
>>>>>> https://github.com/altera-opensource/u-boot-socfpga/blob/socf
>>>>>> pga_
>>>>>> v201
>>>>>> 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock
>>>>>> _man
>>>>>> ager
>>>>>> .c#L229
>>>>>>
>>>>> That is the bug, and i have already fixed it in mainstream
>>>>> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga
>>>>> /clo
>>>>> ck_m
>>>>> anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=
>>>>> HEAD
>>>>> #l11
>>>>> 4
>>>> So the hardware really isn't symmetric in that way ? (why is this
>>>> not
>>>> fixed in the old altera for of u-boot then?)
>>>>
>>> I have no idea why the HW was designed in that way. But the latest
>>> hps.xml handoff file which is generated from qsys and quartus tools
>>> based on our golden system reference design, the
>>> i_clk_mgr_perpllgrp.cntr9clk.cnt is listed inside the file.
>>>
>>> Our priority is getting the things fixed in mainstream, unless the
>>> bugs
>>> in old altera impacts the functionality and board booting up. In
>>> the
>>> end, we will get everything upstream and encouraging user to use
>>> mainstream.
>>>>
>>>> The a10_5v4 doesn't even list clock 9 at all. Why ?
>>>>
>>> This infomation is missing inside the document. Our internal
>>> register
>>> mapping document has this listed.
>> Er, since you say it is listed internally, then the cntr9clk_src
>> exists?
>> I am confused here, really.
>>
> cntr9clk_src is not exists, but cntr9clk_cnt is exists.
Where is that documented and why is every single source file I find
telling me something different ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread