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From: Sricharan R <sricharan@codeaurora.org>
To: mark.rutland@arm.com, robh@kernel.org, sudeep.holla@arm.com,
	linux@arm.linux.org.uk, ctatlor97@gmail.com, rjw@rjwysocki.net,
	viresh.kumar@linaro.org, mturquette@baylibre.com,
	linux-pm@vger.kernel.org, sboyd@codeaurora.org,
	linux@armlinux.org.uk, thierry.escande@linaro.org,
	linux-kernel@vger.kernel.org, david.brown@linaro.org,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	andy.gross@linaro.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	niklas.cassel@linaro.org
Cc: sricharan@codeaurora.org
Subject: [PATCH 09/14] dt-bindings: arm: Document qcom,kpss-gcc
Date: Mon, 13 Aug 2018 19:06:02 +0530	[thread overview]
Message-ID: <1534167367-17545-10-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1534167367-17545-1-git-send-email-sricharan@codeaurora.org>

From: Stephen Boyd <sboyd@codeaurora.org>

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 19 ++++++++++
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  | 44 ++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
 		    the register region. An optional second element specifies
 		    the base address and size of the alias register region.
 
+- clocks:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: reference to the pll parents.
+
+- clock-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: optional
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpuX_aux where X is a
+		    CPU number starting at 0.
+
 Example:
 
 	clock-controller@2088000 {
 		compatible = "qcom,kpss-acc-v2";
 		reg = <0x02088000 0x1000>,
 		      <0x02008000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu0_aux";
 	};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 0000000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be one of the following. The generic compatible
+			"qcom,kpss-gcc" should also be included.
+			"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: base address and size of the register region
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the pll parents.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: required
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpu_l2_aux indicating
+		    an L2 cache auxiliary clock.
+
+Example:
+
+	l2cc: clock-controller@2011000 {
+		compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+		reg = <0x2011000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu_l2_aux";
+	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

WARNING: multiple messages have this Message-ID (diff)
From: sricharan@codeaurora.org (Sricharan R)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/14] dt-bindings: arm: Document qcom,kpss-gcc
Date: Mon, 13 Aug 2018 19:06:02 +0530	[thread overview]
Message-ID: <1534167367-17545-10-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1534167367-17545-1-git-send-email-sricharan@codeaurora.org>

From: Stephen Boyd <sboyd@codeaurora.org>

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 19 ++++++++++
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  | 44 ++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
 		    the register region. An optional second element specifies
 		    the base address and size of the alias register region.
 
+- clocks:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: reference to the pll parents.
+
+- clock-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: optional
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpuX_aux where X is a
+		    CPU number starting at 0.
+
 Example:
 
 	clock-controller at 2088000 {
 		compatible = "qcom,kpss-acc-v2";
 		reg = <0x02088000 0x1000>,
 		      <0x02008000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu0_aux";
 	};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 0000000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be one of the following. The generic compatible
+			"qcom,kpss-gcc" should also be included.
+			"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: base address and size of the register region
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the pll parents.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: required
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpu_l2_aux indicating
+		    an L2 cache auxiliary clock.
+
+Example:
+
+	l2cc: clock-controller at 2011000 {
+		compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+		reg = <0x2011000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu_l2_aux";
+	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2018-08-13 13:36 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-13 13:35 [PATCH V11 00/14] Krait clocks + Krait CPUfreq Sricharan R
2018-08-13 13:35 ` Sricharan R
2018-08-13 13:35 ` [PATCH 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:35 ` [PATCH 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:35 ` [PATCH 03/14] clk: qcom: Add HFPLL driver Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:35 ` [PATCH 04/14] dt-bindings: clock: Document qcom,hfpll Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:35 ` [PATCH 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:35 ` [PATCH 06/14] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
2018-08-13 13:35   ` Sricharan R
2018-08-13 13:36 ` [PATCH 07/14] clk: qcom: Add support for Krait clocks Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` [PATCH 08/14] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` Sricharan R [this message]
2018-08-13 13:36   ` [PATCH 09/14] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
2018-08-13 13:36 ` [PATCH 10/14] clk: qcom: Add Krait clock controller driver Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` [PATCH 11/14] dt-bindings: clock: Document qcom,krait-cc Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` [PATCH 12/14] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` [PATCH 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
2018-08-13 13:36   ` Sricharan R
2018-08-13 13:36 ` [PATCH 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
2018-08-13 13:36   ` Sricharan R

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