* [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT
@ 2018-09-13 22:15 Anusha Srivatsa
2018-09-13 22:40 ` Paulo Zanoni
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Anusha Srivatsa @ 2018-09-13 22:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
We were using the default CFGCR0/1 instead of using
TBT specific CFGCR0 and CFGCR1 registers during
PLL sequence.
Add missing TBTPLL_CFGCR0/1 registers and plumb
them in the existing PLL sequence.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jose Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 ++++++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4948b352bf4c..e299ce7210fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9552,11 +9552,13 @@ enum skl_power_gate {
#define _ICL_DPLL0_CFGCR0 0x164000
#define _ICL_DPLL1_CFGCR0 0x164080
+#define ICL_TBTPLL_CFGCR0 _MMIO(0x164100)
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
_ICL_DPLL1_CFGCR0)
#define _ICL_DPLL0_CFGCR1 0x164004
#define _ICL_DPLL1_CFGCR1 0x164084
+#define ICL_TBTPLL_CFGCR1 _MMIO(0x164080)
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e6cac9225536..5b297445fbf7 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2968,10 +2968,12 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
switch (id) {
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
- case DPLL_ID_ICL_TBTPLL:
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
break;
+ case DPLL_ID_ICL_TBTPLL:
+ hw_state->cfgcr0 = I915_READ(ICL_TBTPLL_CFGCR0);
+ hw_state->cfgcr1 = I915_READ(ICL_TBTPLL_CFGCR1);
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
@@ -3035,6 +3037,16 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
POSTING_READ(ICL_DPLL_CFGCR1(id));
}
+static void icl_tbtpll_write(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+
+ I915_WRITE(ICL_TBTPLL_CFGCR0, hw_state->cfgcr0);
+ I915_WRITE(ICL_TBTPLL_CFGCR1, hw_state->cfgcr1);
+ POSTING_READ(ICL_TBTPLL_CFGCR1);
+}
+
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3107,9 +3119,11 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
switch (id) {
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
- case DPLL_ID_ICL_TBTPLL:
icl_dpll_write(dev_priv, pll);
break;
+ case DPLL_ID_ICL_TBTPLL:
+ icl_tbtpll_write(dev_priv, pll);
+ break;
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT
2018-09-13 22:15 [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT Anusha Srivatsa
@ 2018-09-13 22:40 ` Paulo Zanoni
2018-09-13 23:23 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-09-14 2:38 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Paulo Zanoni @ 2018-09-13 22:40 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
Em Qui, 2018-09-13 às 15:15 -0700, Anusha Srivatsa escreveu:
> We were using the default CFGCR0/1 instead of using
> TBT specific CFGCR0 and CFGCR1 registers during
> PLL sequence.
>
> Add missing TBTPLL_CFGCR0/1 registers and plumb
> them in the existing PLL sequence.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jose Souza <jose.souza@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 ++++++++++++++++--
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4948b352bf4c..e299ce7210fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9552,11 +9552,13 @@ enum skl_power_gate {
>
> #define _ICL_DPLL0_CFGCR0 0x164000
> #define _ICL_DPLL1_CFGCR0 0x164080
> +#define ICL_TBTPLL_CFGCR0 _MMIO(0x164100)
> #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll,
As discussed this in person before, ICL_DPLL_CFGCR0() uses _PICK_EVEN,
which will evaluate to the correct address for TBT.
If you want, you may do this only for informational purposes:
#define _ICL_TBTPLL_CRFCR0 0x164100
but it is not required.
> _ICL_DPLL0_CFGCR0, \
> _ICL_DPLL1_CFGCR0)
>
> #define _ICL_DPLL0_CFGCR1 0x164004
> #define _ICL_DPLL1_CFGCR1 0x164084
> +#define ICL_TBTPLL_CFGCR1 _MMIO(0x164080)
The address added by this patch is just wrong.
For a correct address, the same point as ICL_DPLL_CFGCR0() applies:
_PICK_EVEN does the magic and our code uses the correct value.
There's no need for all that code below. The current code is even valid
in case we add more DPLLs of the same type, as long as their IDs match
the indexing.
> #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll,
> _ICL_DPLL0_CFGCR1, \
> _ICL_DPLL1_CFGCR1)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e6cac9225536..5b297445fbf7 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2968,10 +2968,12 @@ static bool icl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> switch (id) {
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> - case DPLL_ID_ICL_TBTPLL:
> hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> break;
> + case DPLL_ID_ICL_TBTPLL:
> + hw_state->cfgcr0 = I915_READ(ICL_TBTPLL_CFGCR0);
> + hw_state->cfgcr1 = I915_READ(ICL_TBTPLL_CFGCR1);
> case DPLL_ID_ICL_MGPLL1:
> case DPLL_ID_ICL_MGPLL2:
> case DPLL_ID_ICL_MGPLL3:
> @@ -3035,6 +3037,16 @@ static void icl_dpll_write(struct
> drm_i915_private *dev_priv,
> POSTING_READ(ICL_DPLL_CFGCR1(id));
> }
>
> +static void icl_tbtpll_write(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll)
> +{
> + struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
> +
> + I915_WRITE(ICL_TBTPLL_CFGCR0, hw_state->cfgcr0);
> + I915_WRITE(ICL_TBTPLL_CFGCR1, hw_state->cfgcr1);
> + POSTING_READ(ICL_TBTPLL_CFGCR1);
> +}
> +
> static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> @@ -3107,9 +3119,11 @@ static void icl_pll_enable(struct
> drm_i915_private *dev_priv,
> switch (id) {
> case DPLL_ID_ICL_DPLL0:
> case DPLL_ID_ICL_DPLL1:
> - case DPLL_ID_ICL_TBTPLL:
> icl_dpll_write(dev_priv, pll);
> break;
> + case DPLL_ID_ICL_TBTPLL:
> + icl_tbtpll_write(dev_priv, pll);
> + break;
> case DPLL_ID_ICL_MGPLL1:
> case DPLL_ID_ICL_MGPLL2:
> case DPLL_ID_ICL_MGPLL3:
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/tbt: Add CFGCR0/1 registers for TBT
2018-09-13 22:15 [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT Anusha Srivatsa
2018-09-13 22:40 ` Paulo Zanoni
@ 2018-09-13 23:23 ` Patchwork
2018-09-14 2:38 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-09-13 23:23 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tbt: Add CFGCR0/1 registers for TBT
URL : https://patchwork.freedesktop.org/series/49677/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4820 -> Patchwork_10182 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/49677/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10182 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@drv_module_reload@basic-reload:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS
igt@pm_rpm@module-reload:
{fi-cnl-u}: FAIL -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (49 -> 45) ==
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4820 -> Patchwork_10182
CI_DRM_4820: a804643cba4646e18e0e31c9363fdd3c92dca3c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4640: 9a8da36e708f9ed15b20689dfe305e41f9a19008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10182: 42d0861eed82c6f8fac42ba5bc4f6fd88f03d410 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
42d0861eed82 drm/i915/tbt: Add CFGCR0/1 registers for TBT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10182/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/tbt: Add CFGCR0/1 registers for TBT
2018-09-13 22:15 [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT Anusha Srivatsa
2018-09-13 22:40 ` Paulo Zanoni
2018-09-13 23:23 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-09-14 2:38 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-09-14 2:38 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tbt: Add CFGCR0/1 registers for TBT
URL : https://patchwork.freedesktop.org/series/49677/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4820_full -> Patchwork_10182_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10182_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10182_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10182_full:
=== IGT changes ===
==== Warnings ====
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
shard-hsw: PASS -> SKIP +1
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10182_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_color@pipe-b-ctm-max:
shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +68
igt@kms_flip@dpms-vs-vblank-race:
shard-kbl: PASS -> FAIL (fdo#103060)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
==== Possible fixes ====
igt@gem_exec_big:
shard-hsw: TIMEOUT -> PASS
igt@kms_fbcon_fbt@fbc-suspend:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
shard-glk: DMESG-FAIL -> PASS
igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
shard-glk: DMESG-WARN (fdo#105763) -> PASS +3
==== Warnings ====
igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
shard-apl: FAIL (fdo#106510, fdo#105458) -> DMESG-WARN (fdo#103558, fdo#105602)
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105458 https://bugs.freedesktop.org/show_bug.cgi?id=105458
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106510 https://bugs.freedesktop.org/show_bug.cgi?id=106510
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4820 -> Patchwork_10182
CI_DRM_4820: a804643cba4646e18e0e31c9363fdd3c92dca3c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4640: 9a8da36e708f9ed15b20689dfe305e41f9a19008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10182: 42d0861eed82c6f8fac42ba5bc4f6fd88f03d410 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10182/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-09-14 2:38 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2018-09-13 22:15 [PATCH] drm/i915/tbt: Add CFGCR0/1 registers for TBT Anusha Srivatsa
2018-09-13 22:40 ` Paulo Zanoni
2018-09-13 23:23 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-09-14 2:38 ` ✓ Fi.CI.IGT: " Patchwork
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