[U-Boot] [PATCH 3/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Fri, 2018-11-23 at 13:31 +0100, Marek Vasut wrote:
> On 11/23/2018 10:51 AM, Chee, Tien Fong wrote:
> > 
> > On Wed, 2018-11-21 at 15:19 +0100, Marek Vasut wrote:
> > > 
> > > On 11/21/2018 11:41 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add support for loading FPGA bitstream to get DDR up running
> > > > before
> > > > U-Boot is loaded into DDR. Boot device initialization, generic
> > > > firmware
> > > > loader and SPL FAT support are required for this whole
> > > > mechanism to
> > > > work.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/spl_a10.c |   49
> > > > ++++++++++++++++++++++++++++++++++++++-
> > > >  common/spl/spl_mmc.c            |    2 +-
> > > >  include/mmc.h                   |    1 +
> > > >  3 files changed, 50 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> > > > socfpga/spl_a10.c
> > > > index 3ea64f7..67a4fac 100644
> > > > --- a/arch/arm/mach-socfpga/spl_a10.c
> > > > +++ b/arch/arm/mach-socfpga/spl_a10.c
> > > > @@ -1,6 +1,6 @@
> > > >  // SPDX-License-Identifier: GPL-2.0+
> > > >  /*
> > > > - *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + *  Copyright (C) 2012-2018 Altera Corporation <www.altera.com
> > > > >
> > > >   */
> > > >  
> > > >  #include <common.h>
> > > > @@ -23,6 +23,10 @@
> > > >  #include <fdtdec.h>
> > > >  #include <watchdog.h>
> > > >  #include <asm/arch/pinmux.h>
> > > > +#include <asm/arch/fpga_manager.h>
> > > > +#include <mmc.h>
> > > > +
> > > > +#define RBF	0
> > > >  
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > >  
> > > > @@ -73,6 +77,49 @@ void spl_board_init(void)
> > > >  	WATCHDOG_RESET();
> > > >  
> > > >  	arch_early_init_r();
> > > > +
> > > > +	/* If the full FPGA is already loaded, ie.from EPCQ,
> > > > config fpga pins */
> > > > +	if (is_fpgamgr_user_mode()) {
> > > > +		config_pins(gd->fdt_blob, "shared");
> > > > +		config_pins(gd->fdt_blob, "fpga");
> > > > +	} else if (!is_fpgamgr_early_user_mode()) {
> > > > +		/* Program IOSSM(early IO release) or full
> > > > FPGA */
> > > > +		fpga_fs_info fpga_fsinfo;
> > > > +		char buf[16 * 1024]
> > > > __aligned(ARCH_DMA_MINALIGN);
> > > > +		struct spl_boot_device bootdev;
> > > > +		int len = 0;
> > > > +
> > > > +		bootdev.boot_device = spl_boot_device();
> > > > +
> > > > +		/* Init MMC driver before reading FPGA
> > > > bitstream
> > > > from flash */
> > > > +		if (bootdev.boot_device == BOOT_DEVICE_MMC1) {
> > > > +			struct mmc *mmc = NULL;
> > > > +			int err = 0;
> > > > +
> > > > +			err = spl_mmc_find_device(&mmc,
> > > > bootdev.boot_device);
> > > > +			if (err)
> > > > +				return;
> > > > +
> > > > +			err = mmc_init(mmc);
> > > I thought all this backend specific stuff would be hidden in the
> > > FW
> > > loader.
> > The backend supported by FW loader is up to generic file system
> > interface layer. flash driver init is expected done by SPL/U-Boot
> > common init sequence framwork or user. Unfortunately, fw loader
> > need to
> > access flash before init sequence.
> This is actually accessing eMMC though , not flash . If we need this
> huge boilerplate code every time we use the FW loader, than the FW
> loader needs fixing. I can understand the spl_boot_device() being
> outside of the FW loader, but not the mmc_init() and co.
I can explore the posibility of adding the flash int mechanism into the
fm loader probe function.
>